.pof file. initial capital letters indicates keyboard keys and menu names. for example, delete key and the options menu. ?subheading title? quotation marks indicate references to sections within a document and titles of quartus ii help topics. for example, ?typographic conventions.?
info?2 additional information hardcopy iv device handbook, volume 1 ? january 2010 altera corporation courier type indicates signal, port, register, bit, block, and primitive names. for example, data1 , tdi , and input . active-low signals are denoted by suffix n . for example, resetn . indicates command line commands and anything that must be typed exactly as it appears. for example, c:\qdesigns\tutorial\chiptrip.gdf . also indicates sections of an actual file, such as a report file, references to parts of files (for example, the ahdl keyword subdesign ), and logic function names (for example, tri ). 1., 2., 3., and a., b., c., and so on. numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. bullets indicate a list of items when the sequence of the items is not important. 1 the hand points to information that requires special attention. c a caution calls attention to a condition or possible situation that can damage or destroy the product or your work. w a warning calls attention to a condition or possible situation that can cause you injury. r the angled arrow instructs you to press enter . f the feet direct you to more information about a particular topic. visual cue meaning
101 innovation drive san jose, ca 95134 www.altera.com hardcopy iv device handbook, volume 2 hc4_h5v2-2.1
copyright ? 2010 altera corporation. all rights reserved. altera, the programmable solutions company, the stylized altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of altera corporation in the u.s. and other countries. all other product or service names are the property of their respective holders. altera products are protected under numerous u.s. and foreign patents and pending ap- plications, maskwork rights, and copyrights. altera warrants performance of its semiconductor products to current specification s in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibilit y or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera corporation. altera cu stomers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services .
? january 2010 altera corporation hardcopy iv device handbook, volume 2 contents chapter revision dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v section i. hardcopy iv design flow and prototyping with stratix iv devices revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i-1 chapter 1. hardcopy iv design flow using the quartus ii software hardcopy iv development flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 designing with the stratix iv device first flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 designing with the hardcopy iv device first flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 hardcopy advisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 fpga and hardcopy companion device planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 logic resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 i/o pin and package offering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 memory resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 dsp blocks implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 clock and pll planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 clock networks and pll resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 add pll reconfiguration to altera ip blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 use dedicated clock pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 quartus ii settings for hardcopy iv devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 limit dsp and ram to hardcopy device resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 enable design assistant to run during compile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 i/o assignment settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 physical synthesis optimization settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 timing settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 timing constraints for the timequest timing analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 timequest multicorner timing analysis setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 5 incremental compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 top-down incremental compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 top-down incremental compilation with empty design partitions . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 quartus ii fitter settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 hardcopy design readiness check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 timing closure and verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 timing closure with the timequest timing analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 engineering change order (eco) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 migrating one-to-one changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24 migrating changes that must be implemented differently . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24 hardcopy iv handoff process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26
iv contents hardcopy iv device handbook, volume 2 ? january 2010 altera corporation chapter 2. hardcopy design center implementation process hardcopy iv back-end design flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 design netlist generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 design for testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 clock tree and global signal insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 tie-off connections for unused resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 formal verification of the processed netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 timing and signal integrity driven place and route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 parasitic extraction and timing analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 back-end timing closure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 timing ecos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 formal verification of the post-layout netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 layout verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 design signoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 chapter 3. mapping stratix iv device resources to hardcopy iv devices hardcopy iv and stratix iv mapping options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 summary of differences between hardcopy iv and stratix iv devices . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 designing with hardcopy iv i/os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 mapping hardcopy iv and stratix iv i/os and modular i/o banks . . . . . . . . . . . . . . . . . . . . . . . . 3-9 hardcopy iv supported i/o standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 external memory interface i/os in stratix iv and hardcopy iv devices . . . . . . . . . . . . . . . . . . . . 3-16 mapping stratix iv high-speed differential i/o interfaces with hardcopy iv . . . . . . . . . . . . . . . 3-18 hardcopy iv pll planning and utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 hardcopy iv memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 mlab implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 mlab, m9k, and m144k utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 using jtag features in hardcopy iv devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 power-up and configuration pin compatibility with stratix iv devices . . . . . . . . . . . . . . . . . . . . . . . 3-28 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 chapter 4. matching stratix iv power and configuration requirements with hardcopy iv devices hardcopy iv power-up options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 instant on (no added delay) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 instant on after 50 ms delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 configuration pin compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 examples of mapping a stratix fpga configuration to a hardcopy asic . . . . . . . . . . . . . . . . . . . . . . 4-7 hardcopy iv device replacing a stand-alone stratix iv device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 hardcopy iv device replacing a stratix iv device in a cascaded configuration chain . . . . . . . . 4-8 hardcopy iv device replacing a stratix iv device configured with a microprocessor . . . . . . . . 4-10 hardcopy iv device replacing an fpga configured in a jtag chain . . . . . . . . . . . . . . . . . . . . . 4-11 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 additional information about this handbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info-1 how to contact altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info-1 typographic conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info-1
? january 2010 altera corporation hardcopy iv device handbook, volume 2 chapter revision dates the chapters in this book, hardcopy iv device handbook, volume 2 , were revised on the following dates. where chapters or groups of chapters are available separately, part numbers are listed. chapter 1 hardcopy iv design flow using the quartus ii software revised: january 2010 part number: hiv52001-2.1 chapter 2 hardcopy design center implementation process revised: december 2008 part number: hiv52002-1.0 chapter 3 mapping stratix iv device resources to hardcopy iv devices revised: january 2010 part number: hiv52003-2.1 chapter 4 matching stratix iv power and configuration requirements with hardcopy iv devices revised: june 2009 part number: hiv52004-2.0
vi chapter revision dates hardcopy iv device handbook, volume 2 ? january 2010 altera corporation
? january 2010 altera corporation hardcopy iv device handbook, volume 2 section i. hardcopy iv design flow and prototyping with stratix iv devices this section provides a description of the design flow and the implementation process used by the hardcopy design center. it also provides information about mapping stratix ? iv devices to hardcopy ? iv devices and associated power and configuration requirements. this section includes the following chapters: chapter 1, hardcopy iv design flow using the quartus ii software chapter 2, hardcopy design center implementation process chapter 3, mapping stratix iv device resources to hardcopy iv devices chapter 4, matching stratix iv power and configuration requirements with hardcopy iv devices revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook.
i?2 section i: hardcopy iv design flow and prototyping with stratix iv devices hardcopy iv device handbook, volume 2 ? january 2010 altera corporation
? january 2010 altera corporation hardcopy iv device handbook, volume 2 1. hardcopy iv design flow using the quartus ii software this chapter provides recommendations for hardcopy ? iv development, planning, and settings considerations in the quartus ? ii software. beginning with the quartus ii software version 9.1, both companion and compilation for hardcopy iv asics are supported. during hardcopy iv asic development, the quartus ii software ensures that both the stratix iv fpga and hardcopy iv asic have compatible pins, i/o standards, logic, and other resources. hardcopy iv development flow in the quartus ii software, two methods are available for the hardcopy iv development flow: stratix iv device first flow and hardcopy iv device first flow. stratix iv device first flow?design the stratix iv device first for system functional verification and then create the hardcopy iv companion device. performing system verification early helps reduce overall total project development time. hardcopy iv device first flow?design the hardcopy iv device first and then create the stratix iv companion device for system functional verification. this method more accurately predicts the maximum performance of the hardcopy iv asic during development. if you optimize your design to maximize hardcopy iv asic performance, but are unable to meet your performance requirements with the stratix iv fpga, you can still map your design with decreased performance requirements for in-system verification. 1 whichever design flow you choose for your hardcopy iv development, both the target design and the companion device design must be in one quartus ii project. designing with the stratix iv device first flow the hardcopy iv development flow beginning with the stratix iv prototype is very similar to a traditional stratix iv design flow, but requires that you perform a few additional tasks to map the design to the hardcopy iv companion device: 1. choose a stratix iv device for prototyping. 2. specify a hardcopy iv device for conversion. 3. compile the stratix iv design. 4. create and compile the hardcopy iv companion revision. 5. compare the hardcopy iv companion revision compilation to the stratix iv device compilation. 6. generate the handoff files and reports. 7. archive the design and send it to altera to start the back-end design process. hiv52001-2.1
1?2 chapter 1: hardcopy iv design flow using the quartus ii software hardcopy iv development flow hardcopy iv device handbook, volume 2 ? january 2010 altera corporation figure 1?1 shows the development process for designing with a stratix iv device first and creating a hardcopy iv companion device second. figure 1?1. designing with the stratix iv device first flow prepare stratix iv design archive project for handoff design submission & back-end implementation phase select hardcopy iv companion device review hardcopy advisor apply design constraints compile stratix iv design any violations? any violations? create or overwrite hardcopy iv companion revision compile hardcopy iv companion revision fits in hardcopy iv device? compare stratix iv & hardcopy iv revisions generate handoff report hardcopy iv device development with the stratix iv device first flow in-system verification select a larger hardcopy iv companion device fix violations yes no yes yes no no
chapter 1: hardcopy iv design flow using the quartus ii software 1?3 hardcopy iv development flow ? january 2010 altera corporation hardcopy iv device handbook, volume 2 designing with the hardcopy iv device first flow designing with the hardcopy iv device first flow in the quartus ii software allows you to maximize performance in the hardcopy iv device and map the design to the stratix iv prototype for in-system verification. the performance of the stratix iv prototype may be less than the hardcopy iv device. for this design flow, you must select hardcopy iv as the target device and stratix iv as the companion device in the device settings dialog box. the remaining tasks required to complete your design are outlined in figure 1?2 . the hardcopy advisor adjusts its list of tasks based on the device family you start with to guide you through the development process. figure 1?2. designing with the hardcopy iv device first flow prepare hardcopy iv design design submission & back-end implementation phase select stratix iv companion device review hardcopy advisor apply design constraints compile hardcopy iv design any violations? any violations? create or overwrite stratix iv companion revision compile stratix iv companion revision compare stratix iv & hardcopy iv revisions generate handoff report hardcopy iv device development with the hardcopy iv device first flow in-system verification fix violations yes no yes no archive project for handoff
1?4 chapter 1: hardcopy iv design flow using the quartus ii software hardcopy advisor hardcopy iv device handbook, volume 2 ? january 2010 altera corporation hardcopy advisor the hardcopy advisor in the quartus ii software plays an important role in hardcopy iv device development. the hardcopy advisor guides you through a sequence of recommendations, descriptions, and actions. you can track your design progress, generate the design, and complete the comparison archiving and handoff file that you send to the altera ? hardcopy design center. 1 to develop the hardcopy iv design, run the hardcopy advisor in the quartus ii software after you select the stratix iv device and the hardcopy iv companion devices. to run the hardcopy advisor, on the project menu, point to hardcopy utilities and click hardcopy advisor. fpga and hardcopy companion device planning for both the hardcopy iv device and stratix iv prototype planning, the first stage is to choose the device family, device density, speed grade, and package that best suits your design needs. assuming a stratix iv device first flow, select the stratix iv device and hardcopy iv companion device based on the best resource balance for your design requirements. perform this task before compiling your design in a third-party synthesis tool or the quartus ii software. f for information about the features available in each device density, including logic, memory blocks, multipliers, and phase-locked loops (plls), as well as the various package offerings and i/o pin counts, refer to volume 1 of the hardcopy iv device handbook . logic resources during hardcopy iv device planning, determine the required logic density of the stratix iv prototype and hardcopy iv companion device. devices with more logic resources can implement larger and potentially more complex designs. smaller devices have less logic resources available and benefit from lower power consumption. select a device that meets your design needs with some margin, in case you want to add more logic later in the design cycle. f for information about logic resources in hardcopy iv devices, refer to the hardcopy iv device family overview chapter . i/o pin and package offering hardcopy iv devices offer pin-to-pin compatibility with stratix iv prototypes, making them drop-in replacements for fpgas. due to this compatibility, the same system board and software developed for the fpga prototype can be retained, enabling faster time to market for high volume production. to further reduce the cost for hardcopy devices, hardcopy e devices offer non-socket replacement mapping. for example, you can map the ep4se230 device in the 780-pin fbga package to the hc4e25 device in the 484-pin fbga package. because the pinout for the two packages are not the same, a separate board design is required for the stratix iv device and the hardcopy iv e device.
chapter 1: hardcopy iv design flow using the quartus ii software 1?5 fpga and hardcopy companion device planning ? january 2010 altera corporation hardcopy iv device handbook, volume 2 1 for the non-socket replacement path, be sure to select i/os in the stratix iv e device that can be mapped to the hardcopy iv e device. not all i/os in the stratix iv e device are available in the hardcopy iv e non-socket replacement device. check the pinout information for both the stratix iv e device and the hardcopy iv e device to ensure that you can map successfully and be sure to select the hardcopy iv e companion device when designing for the stratix iv e device. when mapping a specific stratix iv device to a hardcopy iv companion device, there are a number of fpga prototype choices. table 1?1 lists the stratix iv gx fpga-to-hardcopy iv gx asic mapping options; table 1?2 lists the stratix iv e fpga-to-hardcopy iv e asic mapping options.
1?6 chapter 1: hardcopy iv design flow using the quartus ii software fpga and hardcopy companion device planning hardcopy iv device handbook, volume 2 ? january 2010 altera corporation ta ble 1? 1. stratix iv gx fpga prototype to hardcopy iv gx asic mapping paths hardcopy iv gx asic stratix iv gx fpga prototype and package ep4sgx70 ep4sgx110 ep4sgx180 ep4sgx230 ep4sgx290 ep4sgx360 ep4sgx530 device package f780 f780 f1152 f780 f1152 f1517 f780 f1152 f1517 h780 f1152 f1517 h780 f1152 f1517 h1152 h1517 HC4GX15 780-pin fineline bga v v ? v ?? v ?? v (1) ?? v (1) ?? ? ? hc4gx25 780-pin fineline bga ??? ? ? ? ? ? ? v (1) ?? v (1) ?? ? ? 1152-pin fineline bga ?? v ? v ?? v ?? v ?? v ? v (1) ? hc4gx35 1152-pin fineline bga ? ???? ?? v ???? ? v ? v (1) ? 1517-pin fineline bga ? ???? v ?? v ?? v ?? v ? v note to ta bl e 1? 1 : (1) the hybrid fbga package requires additional unused board space along the edges beyond the footprint, but its footprint is co mpatible with the regular fbga package.
chapter 1: hardcopy iv design flow using the quartus ii software 1?7 fpga and hardcopy companion device planning ? january 2010 altera corporation hardcopy iv device handbook, volume 2 f for more information about i/o features in hardcopy iv devices, refer to the hardcopy iv i/o features chapter . f for more information about hardcopy iv device packages, refer to the hardcopy iv device family overview chapter. memory resources the trimatrix memory in hardcopy iv devices supports the same memory functions and features as stratix iv devices. you can configure each embedded memory block to be a single- or dual-port ram, fifo, rom, or shift register using the megawizard ? plug-in manager in the quartus ii software. hardcopy iv embedded memory consists of memory logic array blocks (mlabs), m9k, and m144k memory blocks and has a one-to-one mapping from the stratix iv memory. however, the number of available memory blocks differs based on density, package, and stratix iv fpga-to-hardcopy iv asic mapping paths. f for more information about hardcopy iv embedded memory resources, refer to the mapping stratix iv device resources with hardcopy iv devices chapter. while all three memory types are dedicated resources in stratix iv devices, only the m9k and m144k memory blocks are dedicated resources in the hardcopy iv devices. however, the same functionality of the stratix iv mlabs can be supported in hardcopy iv devices. the quartus ii software maps the stratix iv mlab function to the appropriate hcell macro that preserves the memory function. this allows the hardcopy iv core fabric to be used more efficiently, freeing up unused hcells for adaptive logic modules (alms) or digital signal processing (dsp) functions. tab le 1 ?2 . stratix iv e fpga prototype-to-hardcopy iv e asic mapping paths hardcopy iv e asic stratix iv e fpga prototype and package ep4se230 ep4se360 ep4se530 ep4se820 device package f780 h780 f1152 h1152 h1517 h1152 h1517 hc4e25 484-pin fineline bga v (1) ? ?? ? ?? 780-pin fineline bga v v (2) ? ? ? ? ? hc4e35 1152-pin fineline bga ? ? v v (2) ? v (2) ? 1517-pin fineline bga ? ? ? ? v (2) ? v notes to ta bl e 1? 2 : (1) this mapping is a non-socket replacement path that requires a different board design for the stratix iv e device and the har dcopy iv e device. (2) the hybrid fbga package requires additional unused board space along the edges beyond the footprint, but its footprint is co mpatible with the regular fbga package.
1?8 chapter 1: hardcopy iv design flow using the quartus ii software clock and pll planning hardcopy iv device handbook, volume 2 ? january 2010 altera corporation although the memory in hardcopy iv devices supports the same memory functions and features as stratix iv devices, you cannot pre-load or initialize hardcopy iv memory blocks with a memory initialization file ( .mif ) when they are used as ram. unlike stratix iv devices, hardcopy iv devices do not have device configuration. the memory content of hardcopy iv devices are random after power-up. therefore, you must ensure that your stratix iv design does not require a .mif if the memory blocks are used as ram. however, if the hardcopy iv memory block is designed as rom, it powers up with the rom contents. 1 use the altmem_init megafunction to initialize the ram after power-up for hardcopy iv devices. this megafunction reads from an internal rom (inside the megafunction) or an external rom (on-chip or off-chip) and writes to the ram after power-up. when using non-registered output mode for the hardcopy iv mlabs, the output powers up with memory content. when using registered output mode for these memory blocks, the outputs are cleared on power-up. you must take this into consideration when designing logic that might evaluate the initial power-up values of the mlab memory block. f for more information about memory blocks in hardcopy iv devices, refer to the trimatrix embedded memory blocks in hardcopy iv devices chapter . dsp blocks implementation the quartus ii software uses a library of pre-characterized hcell macros to place stratix iv dsp configurations into the hardcopy iv hcell-based logic fabric. depending on the stratix iv dsp configurations, the quartus ii software partitions the dsp function into a combination of dsp hcell macros in the hardcopy iv device. this optimizes the dsp function and allows the core fabric to be used more efficiently. f for more information about dsp blocks in hardcopy iv devices, refer to the dsp block implementation in hardcopy iv devices chapter . clock and pll planning to ensure that you map the stratix iv design to a hardcopy iv design successfully, follow these guidelines when implementing your design. they can help make your design robust, ensuring it meets timing closure and achieves the performance you need. f for more information about the clock scheme and pll features in hardcopy iv devices, refer to the clock networks and plls in hardcopy iv devices chapter . clock networks and pll resources you must consider the system clocking scheme, timing requirements, and fan-out requirements during clock networks and pll resources planning. matching pll resources between stratix iv and hardcopy iv devices is determined by the design?s clocking scheme and timing requirements. for high fan-out signals, use a dedicated clock resource.
chapter 1: hardcopy iv design flow using the quartus ii software 1?9 quartus ii settings for hardcopy iv devices ? january 2010 altera corporation hardcopy iv device handbook, volume 2 in the quartus ii software, be sure the hardcopy iv companion device is selected in the device selection panel. this ensures that the pll, other resources used, and the functions implemented in both the stratix iv and hardcopy iv designs match. in addition, it ensures that the design converts successfully. f for more information about hardcopy iv pll resources, refer to the mapping stratix iv device resources with hardcopy iv devices chapter . add pll reconfiguration to altera ip blocks enable pll reconfiguration for your design if it uses plls. the pll settings in hardcopy iv companion devices may require different settings from the stratix iv plls because of different clock tree lengths and pll compensations. by enabling pll reconfiguration, you can adjust your pll settings on the hardcopy iv companion device after the silicon has been fabricated. this allows you to fine tune and further optimize your system performance. use dedicated clock pins during clock planning, use dedicated clock input pins for high fan-out control signals, such as asynchronous clears, presets, and clock enables for protocol signals, such as trdy and irdy for pci express (pipe), in global or regional clock networks. these dedicated routing networks provide predictable delay and minimize skew for high fan-out signals. use dedicated clock pins to drive the pll reference clock inputs, especially if the design interfaces with external memories. this minimizes the reference clock input jitter to the plls, providing more timing margin to make the timing closure successful. for external memory interfaces, altera recommends using the double date rate (ddr) register in the i/o element to generate the external memory clocks. f for information about external memory interfaces, refer to the external memory interfaces in hardcopy iv devices chapter . quartus ii settings for hardcopy iv devices the hardcopy iv development flow requires additional quartus ii settings when compared with a typical fpga-only design flow. this is because the hardcopy iv design is implemented in two devices: a stratix iv prototype and a hardcopy iv companion device. you must take these settings into consideration when developing your design. limit dsp and ram to hardcopy device resources to maintain compatibility between the stratix iv and hardcopy iv devices, your design must use resources that are common to both families. the quartus ii software turns on limit dsp & ram to hardcopy device resources by default when you select the stratix iv device and hardcopy iv companion device in the quartus ii software. this prevents the quartus ii software from using resources in the stratix iv device that are not available in the hardcopy iv device. figure 1?3 shows the appropriate setting to select in the companion device section.
1?10 chapter 1: hardcopy iv design flow using the quartus ii software quartus ii settings for hardcopy iv devices hardcopy iv device handbook, volume 2 ? january 2010 altera corporation 1 the altera hardcopy design center requires that your final stratix iv and hardcopy iv designs be compiled with the limit dsp & ram to hardcopy device resources setting turned on before submission to the altera hardcopy design center for back-end implementation. enable design assistant to run during compile you must use the quartus ii design assistant to check for design rule violations before submitting the designs to the altera hardcopy design center. additionally, you must fix all critical and high-level errors reported by the quartus ii design assistant. altera recommends turning on the design assistant to run automatically during development. to enable the design assistant to run during compilation, on the assignments menu, click settings . in the category list, select design assistant and turn on run design assistant during compilation . figure 1?3. limit dsp and ram to hardcopy iv device resources checkbox
chapter 1: hardcopy iv design flow using the quartus ii software 1?11 quartus ii settings for hardcopy iv devices ? january 2010 altera corporation hardcopy iv device handbook, volume 2 figure 1?4 shows the design assistant . i/o assignment settings due to the complex rules governing the use of i/o cells and their availability for specific pins and packages, altera recommends that i/o assignments be completed using the pin planner tool and the assignment editor in the quartus ii software. these tools ensure that all of the rules regarding each pin and i/o cell are applied correctly. the quartus ii software can export a .tcl script containing all i/o assignments. f for more information about i/o location and type assignments using the quartus ii assignment editor and pin planner tools, refer to the assignment editor chapter in volume 2 of the quartus ii handbook. to ensure that the hardcopy iv mapping is successful, you must make accurate i/o assignments that include pin locations, i/o standards, drive strengths, and capacitance loading for the design. ensure that the i/o assignments are compatible with all selected devices. altera recommends not leaving any i/o with an unassigned i/o assignment. figure 1?4. enabling the design assistant
1?12 chapter 1: hardcopy iv design flow using the quartus ii software quartus ii settings for hardcopy iv devices hardcopy iv device handbook, volume 2 ? january 2010 altera corporation the i/o pins of a stratix iv device and a hardcopy iv device are arranged in groups called modular i/o banks. when mapping between a stratix iv device and a hardcopy iv device, the i/o pin location must be assigned to the available common i/o banks for both devices. because hardcopy iv devices have fewer i/o banks than stratix iv devices, the quartus ii software limits the i/o banks to only those available in hardcopy iv devices. f for more information about i/o banks and pins in hardcopy iv devices, refer to the hardcopy iv device i/o features chapter . hardcopy iv i/o buffers support 3.3-v i/o standards. you can use them as transmitters or receivers in your system. the 3.3-v i/o standard can be supported by using the bank supply voltage (v ccio ) at 3.0 v. in this method, the clamp diode (on-chip or off-chip), when enabled, can sufficiently clamp overshoot voltage to within the dc and ac input voltage specification. the clamped voltage can be expressed as the sum of the supply voltage (v ccio ) and the diode forward voltage. f for more information about hardcopy iv i/o buffers and the standards they support, refer to the dc and switching characteristics chapter . f for more information about mapping stratix iv to hardcopy iv i/os, refer to the mapping stratix iv device resources to hardcopy iv devices chapter . it is essential to constrain the i/o standards for the design. if you leave the i/o with an unassigned i/o assignment, the quartus ii software assigns the i/o standard to 2.5 v by default. this standard may not be compatible with your intended i/o standard. to check the supported i/o standards and identify incompatible i/o settings on the assigned i/os, run the quartus ii i/o assignment analysis to verify the i/o settings and assignments. to run i/o assignment analysis, on the processing menu, point to start , then click start i/o assignment analysis . figure 1?5 shows the i/o assignment analysis in the quartus ii software.
chapter 1: hardcopy iv design flow using the quartus ii software 1?13 quartus ii settings for hardcopy iv devices ? january 2010 altera corporation hardcopy iv device handbook, volume 2 the default output drive strength in the quartus ii software might not be appropriate for your application. altera recommends verifying the correct output drive strength for the design. assigning the right output drive strength improves signal integrity while achieving timing requirements. in addition, the output capacitance loading for both the output and bidirectional pins must be set in the i/o assignment for a successful hardcopy compilation. physical synthesis optimization settings when you develop a hardcopy iv device with the quartus ii software, you can target physical synthesis optimizations to the fpga architecture in stratix iv-device first flow or the hardcopy architecture in the hardcopy iv-first flow. the optimizations in the base revision are mapped to the companion device architecture during the mapping process and the post-fitting netlists of both devices are generated and compared. therefore, you must have the identical physical synthesis settings for both the hardcopy iv asic and stratix iv fpga revisions in order to avoid revision comparison failure. to enable physical synthesis optimizations for the stratix iv fpga revision of the design, on the assignments menu, click settings . in the settings dialog box, in the category list, expand fitter settings . these optimizations are passed into the hardcopy iv companion revision for placement and timing closure. when designing with a hardcopy iv device first, you can enable physical synthesis optimizations for the hardcopy iv device, and these post-fit optimizations are passed to the stratix iv fpga revision. figure 1?5. start i/o assignment analysis stratix iv: ep4sgx110f ...
1?14 chapter 1: hardcopy iv design flow using the quartus ii software quartus ii settings for hardcopy iv devices hardcopy iv device handbook, volume 2 ? january 2010 altera corporation 1 beginning with the quartus ii v9.0 software, the physical synthesis optimizations settings changed. if a hardcopy iv device is set as a companion device, the physical synthesis optimization setting in the stratix iv fpga or hardcopy iv asic revision supports the perform physical synthesis for combination logic and perform register retiming options. in addition, the effort level of physical synthesis optimization is set to fast by default. timing settings for hardcopy iv device development, you must use the timequest timing analyzer. in the quartus ii software, timequest timing analyzer is the default timing analyzer for stratix iv and hardcopy iv designs. the timequest timing analyzer guides the quartus ii fitter and analyzes timing results during each stratix iv and hardcopy iv design compilation. for information about how to set the quartus ii fitter to use timing-driven compilation, refer to ?quartus ii fitter settings? on page 1?19 . timing constraints for the timequest timing analyzer the timequest timing analyzer is a powerful asic-style timing analysis tool that validates timing in your design using industry-standard constraint, analysis, and reporting methodology. you can use the timequest analyzer ?s gui or command-line interface to constrain, analyze, and report results for all timing paths in your design. before running the timequest analyzer, you must specify initial timing constraints that describe the clock characteristics, timing exceptions, signal transition arrival, and required times. you can specify timing constraints in the synopsys design constraints file ( .sdc ) format using the timequest analyzer gui or the command-line interface. the quartus ii fitter optimizes the placement of logic to meet your constraints. the timequest analyzer analyzes the timing paths in the design, calculates the propagation delay along each path, checks for timing constraint violations, and reports timing results as slack in the report and console panels. if the timequest analyzer reports any timing violations, you can customize the reporting to view precise timing information about the specific paths, and then constrain those paths to correct the violations. when your design is free of timing violations, you can be confident that the logic will operate as intended in the target device. the timequest analyzer is a complete static timing analysis tool that you can use as a sign-off tool for the stratix iv design. for the hardcopy iv design, the altera hardcopy design center uses the primetime timing analyzer as the sign-off tool for back-end implementation. f for more information about how to create .sdc format timing constraints, refer to the quartus ii timequest timing analyzer chapter in volume 3 of the quartus ii handbook.
chapter 1: hardcopy iv design flow using the quartus ii software 1?15 incremental compilation ? january 2010 altera corporation hardcopy iv device handbook, volume 2 timequest multicorner timing analysis setting the altera hardcopy design center requires that all hardcopy handoff files include a timequest analyzer timing report for design review. in the timequest analyzer timing report, you must include both fast- and slow-corner timing analysis for setup, hold, and i/o paths. to do this, enable the multicorner timing analysis during compilation option on the timequest timing analyzer page under timing analysis settings in the quartus ii software. this option directs the timequest analyzer to analyze the design and generate slack reports for the slow and fast corners. figure 1?6 shows the settings you must enable so that the timequest analyzer generates the appropriate reports. incremental compilation for the hardcopy development flow, the quartus ii design software offers incremental compilation to preserve the compilation results for unchanged logic in your design. this feature dramatically reduces your design iteration time by focusing new compilations only on changed design partitions. new compilation results are then merged with the previous compilation results from unchanged design partitions. there are two approaches of incremental compilation in the quartus ii software: top-down incremental compilation bottom-up incremental compilation 1 bottom-up incremental compilation flow is not supported for designs targeting hardcopy asics. figure 1?6. timequest multicorner timing analysis setting
1?16 chapter 1: hardcopy iv design flow using the quartus ii software incremental compilation hardcopy iv device handbook, volume 2 ? january 2010 altera corporation for large, high-density and high-performance designs in stratix fpgas and hardcopy asics, use top-down incremental compilation. top-down incremental compilation facilitates team-based design environments, allowing designers to create and optimize design blocks independently. begin planning for incremental compilation from the start of your design development. to take advantage of incremental compilation flow, split the design along any of its hierarchical boundaries into blocks called design partitions. in the quartus ii software, the same procedures create design partitions in the hardcopy asic and stratix fpga revisions. f for more information about creating design partitions, refer to the quartus ii incremental compilation for hierarchical and team-based design chapter in volume 1 of the quartus ii handbook . in the quartus ii software, the full incremental compilation option is turned on by default, so the project is ready for you to create design partitions for incremental compilation. figure 1?7 shows the full incremental compilation option in the quartus ii software. 1 if you do not create design partitions in a design, the quartus ii software uses a flat compilation flow, and you cannot use incremental compilation. figure 1?7. quartus ii incremental compilation option
chapter 1: hardcopy iv design flow using the quartus ii software 1?17 incremental compilation ? january 2010 altera corporation hardcopy iv device handbook, volume 2 top-down incremental compilation top-down incremental compilation is supported for the base revision for designs targeting hardcopy asics in both the fpga first flow and hardcopy first flow. in the quartus ii design software, you must select the base and companion revisions before design partitions of the base revision are created. after the design partitions are created in the quartus ii design software, the base revision is compiled and the design partition assignments are mapped to the companion device. in the hardcopy development flow, you make changes only in the base revision's design and design partition assignments with the quartus ii design software. therefore, you can perform top-down incremental compilation only in the base revision, but cannot perform incremental compilation to the companion revision. figure 1?8 shows the design ?top? with two design partitions. after the design partitions are created and compiled in the base family revision, you can modify the specific design partitions for additional area and performance improvement. figure 1?9 shows that when the logic is modified in partition ?inst3? the quartus ii software is ready to re-compile the individual hierarchical design partition separately, based on the preservation level in the design partition window. therefore, the optimization result of design partitions ?top? and ?inst2? are preserved while the partition ?inst3? is re-compiled in the quartus ii design software. figure 1?8. quartus ii project with design partitions figure 1?9. design partition modified partition ?inst3? partition ?inst2? top partition ?inst3? partition ?inst2? (no change) top
1?18 chapter 1: hardcopy iv design flow using the quartus ii software incremental compilation hardcopy iv device handbook, volume 2 ? january 2010 altera corporation before recompiling the design, you can set the netlist type in the design partition window to source file , post-synthesis , or post-fitting to preserve the netlist type of each design partition. figure 1?10 shows the design partition window with the post-fit preservation level for the design partitions ?top? and ?inst2.? this allows the quartus ii design software to re-compile the design partition ?inst2? from the source file, but preserves the post-fitting results of design partitions ?top? and ?inst3.? the quartus ii software merges the new compiled design partition ?inst3? into a complete netlist for subsequent stages of the compilation flow. design partitions ?top? and ?inst2? in the design do not perform incremental compilation because their logic must be preserved. therefore, the compilation time for the overall design is reduced. top-down incremental compilation with empty design partitions bottom-up incremental compilation is not supported in the hardcopy development flow. during the initial stage of the design cycle, part of the design may be incomplete or developed by a different designer or ip provider. however, you can create an empty partition for this part of the design while compiling the completed partitions, and then save the results for the complete partitions while you optimize the imported part of the design. 1 you can often use a top-down flow with empty partitions to implement behavior similar to a bottom-up flow, as long as you do not change the global assignments between compilations. all global assignments must be the same for all compiled partitions, so the assignments can be reproduced in the companion device after mapping. 1 for the hardcopy development flow, create an empty partition in the base device because it cannot be created in the companion revision. creating an empty partition in a design is similar to creating a regular design partition in the quartus ii software. when the logic within a specific design partition is incomplete, use the following instructions to set the netlist type to empty . 1. on the assignment menu, click design partitions window . 2. double-click an entry under the netlist type column and select empty . this setting specifies that the quartus ii compiler must use an empty placeholder netlist for the partition. figure 1?11 shows the empty partition setting in the design partition window. figure 1?10. design partition window
chapter 1: hardcopy iv design flow using the quartus ii software 1?19 quartus ii fitter settings ? january 2010 altera corporation hardcopy iv device handbook, volume 2 when a partition netlist type is defined as empty , virtual pins are automatically created at the boundary of the partition. this means that the software temporarily maps the i/o pins in the lower-level design entity to the internal cells instead of the pins during compilation. any child partitions below an empty partition in the design hierarchy are also automatically treated as empty, regardless of their settings. after the design partition with the empty netlist type is completed and you have defined ?inst3? in the top module, the quartus ii software is ready to recompile the ?inst3? design partition. first, set the netlist type of the design partition ?inst2? to the specific preservation target, such as post-synthesis or post-fit to preserve the performance results from the previous compilation. before you recompile the design, ensure that you set the netlist type of the design partition ?inst3? to source file because this is new design source for the quartus ii software. as in the traditional top-down design flow, the quartus ii software merges the new compiled design partition ?inst3? into a complete netlist for the subsequent stages of the compilation flow. therefore, the turnaround time for the design compilation is reduced. quartus ii fitter settings to make the hardcopy iv device implementation more robust across process, temperature, and voltage variations, the altera hardcopy design center requires that you enable multicorner optimization for the quartus ii fitter. this setting controls whether the fitter optimizes a design to meet timing requirements at the fast-timing process corner and operating condition, as well as at the slow-timing process corner and operating condition. the altera hardcopy design center also requires that you enable the optimize hold timing setting for the quartus ii fitter. this setting allows the fitter to optimize hold time by adding delay to the appropriate paths. figure 1?11. design partition with empty netlist type
1?20 chapter 1: hardcopy iv design flow using the quartus ii software hardcopy design readiness check hardcopy iv device handbook, volume 2 ? january 2010 altera corporation figure 1?12 shows the optimize multi-corner timing and optimize hold timing settings in the fitter settings panel. hardcopy design readiness check the hardcopy design readiness check (hcdrc) feature checks issues that must be addressed before handing off the hardcopy iv design to the altera hardcopy design center for the back-end implementation process. in the quartus ii software, the hcdrc includes logic checks such as pll, ram, and setting checks (global setting, instance setting, and operating setting) that were previously done in the hardcopy hand-off report. beginning with the quartus ii software version 8.0, the default setting for running hcdrc is on . you can run hcdrc at post-fitter either turned on through the quartus settings file ( .qsf ) or gui. figure 1?12. quartus ii fitter settings for optimization multicorner and hold time fix
chapter 1: hardcopy iv design flow using the quartus ii software 1?21 timing closure and verification ? january 2010 altera corporation hardcopy iv device handbook, volume 2 figure 1?13 shows the hardcopy design readiness check in the quartus ii software. f for more information about the hardcopy design readiness check, refer to the quartus ii support for hardcopy series devices chapter in volume 1 of the quartus ii handbook. timing closure and verification after compiling the project for the stratix iv and hardcopy iv designs, check the device used and verify that the design meets your timing requirements. analyze the messages generated by the quartus ii software during compilation to check for any potential problems. also verify the design functionality between the stratix iv and hardcopy iv devices with the hardcopy companion revision comparison option in the quartus ii software. timing closure with the timequest timing analyzer the timequest timing analyzer is the timing analysis tool for all hardcopy iv devices during the front-end design process; it is the default timing analyzer for stratix iv and hardcopy iv devices in the quartus ii software. after you specify the initial timing constraints that describe the clock characteristics, timing exceptions, and signal transition arrival and required time in the .sdc , the timequest analyzer analyzes the timing paths in the design, calculates the propagation delay along each path, checks for timing constraint violations, and reports timing results. figure 1?13. hardcopy design readiness check in the quartus ii software
1?22 chapter 1: hardcopy iv design flow using the quartus ii software timing closure and verification hardcopy iv device handbook, volume 2 ? january 2010 altera corporation from the timequest analyzer settings in the quartus ii software, ensure that the timequest analyzer has the enable multicorner timing analysis during compilation check box selected. this setting is necessary to achieve timing closure for the hardcopy iv asic design. by default, the timequest analyzer has this setting enabled to analyze the design against best-case and worst-case operating conditions during compilation ( figure 1?14 ). to direct the timequest analyzer to remove the common clock path pessimism during slack computation in the quartus ii software, select the enable common clock path pessimism removal option in the timequest timing analyzer page ( figure 1?14 ). verification the quartus ii software uses companion revisions in a single project to promote conversion of your design from a stratix iv fpga to a hardcopy iv asic. this methodology allows you to design with one set of register transfer level (rtl) code to be used in both the stratix iv and hardcopy iv designs, guaranteeing functional equivalency. figure 1?14. timequest timing analyzer enable multicorner timing analysis during compilation and enable common clock path pessimism removal options
chapter 1: hardcopy iv design flow using the quartus ii software 1?23 engineering change order (eco) ? january 2010 altera corporation hardcopy iv device handbook, volume 2 when making changes to your design in a companion revision, use the compare hardcopy companion revisions feature in the quartus ii software to ensure that your stratix iv and hardcopy iv designs match functionality and compilation settings. you must perform this comparison after both stratix iv and hardcopy iv designs are compiled and before you hand off the design to the altera hardcopy design center. figure 1?15 shows how to navigate to the companion revisions comparison. on the project menu, point to hardcopy utilities and click compare hardcopy companion revisions . engineering change order (eco) during the last stage of the design cycle, it is critical to implement a specific portion of the design, without affecting the rest of its logic. as described in the previous section, incremental compilation can implement and manage certain partitions of the design, and preserve the optimization results for the rest of the design. however, this becomes difficult to manage because engineering change orders (ecos) are often implemented as last-minute changes to your design. the quartus ii software provides the chip planner tool and the resource property editor for eco operations to shorten the design cycle time significantly. for the hardcopy development flow, ecos occur in the stratix fpga revision and you make the changes directly to the post place-and-route netlist. when you switch to the hardcopy asic revision, apply the same ecos, run the timing analysis and assembler, perform a revision compare, and then run hardcopy netlist writer for design submission. figure 1?15. compare hardcopy companion revisions
1?24 chapter 1: hardcopy iv design flow using the quartus ii software engineering change order (eco) hardcopy iv device handbook, volume 2 ? january 2010 altera corporation ecos can be categorized in two ways for hardcopy development: migrating one-to-one changes migrating changes that must be implemented differently migrating one-to-one changes some examples of migrating one-to-one changes are changes such as creating, deleting, or moving pins, changing pin or pll properties, or changing pin connectivity (provided the source and destination of the connectivity changes are i/os or plls). to duplicate the same eco in the quartus ii software, use the change manager and record all ecos for the fpga revision. ensure that the same eco operations occur on each revision for both the stratix fpga and hardcopy asic revisions to avoid a revision comparison failure. to generate a .tcl script of the eco operations in the stratix fpga revision and apply it to the hardcopy revision, follow these steps: 1. in the stratix fpga revision, open change manager . 2. on the view menu, click utility windows and select change manager . 3. perform the eco in the chip planner or resource property editor . you will see the eco operations in the change manager . f for the information about eco operations in the stratix fpga revision, refer to the engineering change management with the chip planner chapter in volume 2 of the quartus ii handbook . 4. export the eco operations from the change manager to tc l s cr i p t . on the change manager , right mouse click the entry. click export , and then click export all changes as? 5. save the .tcl script, to be used in the hardcopy revision. in the hardcopy revision, apply the .tcl script to the companion revision using the following procedure. 1. open the generated .tcl script from the quartus ii software or a text editor tool. edit the line project_open - revision to refer to the appropriate companion revision. save the .tcl script. 2. apply the .tcl script to the companion revision. on tools menu, scroll the tc l scripts pull-down menu, and select eco tcl and click run . migrating changes that must be implemented differently unlike migrating changes one-to-one, some changes must be implemented on the stratix fpga and hardcopy asic revisions differently. changes affecting the logic of the design can fall into this category. examples of these are lutmask changes, lc_comb/hsadder creation and deletion, and connectivity changes not covered in the previous section.
chapter 1: hardcopy iv design flow using the quartus ii software 1?25 engineering change order (eco) ? january 2010 altera corporation hardcopy iv device handbook, volume 2 f for a summary of suggested implementation changes, refer to the quartus ii support for hardcopy series devices chapter in volume 1 of the quartus ii handbook . pll settings are another example of implementing changes differently on the stratix fpga and the hardcopy asic revisions. sometimes pll-generated clocks must be modified to provide a higher-frequency clock in hardcopy devices to improve the performance of the hardcopy device without changing the performance of the stratix fpga. you must handle the modification correctly so that the hardcopy companion revision comparison utility does not generate critical errors. to set different pll settings for the stratix fpga and hardcopy revisions, you must have different pll source files. each pll must have the same module name, so that the same pll in both revisions is not treated differently during the hardcopy revision comparison stage. you must have two pll files with different names that reference the same module. when starting hardcopy development with the fpga first flow to override the file naming convention so that the same pll module can be referenced by two different pll files, complete the following steps: 1. specify the pll source file in the qsf file in the stratix fpga revision. for example, set_global_assignment -name migration_different_source_file pll_fgpa.v 1 note that when there are multiple pll source files, you must use multiple assignments to specify the pll source files. 2. compile the stratix fpga revision in the quartus ii software. 3. after creating the hardcopy revision, modify the pll source file manually or with the megawizard plug-in manager in order to improve the performance in the hardcopy revision. 1 when the megawizard plug-in manager updates the new source file, it modifies the top-level name of the module or entity in the source file to match the name of the source file. therefore, you must rename the module or entity after you have updated the file with the megawizard plug-in manager so that your top-level design instantiates the pll with the newly modified pll design file. 4. after updating the pll source file in the hardcopy revision, verify that the qsf source file setting contains the newly modified pll source file. for example, set_global_assignment -name verilog_file pll_hc.v 5. compile the hardcopy revision in the quartus ii software. after compilation is completed, run the hardcopy companion revision comparison utility to observe and track the changes made to the plls and design settings. these changes are captured as critical warnings in the revision comparison report and must be reviewed by the hardcopy design center before the design is accepted for mapping.
1?26 chapter 1: hardcopy iv design flow using the quartus ii software hardcopy iv handoff process hardcopy iv device handbook, volume 2 ? january 2010 altera corporation hardcopy iv handoff process to submit a design to the altera hardcopy design center for design review and back-end implementation, generate a hardcopy iv handoff report and archive the hardcopy iv project. before you generate the hardcopy iv handoff report, you must first successfully perform the following tasks: compile both stratix iv and hardcopy iv revisions of the design. run the compare hardcopy companion revision utility. archive the hardcopy iv project and submit it to the altera hardcopy design center for back-end implementation. this is the last step in the hardcopy iv design flow. the hardcopy iv archive utility creates a different quartus ii archive file ( .qar ) than the standard quartus ii project archive utility generates. this archive contains only the data from the quartus ii project needed to implement the design in the altera hardcopy design center. to u s e t he archive hardcopy handoff files utility, you must perform all tasks for generating a hardcopy iv handoff report. after you generate a hardcopy iv handoff report, select the handoff option. on the project menu, point to hardcopy utilities and click archive hardcopy handoff files . the archive hardcopy handoff files utility archives your design, settings, results, and database files for delivery to altera. these files are generated at the same directory level as the targeted project created with an _hc extension. document revision history table 1?3 lists the revision history for this chapter. tab le 1 ?3 . document revision history (part 1 of 2) date version changes made january 2010 2.1 updated tab le 1 ?2 . added ?physical synthesis optimization settings? on page 1?13 . added ?incremental compilation? on page 1?15 . added ?engineering change order (eco)? on page 1?23 . minor text edits. june 2009 2.0 updated table 1?1. removed tables 1-2 and 1-3. added several references to other handbook chapters. minor text edits.
chapter 1: hardcopy iv design flow using the quartus ii software 1?27 document revision history ? january 2010 altera corporation hardcopy iv device handbook, volume 2 may 2009 1.1 updated table 1?3. updated figure 1?1, figure 1?2, figure 1?4, figure 1?6, figure 1?7, and figure 1?9. updated the ?fpga and hardcopy companion device planning?, ?i/o pin and package offering?, ?i/o assignment settings?, ?timing settings? and ?timing closure with the timequest timing analyzer? sections. removed the setting up the timequest timing analyzer, reference documents, and conclusion sections. december 2008 1.0 initial release. tab le 1 ?3 . document revision history (part 2 of 2)
1?28 chapter 1: hardcopy iv design flow using the quartus ii software document revision history hardcopy iv device handbook, volume 2 ? january 2010 altera corporation
? december 2008 altera corporation hardcopy iv device handbook, volume 2 2. hardcopy design center implementation process this chapter discusses the hardcopy ? iv back-end design flow executed by the altera ? hardcopy design center when developing your hardcopy iv device. hardcopy iv back-end design flow this section outlines the back-end design process for hardcopy iv devices. figure 2?1 illustrates these steps. the design process uses both proprietary and third-party eda tools. design netlist generation for hardcopy iv designs, the quartus ? ii software generates a complete verilog gate-level netlist of your design. the hardcopy design center uses the netlist to start the back-end process. in addition to the verilog gate-level netlist, the quartus ii software generates information as part of the design database submitted by you to the altera hardcopy design center. this information includes timing constraints, placement constraints, and global routing information. generation of this database provides the hardcopy design center with the necessary information to complete the design of your hardcopy iv device. figure 2?1. hardcopy iv back-end design flow note to figure 2?1 (1) refer to figure 2?2 for more information about the timing eco. quartus ii netlist formal verification clock insertion dft insertion global signal insertion other tasks design database processed netlist timing and si driven place and route design database contents: quartus ii constraints: -timing constraints -placement constraints -routing constraints hardcopy iv design libraries: -physical and timing models -base layout database post place and route netlist formal verification drc/lvs/antenna physical layout verification layout gds2 layout signoff design tape-out netlist signoff crosstalk, sl, static timing analysis timing signoff parasitic extraction timing eco (1) stratix iv physical netlist stratix iv .sof file hiv52002-1.0
2?2 chapter 2: hardcopy design center implementation process hardcopy iv back-end design flow hardcopy iv device handbook, volume 2 ? december 2008 altera corporation design for testability the hardcopy design center inserts the necessary test structures into the hardcopy iv verilog netlist. these test structures include full-scan capable registers and scan chains, jtag, and memory testing. after adding the test structures, the modified netlist is verified using third-party eda formal verification software against the original verilog netlist to ensure that the test structures have not broken your netlist functionality. ?formal verification of the processed netlist? on page 2?2 explains the formal verification process. clock tree and global signal insertion along with test insertion, the hardcopy design center adds a local layer of clock tree buffering to connect the global clock resources to the locally placed registers in the design. global signals with high fan-out can also use dedicated global clock resources built into the base layers of all hardcopy iv devices. the hardcopy design center does local buffering. tie-off connections for unused resources if an unused resource in a customer design still exists in the hardcopy iv database, the hardcopy design center uses special handling on the tie-off connections for these resources. i/o ports of unused resources are connected to power or ground so that the resources are in a lower power state. this is achieved by using the same metal layers that are used to configure and connect all resources used in the design. formal verification of the processed netlist after all design-for-testability logic, clock tree buffering, global signal buffering, and tie-off connection are added to the processed netlist, the hardcopy design center uses third-party eda formal verification software to compare the processed netlist with your submitted verilog netlist generated by the quartus ii software. added test structures are constrained to bypass mode during formal verification to verify that your design?s intended functionality is unchanged. timing and signal integrity driven place and route placement and global signal routing is principally done in the quartus ii software before submitting the hardcopy iv design to the hardcopy design center. with the quartus ii software, you control the placement and timing driven placement optimization of your design. the quartus ii software also does global routing of your signal nets, and passes this information in the design database to the hardcopy design center to do the final routing. after the design is submitted, altera engineers use the placement and global routing information provided in the design database to do final routing and timing closure, and to perform signal integrity and crosstalk analysis. this may require buffer and delay cell insertion in the design through an engineering change order (eco). the resulting post place and route netlist is verified again with the source netlist and the processed netlist to guarantee that functionality was not altered in the process. for more details about back-end timing closure and timing ecos, refer to ?back-end timing closure? and ?timing ecos? .
chapter 2: hardcopy design center implementation process 2?3 hardcopy iv back-end design flow ? december 2008 altera corporation hardcopy iv device handbook, volume 2 parasitic extraction and timing analysis after the hardcopy design center places and routes your design, a .gds2 design file is generated. parasitic extraction uses the physical layout of the design stored in the database to extract the resistance and capacitance values for all signal nets in the design. the hardcopy design center uses these parasitic values to calculate the path delays through the design for static timing analysis and crosstalk analysis. back-end timing closure the quartus ii software provides a pre-layout estimation of your hardcopy iv design performance. the altera hardcopy design center then uses industry leading eda software to complete the back-end layout and extract the final timing results prior to tape-out. altera performs rigorous timing analysis on the hardcopy iv design during its back-end implementation, ensuring that it meets the required timing constraints. after generating the customized metal interconnect for the hardcopy iv device, altera checks the design timing with a static timing analysis tool. the static timing analysis tool may report timing violations, which are reviewed with the customer. the critical timing paths of the hardcopy iv device may be different from the corresponding paths in the stratix iv fpga revision; these differences can exist for several reasons. while maintaining the same set of features as the corresponding stratix iv fpga, hardcopy iv devices have a highly optimized die size to make them as small as possible. because of the customized interconnect structure that makes this optimization possible, the delay through each signal path is different from the original stratix iv fpga design. therefore, it is important to constrain the stratix iv fpga and hardcopy iv devices to the exact, system-level timing requirements that need to be achieved. timing violations seen in the quartus ii project or in the hardcopy design center back-end process must be fixed or waived prior to the design tape-out. timing ecos in an asic design, small incremental changes to a design database are termed ecos. in the hardcopy iv design flow, timing closure ecos are performed by altera?s hardcopy design center after the initial post-layout timing data is available. the altera hardcopy design center runs static timing analysis on the design. this analysis may show that the place and route tool was not able to close timing automatically on some paths. the hardcopy design center engineer will determine the best way to fix the timing on these paths (for example, by adding delay cells to fix a hold time violation). this list of changes is fed back into the place and route tool which subsequently implements the changes. the impact to the place and route database is minimized by maintaining all of the pre-existing placement and routing, and only changing the paths that need improvement. the parasitic resistances and capacitances of the customized interconnect are extracted, and are used in conjunction with the static timing analysis tool to re-check the timing of the design. detected crosstalk violations on signals are fixed by adding additional buffering to increase the setup or hold margin on victim signals. in-line buffering and small buffer tree insertion is done for signals with high fanout, high transition times, or high capacitive loading. figure 2?2 shows this flow in more detail.
2?4 chapter 2: hardcopy design center implementation process hardcopy iv back-end design flow hardcopy iv device handbook, volume 2 ? december 2008 altera corporation the back-end flow produces the final signoff timing for your hardcopy iv device. the quartus ii software produces the timing report for hardcopy iv based on global routing and does not factor in the exact physical parasitic of the routed nets. the quartus ii software also does not factor in the crosstalk effect that neighboring nets can have on interconnect capacitance. formal verification of the post-layout netlist besides the .gds2 file and parasitic files that are generated by the hardcopy design center, the post-layout netlist is also generated for formal verification with stratix iv fpgas. the hardcopy design center checks the functional equivalence between the stratix iv fpga prototype and hardcopy iv device according to the stratix iv .sof file and hardcopy iv post-layout netlist. figure 2?2. timing closure eco flow diagram timing closure eco iterations eco file preparation merge new cells into physical database placement clock tree synthesis and high fan-out net buffering detailed routing static timing analysis timing violations timing closed database
chapter 2: hardcopy design center implementation process 2?5 conclusion ? december 2008 altera corporation hardcopy iv device handbook, volume 2 layout verification when the timing analysis reports that all timing requirements are met, the design layout goes into the final stage of verification for manufacturability. the hardcopy design center performs physical design rule checking (drc), antenna checking of long traces of signals in the layout, and a comparison of layout to the design netlist, commonly referred to as layout versus schematic (lvs). these tasks guarantee that the layout contains the exact logic represented in the place-and-route netlist and the physical layout. design signoff the altera hardcopy iv back-end design methodology has a thorough verification and signoff process, guaranteeing your design?s functionality. signoff occurs after completing the final place-and-route netlist functional verification, layout verification for manufacturability, and timing analysis. after achieving all three signoff points, altera begins the manufacturing of the hardcopy iv devices. conclusion altera?s back-end design methodology ensures that your design converts successfully from your stratix iv fpga prototype to the hardcopy iv asic. altera?s unique system development methodology offers an excellent way for you to benefit from using a stratix iv fpga for design prototyping and debugging, and using a hardcopy iv asic for volume production. document revision history table 2?1 shows the revision history for this chapter. tab le 2 ?1 . document revision history december 2008 1.0 initial release.
2?6 chapter 2: hardcopy design center implementation process document revision history hardcopy iv device handbook, volume 2 ? december 2008 altera corporation
? january 2010 altera corporation hardcopy iv device handbook, volume 2 3. mapping stratix iv device resources to hardcopy iv devices this chapter discusses the available options for mapping from a stratix ? iv device to a hardcopy ? iv device. the quartus ii software limits resources to those available to both the stratix iv fpga and the hardcopy iv asic. it also ensures that the design revision targeting a hardcopy iv device retains the same functionality as the original stratix iv design. when compiling designs with the quartus ii software, you can specify one stratix iv target device and one or more stratix iv mapping devices. when you specify at least one mapping device, the quartus ii compiler constrains i/o pins and relevant hard ip blocks to the minimum resources available in any of the selected mapping devices. this feature allows vertical mapping between devices using the same package footprint. selecting a hardcopy iv device as a companion device is similar to adding another stratix iv device to the mapping device chain. the quartus ii software compiles the design to use the common resources available in all of the selected stratix iv and hardcopy iv devices. the hardcopy iv companion device becomes the target device when you create the hardcopy companion revision. figure 3?1 shows the device page of the settings dialog box, where you choose the companion device for the target device selected. the device panel lists appropriate companion devices based on the target device you select. hiv52003-2.1
3?2 chapter 3: mapping stratix iv device resources to hardcopy iv devices hardcopy iv device handbook, volume 2 ? january 2010 altera corporation when you select a hardcopy iv companion device, the quartus ii software fits your design to common resources in the i/os, clock structures, plls, memory blocks, and core logic for digital signal processing (dsp). f for more information about compiling with stratix iv and hardcopy iv companion revisions using the quartus ii software, refer to the quartus ii support for hardcopy series devices chapter in volume 1 of the quartus ii handbook . figure 3?1. quartus ii device settings page with hardcopy iv device selected as companion device
chapter 3: mapping stratix iv device resources to hardcopy iv devices 3?3 hardcopy iv and stratix iv mapping options ? january 2010 altera corporation hardcopy iv device handbook, volume 2 hardcopy iv and stratix iv mapping options hardcopy iv asics offer a wide range of family options that can map with various stratix iv fpgas. table 3?1 and table 3?2 lists the available hardcopy iv and stratix iv companion pairs. tab le 3 ?1 . hardcopy iv gx and stratix iv gx companion devices companion pair hardcopy iv package hardcopy iv gx asic stratix iv gx fpga prototype HC4GX15laf780n ep4sgx70df29 (f780) 780-pin fineline bga ep4sgx110df29 (f780) ep4sgx180df29 (f780) ep4sgx230df29 (f780) HC4GX15lf780n ep4sgx290fh29 (h780) ep4sgx360fh29 (h780) hc4gx25lf780n ep4sgx290fh29 (h780) 780-pin fineline bga ep4sgx360fh29 (h780) hc4gx25lf1152n ep4sgx110ff35 (f1152) 1152-pin fineline bga ep4sgx180ff35 (f1152) ep4sgx230ff35 (f1152) ep4sgx290ff35 (f1152) ep4sgx360ff35 (f1152) hc4gx25ff1152n ep4sgx180hf35 (f1152) 1152-pin fineline bga ep4sgx230hf35 (f1152) ep4sgx290hf35 (f1152) ep4sgx360hf35 (f1152) ep4sgx530hh35 (h1152) hc4gx35ff1152n ep4sgx230hf35 (f1152) 1152-pin fineline bga ep4sgx360hf35 (f1152) ep4sgx530hh35 (h1152) hc4gx35ff1517n ep4sgx180kf40 (f1517) 1517-pin fineline bga ep4sgx230kf40 (f1517) ep4sgx290kf40 (f1517) ep4sgx360kf40 (f1517) ep4sgx530kh40 (h1517)
3?4 chapter 3: mapping stratix iv device resources to hardcopy iv devices hardcopy iv and stratix iv mapping options hardcopy iv device handbook, volume 2 ? january 2010 altera corporation when the quartus ii software successfully compiles a design, the hardcopy device resource guide in the fitter compilation report contains information about mapping compatibility to a hardcopy iv device. use this information to select the optimal hardcopy iv device for the prototype stratix iv device based on resource and package requirements. table 3?3 and table 3?4 show the available resources for prototyping on a stratix iv device when choosing a hardcopy iv device. tab le 3 ?2 . hardcopy iv e and stratix iv e companion devices companion pair hardcopy iv package hardcopy iv e asic stratix iv e fpga prototype hc4e25wf484n (1) ep4se230f29 (f780) 484-pin fineline bga wire bond hc4e25ff484n (1) ep4se230f29 (f780) 484-pin fineline bga hc4e25wf780n ep4se230f29 (f780) 780-pin fineline bga wire bond ep4se360h29 (h780) hc4e25ff780n ep4se230f29 (f780) 780-pin fineline bga ep4se360h29 (h780) hc4e35lf1152n ep4se360f35 (f1152) 1152-pin fineline bga ep4se530h35 (h1152) ep4se820h35 (h1152) hc4e35ff1152n ep4se360f35 (f1152) 1152-pin fineline bga ep4se530h35 (h1152) ep4se820h35 (h1152) hc4e35lf1517n ep4se530h40 (h1517) 1517-pin fineline bga ep4se820h40 (h1517) hc4e35ff1517n ep4se530h40 (h1517) 1517-pin fineline bga ep4se820h40 (h1517) note to tab l e 3 ?2 : (1) this mapping is a non-socket replacement path that requires a different board design for the stratix iv e device and the hardcopy iv e device. the stratix iv e device is in a 780-pin fbga package while the hardcopy iv e device is in a 484-pin fbga package.
chapter 3: mapping stratix iv device resources to hardcopy iv devices 3?5 hardcopy iv and stratix iv mapping options ? january 2010 altera corporation hardcopy iv device handbook, volume 2 tab le 3 ?3 . hardcopy iv gx asic features hardcopy iv gx asic stratix iv gx fpga prototype asic equivalent gates (1) transceivers 6.5+gbps (2) m9k blocks m144k blocks total dedicated ram bits (not including mlabs) (3) 18 x 18-bit multipliers (fir mode) plls HC4GX15 ep4sgx70 2.8 m 8, 0 462 16 6,462 kb 384 3 ep4sgx110 3.8 m 8, 0 660 16 8,244 kb 512 3 ep4sgx180 6.7 m 8, 0 660 20 8,820 kb 920 3 ep4sgx230 9.2 m 8, 0 660 22 9,108 kb 1288 3 ep4sgx290 7.7 m 8, 0 660 24 9,396 kb 832 2 ep4sgx360 9.4 m 8, 0 660 24 9,396 kb 1040 2 hc4gx25 ep4sgx110 3.8 m 16, 0 660 16 8,244 kb 512 4 ep4sgx180 6.7 m 16, 8 (6) 936 20 11,304 kb 920 6 ep4sgx230 9.2m 16, 8 (6) 936 22 11,592 kb 1288 6 ep4sgx290 7.7 m 16, 8 (6) 936 36 13,608 kb 832 6 (4) ep4sgx360 9.4 m 16, 8 (6) 936 36 13,608 kb 1040 6 (4) ep4sgx530 11.5 m 16, 8 936 36 13,608 kb 1024 6 hc4gx35 ep4sgx180 6.7 m 24, 12 (7) 950 20 11,430 kb 920 8 ep4sgx230 9.2 m 24, 12 (7) 1235 22 14,283 kb 1288 8 (5) ep4sgx290 7.7 m 24, 12 (7) 936 36 13,608 kb 832 8 ep4sgx360 9.4 m 24, 12 (7) 1248 48 18,144 kb 1040 8 (5) ep4sgx530 11.5 m 24, 12 (7) 1280 64 20,736 kb 1024 8 (5) notes to ta bl e 3? 3 : (1) this is the number of asic-equivalent gates available in the hardcopy iv gx base array, shared between both adaptive logic m odule (alm) logic and dsp functions from a stratix iv gx fpga prototype. the number of usable asic equivalent gates is bounded by the number of a lms in the companion stratix iv gx fpga device. (2) the first number indicates the number of transceivers and the second number indicates the number of cmu (pma only) transcei vers. (3) hardcopy iv gx devices do not have dedicated mlabs, but the st ratix iv gx mlab features and functions are supported in hardc opy iv gx devices. (4) this device has six plls in the f1152 package and four plls in the f780 package. (5) this device has eight plls in the f1517 package and six plls in the f1152 package. (6) devices in the cost optimized lf780 and the lf1152 package have 16 transceivers and no cmu transceiver. devices in the perfo rmance optimized ff1152 package have 16 tr ansceivers and 8 cmu transceivers. (7) devices in the f1152 package have 16 transceivers and eight cmu transceivers. devices in the performance optimized ff1517 pa ckage have 24 transceivers and 12 cmu transceivers. tab le 3 ?4 . hardcopy iv e asic features (part 1 of 2) hardcopy iv e asic stratix iv e fpga prototype asic equivalent gates (1) m9k blocks m144k blocks total dedicated ram bits (not including mlabs) (2) 18 x 18-bit multipliers (fir mode) plls hc4e25 ep4se230 9.2 m 864 22 10,944 kb 1288 4 ep4se360 9.4 m 864 32 12,384 kb 1040 4
3?6 chapter 3: mapping stratix iv device resources to hardcopy iv devices hardcopy iv and stratix iv mapping options hardcopy iv device handbook, volume 2 ? january 2010 altera corporation hardcopy iv asics offer pin-to-pin compatibility to the stratix iv prototype, making them drop-in replacements for fpgas. due to this compatibility, the same system board and software developed for prototyping and field trials can be retained, enabling faster time-to-market for high-volume production. hardcopy iv devices also offer non-socket replacement mapping for further cost reduction. for example, the ep4se230 device in the 780-pin fbga package can be mapped to the hc4e25 device in the 484-pin fbga package. because the pinout for the two packages are not the same, a separate board design is required for the stratix iv device and the hardcopy iv device. 1 for the non-socket replacement path, select i/os in the stratix iv device that can be mapped to the hardcopy iv device. not all i/os in the stratix iv device are available in the hardcopy iv non-socket replacement device. check pinout information for both the stratix iv device and the hardcopy iv device to ensure that you can map successfully, and select the hardcopy iv companion device when designing for the stratix iv device. table 3?5 and table 3?6 show available i/o pin counts by package for each stratix iv and hardcopy iv companion pair. hc4e35 ep4se360 9.4 m 1,248 48 18,144 kb 1040 8 ep4se530 11.5 m 1,280 48 18,432 kb 1024 12 (3) ep4se820 14.6 m 1,320 48 18,792 kb 960 12 (3) notes to ta bl e 3? 4 : (1) this is the number of asic-equivalent gates available in the hardcopy iv e base array, shared between both adaptive logic mo dule (alm) logic and dsp functions from a stratix iv e fpga prototype. the number of usable asic equivalent gates is bounded by the number of al ms in the companion stratix iv e fpga device. (2) hardcopy iv e devices do not have dedicated mlabs, but the stratix iv e mlab features and functions are supported in hardcop y iv devices. (3) this device has 12 plls in the f1517 package and 8 plls in the f1152 package. tab le 3 ?4 . hardcopy iv e asic features (part 2 of 2) hardcopy iv e asic stratix iv e fpga prototype asic equivalent gates (1) m9k blocks m144k blocks total dedicated ram bits (not including mlabs) (2) 18 x 18-bit multipliers (fir mode) plls tab le 3 ?5 . hardcopy iv gx and stratix iv gx package and i/o pin count mapping (part 1 of 2) hardcopy iv gx asic (1) stratix iv gx fpga prototype 484-pin fineline bga 780-pin fineline bga (2) 1152-pin fineline bga (3) 1517-pin fineline bga (4) 1760-pin fineline bga HC4GX15la ep4sgx70 ? 372 ? ? ? ep4sgx110 ? 372 ? ? ? ep4sgx180 ? 372 ? ? ? ep4sgx230 ? 372 ? ? ? HC4GX15l ep4sgx290 ? 257 ? ? ? ep4sgx360 ? 257 ? ? ?
chapter 3: mapping stratix iv device resources to hardcopy iv devices 3?7 hardcopy iv and stratix iv mapping options ? january 2010 altera corporation hardcopy iv device handbook, volume 2 hc4gx25l ep4sgx110 ? ? 372 ? ? ep4sgx180 ? ? 564 ? ? ep4sgx230 ? ? 564 ? ? ep4sgx290 ? 289 564 ? ? ep4sgx360 ? 289 564 ? ? ep4sgx530 ? ? ? ? ? hc4gx25f ep4sgx110 ? ? ? ? ? ep4sgx180 ? ? 564 ? ? ep4sgx230 ? ? 564 ? ? ep4sgx290 ? ? 564 ? ? ep4sgx360 ? ? 564 ? ? ep4sgx530 ? ? 564 ? ? hc4gx35f ep4sgx180 ? ? ? 744 ? ep4sgx230 ? ? 564 744 ? ep4sgx290 ? ? ? 744 ? ep4sgx360 ? ? 564 744 ? ep4sgx530 ? ? 564 744 ? notes to ta bl e 3? 5 : (1) the last letter (two letters in the la package) in the hardcopy iv gx name refers to the following package types: f?performa nce-optimized flip chip package, l or la?cost-optimized flip-chip package. (2) the i/o pin count for the laf780 package includes the four dedicated clock inputs (clk1n, clk1p, clk3n, clk3p). the i/o pin count for the lf780 package includes one dedicated clock input (clk1p). (3) all i/o pin counts include four dedicated clock inputs (clk1p, clk1n, clk10p, and clk10n) that can be used as data inputs. (4) all i/o pin counts include eight dedicated clock inputs (clk1p, clk1n, clk3p, clk3n, clk8p, clk8n, clk10p, and clk10n) that can be used as data inputs. tab le 3 ?6 . hardcopy iv e and stratix iv e package and i/o pin count mapping (part 1 of 2) hardcopy iv e asic (1) stratix iv e fpga prototype 484-pin fineline bga (2) 780-pin fineline bga (2) 1152-pin fineline bga (2) 1517-pin fineline bga (3) 1760-pin fineline bga hc4e25w ep4se230 296 (4) 392 ? ? ? ep4se360 ? 392 ? ? ? hc4e25f ep4se230 296 (4) 488 ? ? ? ep4se360 ? 488 ? ? ? hc4e35l ep4se360 ? ? 744 ? ? ep4se530 ? ? 744 880 ? ep4se820 ? ? 744 880 ? tab le 3 ?5 . hardcopy iv gx and stratix iv gx package and i/o pin count mapping (part 2 of 2) hardcopy iv gx asic (1) stratix iv gx fpga prototype 484-pin fineline bga 780-pin fineline bga (2) 1152-pin fineline bga (3) 1517-pin fineline bga (4) 1760-pin fineline bga
3?8 chapter 3: mapping stratix iv device resources to hardcopy iv devices summary of differences between hardcopy iv and stratix iv devices hardcopy iv device handbook, volume 2 ? january 2010 altera corporation summary of differences between hardcopy iv and stratix iv devices hardcopy iv asics are functionally equivalent to stratix iv fpgas, but they have architectural differences. when implementing your design and laying out your board, consider the differences to ensure successful design mapping from the stratix iv fpga to the hardcopy iv asic. architectural differences between the stratix iv fpga and the hardcopy iv asic include: hardcopy iv devices have up to 20 i/o banks and 880 i/o pins, while the largest stratix iv companion devices have up to 24 i/o banks and 976 i/o pins in the 1517-pin fbga package. the number of global and regional clocks is identical for stratix iv and hardcopy iv devices, but stratix iv devices have up to 116 peripheral clocks, while hardcopy iv devices have up to 88. the quartus ii software limits the clock availability on stratix iv and hardcopy iv companion pairs to ensure device compatibility. configuration is not required for hardcopy iv devices; therefore, these stratix iv features are not supported: programming modes and features such as remote update and programmer object file ( .pof ) encryption. cyclical redundancy check (crc) for configuration error detection. 256-bit (aes) volatile and non-volatile security key to protect designs. jtag instructions used for configuration. fpga configuration emulation mode is not supported. boundary scan (bscan) chain length is different and varies with device density. memory initialization files (. mif ) for embedded memories used as ram are not supported. hc4e35f ep4se360 ? ? 744 ? ? ep4se530 ? ? 744 880 ? ep4se820 ? ? 744 880 ? notes to ta bl e 3? 6 : (1) the last letter in the hardcopy iv e device name refers to the following package types: f?performance-optimized flip-chip pa ckage, l-cost-optimized flip-chip p ackage, w?low-cost wirebond package. (2) all i/o pin counts include eight dedicated clock inputs (clk1p, clk1n, clk3p, clk3n, clk8p, clk8n, clk10p, and clk10n) that can be used for data inputs. (3) all i/o pin counts include eight dedicated clock inputs (clk1p, clk1n, clk3p, clk3n, clk8p, clk8n, clk10p, and clk10n) and e ight dedicated corner pll clock inputs (pll_l1_clkp, pll_l1_clkn, pll_l4_clkp, pll_l4_clkn, pll_r4_clkp, pll_r4_clkn, pll_r1_clkp, and pll_r1_clkn) that can be used as data inputs. (4) this mapping is a non-socket replacement path and requires a different board design for the stratix iv e device and the hard copy iv e device. the stratix iv e device is in a 780-pin fineline bga package whil e the hardcopy iv e device is in a 484-pin fineline bga packag e. tab le 3 ?6 . hardcopy iv e and stratix iv e package and i/o pin count mapping (part 2 of 2) hardcopy iv e asic (1) stratix iv e fpga prototype 484-pin fineline bga (2) 780-pin fineline bga (2) 1152-pin fineline bga (2) 1517-pin fineline bga (3) 1760-pin fineline bga
chapter 3: mapping stratix iv device resources to hardcopy iv devices 3?9 designing with hardcopy iv i/os ? january 2010 altera corporation hardcopy iv device handbook, volume 2 stratix iv lab/mlab and dsp functions are implemented with hcells in hardcopy iv devices instead of dedicated blocks. stratix iv programmable power technology is not supported in hardcopy iv devices. however, the hardcopy iv asic architecture offers performance on par with the stratix iv devices with significantly low power. designing with hardcopy iv i/os hardcopy iv asics support a wide range of industry standards that match stratix iv supported standards. hardcopy iv devices support 3.3 v i/o standards. the 3.3 v lvttl/lvcmos i/o standard is supported using v ccio at 3.0 v. hardcopy iv i/o standards support the same specifications as their stratix iv companion equivalent. the i/o arrangement matches stratix iv such that i/o pins located on the left and right side i/o banks contain circuits dedicated to high-speed differential i/o interfaces, but have the ability to support external memory devices if required. the top and bottom i/o banks contain dedicated circuitry to optimize external memory interfaces. they also have the ability to support high-speed differential inputs and outputs at lower speed than the left and right side banks. f for more information, refer to the hardcopy iv device i/o features chapter . mapping hardcopy iv and stratix iv i/os and modular i/o banks i/o pins in stratix iv and hardcopy iv devices are arranged in groups called modular i/o banks. on stratix iv devices, the number of i/o banks can range from 16 to 24 banks. on hardcopy iv devices, the number of i/o banks can range from 12 to 20 banks. in both stratix iv and hardcopy iv devices, the maximum number of i/o banks per side is four or six, depending on the device density. when migrating between devices with a different number of i/o banks per side, the middle or ?b? bank is removed or inserted. for example, when moving from a 24-bank stratix iv device to a 16-bank stratix iv or hardcopy iv device, the banks that are dropped are ?b? banks, namely 1b, 2b, 3b, 4b, 5b, 6b, 7b, and 8b. hardcopy iv devices do not have banks 1b, 2b, 5b, and 6b. when you design with a stratix iv device that has 24 banks, the quartus ii software limits the available banks common to all devices selected if a hardcopy iv device is selected as a companion pair. if you try to assign i/o pins to a non-existent bank in a mapping or companion device, the quartus ii compilation halts with an error. the following are examples of quartus ii compilation errors: error: i/o pins (xx) assigned in i/o bank 1b. the i/o bank does not exist in the selected device error: device migration enabled -- compilation may have failed due to additional constraints when migrating error: can't fit design in device
3?10 chapter 3: mapping stratix iv device resources to hardcopy iv devices designing with hardcopy iv i/os hardcopy iv device handbook, volume 2 ? january 2010 altera corporation the sizes of each bank are 24, 26, 32, 40, 42, 48, or 50 i/o pins (including up to two dedicated input pins per bank). during mapping from a smaller device to a larger device, the bank size increases or remains the same but never decreases. for example, banks may increase from a size of 24 i/o to a bank of size 32, 40, 48, or 50 i/o, but will never decrease. table 3?7 summarizes the number of i/o pins available in each i/o bank for all companion pairs of stratix iv gx and hardcopy iv gx devices.
chapter 3: mapping stratix iv device resources to hardcopy iv devices 3?11 designing with hardcopy iv i/os ? january 2010 altera corporation hardcopy iv device handbook, volume 2 tab le 3 ?7 . hardcopy iv gx asic and stratix iv gx fpga i/o bank and pin count mapping (part 1 of 2) (1) bank 780-pin fineline bga (2) 780-pin fineline bga (2) 780-pin fineline bga (2) 1152-pin fineline bga (3) 1152-pin fineline bga (3) 1517-pin fineline bga (4) hardcopy iv gx asic stratix iv gx fpga prototype hardcopy iv gx asic stratix iv gx fpga prototype (5) hardcopy iv gx asic stratix iv gx fpga prototype (5) hardcopy iv gx asic stratix iv gx fpga prototype hardcopy iv gx asic stratix iv gx fpga prototype hardcopy iv gx asic stratix iv gx fpga prototype HC4GX15 ep4sgx70 ep4sgx110 ep4sgx180 ep4sgx230 HC4GX15 ep4sgx290 ep4sgx360 hc4gx25l ep4sgx290 ep4sgx360 hc4gx25l (8) ep4sgx110 hc4gx25l hc4gx25f hc4gx35f ep4sgx180 ep4sgx230 ep4sgx290 ep4sgx360 ep4sgx530 (6) hc4gx35f ep4sgx180 ep4sgx230 ep4sgx290 ep4sgx360 ep4sgx530 (7) 1a 32 32 ? ? ? ? 32 32 48 48 48 48 1b????????? ? ? ? 1c 26 26 1 1 1 1 26 26 42 42 42 42 2a 32 32 ? ? ? ? ? ? ? ? 48 48 2b????????? ? ? ? 2c 26 26 ? ? ? ? ? ? ? ? 42 42 3a 40 40 40 40 40 40 40 40 40 40 40 40 3b????????24 24 24 24 3c 24 24 24 32 32 32 24 24 32 32 32 32 4a 40 40 40 40 40 40 40 40 40 40 40 40 4b????????24 24 24 24 4c 24 24 24 32 32 32 24 24 32 32 32 32 5a????????? ? 48 48 5b????????? ? ? ? 5c????????? ? 42 42 6a ? ? ? ? ? ? 32 32 48 48 48 48 6b????????? ? ? ? 6c ? ? ? ? ? ? 26 26 42 42 42 42
3?12 chapter 3: mapping stratix iv device resources to hardcopy iv devices designing with hardcopy iv i/os hardcopy iv device handbook, volume 2 ? january 2010 altera corporation table 3?8 and ta b l e 3 ?9 summarize the number of i/o pins available in each i/o bank for all companion pairs of stratix iv e and hardcopy iv e devices for socket replacement and non-socket replacement flows, respectively. 7a 40 40 40 40 40 40 40 40 40 40 40 40 7b ? ? ? ? ? ? ? ? 24 24 24 24 7c 24 24 24 32 32 32 24 24 32 32 32 32 8a 40 40 40 40 40 40 40 40 40 40 40 40 8b ? ? ? ? ? ? ? ? 24 24 24 24 8c 24 24 24 32 32 32 24 24 32 32 32 32 tota l i/o 372 372 257 289 289 289 372 372 564 564 744 744 notes to table 3?7 : (1) user i/o pin counts are preliminary. (2) all i/o pin counts include four dedicated clock inputs (clk1p, clk1n, clk3p, clk3n) that can be used for data inputs. the ep 4sgx290 and ep4sgx360 mappings include only one dedicated clock input (clk1p) that can be used as data input. (3) all i/o pin counts include four dedicated clock inputs (clk1p, clk1n, clk10p, and clk10n) that can be used as data inputs. (4) all i/o pin counts include eight dedicated clock inputs (clk1p, clk1n, clk3p, clk3n, clk8p, clk8n, clk10p, and clk10n) that can be used as data inputs. (5) the ep4sgx290 and ep4sgx360 fpga s are offered in the h780 package. (6) the ep4sgx530 fpga is offered in th e h1152 package. (7) the ep4sgx530 fpga is offered in th e h1517 package. (8) the hc4gx25l has 564 i/os, but only 372 i/os can be mapped if the fpga ep4sgx110 is selected. ta ble 3? 7. hardcopy iv gx asic and stratix iv gx fpga i/o bank and pin count mapping (part 2 of 2) (1) bank 780-pin fi neline bga (2) 780-pin fineline bga (2) 780-pin fineline bga (2) 1152-pin fi neline bga (3) 1152-pin fineline bga (3) 1517-pin fineline bga (4) hardcopy iv gx asic stratix iv gx fpga prototype hardcopy iv gx asic stratix iv gx fpga prototype (5) hardcopy iv gx asic stratix iv gx fpga prototype (5) hardcopy iv gx asic stratix iv gx fpga prototype hardcopy iv gx asic stratix iv gx fpga prototype hardcopy iv gx asic stratix iv gx fpga prototype HC4GX15 ep4sgx70 ep4sgx110 ep4sgx180 ep4sgx230 HC4GX15 ep4sgx290 ep4sgx360 hc4gx25l ep4sgx290 ep4sgx360 hc4gx25l (8) ep4sgx110 hc4gx25l hc4gx25f hc4gx35f ep4sgx180 ep4sgx230 ep4sgx290 ep4sgx360 ep4sgx530 (6) hc4gx35f ep4sgx180 ep4sgx230 ep4sgx290 ep4sgx360 ep4sgx530 (7)
chapter 3: mapping stratix iv device resources to hardcopy iv devices 3?13 designing with hardcopy iv i/os ? january 2010 altera corporation hardcopy iv device handbook, volume 2 tab le 3 ?8 . hardcopy iv e asic and stratix iv e fpga protyotype i/o pin bank and pin count mapping with socket replacement flow (note 1) bank 780-pin fineline bga (2) 780-pin fineline bga (2) 1152-pin fineline bga 1517-pin fineline bga hardcopy iv e asic stratix iv e fpga prototype hardcopy iv e asic stratix iv e fpga prototype hardcopy iv e asic (2) stratix iv e fpga prototype hardcopy iv e asic (3) stratix iv e fpga prototype hc4e25w ep4se230 ep4se360 (4) hc4e25f ep4se230 ep4se360 (4) hc4e35f hc4e35l ep4se360 ep4se530 (5) ep4se820 (5) hc4e35l hc4e35f ep4se530 (6) ep4se820 1a 24 32 32 32 48 48 50 50 1b???????24 1c 42 26 26 26 42 42 42 42 2a 24 32 32 32 48 48 50 50 2b???????24 2c 42 26 26 26 42 42 42 42 3a?40404040404848 3b????24244848 3c 32 24 24 24 32 32 32 32 4a?40404040404848 4b????24244848 4c 32 24 24 24 32 32 32 32 5a 24 32 32 32 48 48 50 50 5b???????24 5c 42 26 26 26 42 42 42 42 6a 24 32 32 32 48 48 50 50 6b???????24 6c 42 26 26 26 42 42 42 42 7a?40404040404848 7b????24244848 7c 32 24 24 24 32 32 32 32 8a?40404040404848 8b????24244848 8c 32 24 24 24 32 32 32 32 total i/o 392 488 488 488 744 744 880 976 notes to table 3?8 : (1) user i/o pin counts are preliminary. (2) all i/o pin counts include eight dedicated clock inputs (clk1p, clk1n, clk3p, clk3n, clk8p, clk8n, clk10p and clk10n) that c an be used for data inputs. (3) all i/o pin counts include eight dedicated clock inputs (clk1p, clk1n, clk3p, clk3n, clk8p, clk8n, clk10p and clk10n) and ei ght dedicated corner pll clock inputs (pll_l1_clkp, pll_l1_clkn, pll_l4_clkp, pll_l4_clkn, pll_r4_clkp, pll_r4_clkn, pll_r1_clkp, and pll_r1_clkn) that can be used for data inputs. (4) the ep4se360 fpga is offered in the h780 package. (5) the ep4se530 and ep4se820 fpgas are offered in the h1152 package. (6) the ep4se530 fpga is offered in the h1517 package.
3?14 chapter 3: mapping stratix iv device resources to hardcopy iv devices designing with hardcopy iv i/os hardcopy iv device handbook, volume 2 ? january 2010 altera corporation hardcopy iv asics offer the non-socket replacement flow to reduce design board space and cost. because hardcopy iv and stratix iv device packages are different, some stratix iv device i/os are not available in the hardcopy iv device. table 3?9 shows the number of i/os in each bank on stratix iv and hardcopy iv devices for the non-socket replacement flow. tab le 3 ?9 . hardcopy iv e and stratix iv e i/o bank and count mapping with non-socket replacement flow (note 1) bank 484-pin fineline bga 780-pin fineline bga hardcopy iv e asic stratix iv e fpga prototype hc4e25w hc4e25f ep4se230 1a 24 32 1b ? ? 1c 26 26 2a 24 32 2b ? ? 2c 26 26 3a ? 40 3b ? ? 3c 24 24 4a ? 40 4b ? ? 4c 24 24 5a 24 32 5b ? ? 5c 26 26 6a 24 32 6b ? ? 6c 26 26 7a ? 40 7b ? ? 7c 24 24 8a ? 40 8b ? ? 8c 24 24 total i/o 296 488 note to tab l e 3 ?9 : (1) user i/o pin counts are preliminary.
chapter 3: mapping stratix iv device resources to hardcopy iv devices 3?15 designing with hardcopy iv i/os ? january 2010 altera corporation hardcopy iv device handbook, volume 2 hardcopy iv supported i/o standards hardcopy iv asics support the same i/o standards as stratix iv fpgas. table 3?10 lists i/o standards that hardcopy iv asic support. table 3?10. i/o standards and voltage levels for hardcopy iv devices (part 1 of 2) (note 1) i/o standard standard support v cc io (v) v ccpd (v) (pre-driver voltage) v ref (v) (input ref voltage) v tt (v) (board termination voltage) input operation output operation column i/o banks row i/o banks column i/o banks row i/o banks 3.3-v lvttl (2) jesd8-b 3.0/2.5 3.0/2.5 3.0 3.0 3.0 ? ? 3.3-v lvcmos (2) jesd8-b 3.0/2.5 3.0/2.5 3.0 3.0 3.0 ? ? 2.5-v lvttl/lvcmos jesd8-5 3.0/2.5 3.0/2.5 2.5 2.5 2.5 ? ? 1.8-v lvttl/lvcmos jesd8-7 1.8/1.5 1.8/1.5 1.8 1.8 2.5 ? ? 1.5-v lvttl/lvcmos jesd8-11 1.8/1.5 1.8/1.5 1.5 1.5 2.5 ? ? 1.2-v lvttl/lvcmos jesd8-12 1.2 1.2 1.2 1.2 2.5 ? ? 3.0-v pci pci rev 2.1 3.0 3.0 3.0 3.0 3.0 ? ? 3.0-v pci-x pci-x rev 1.0 3.0 3.0 3.0 3.0 3.0 ? ? sstl-2 class i jesd8-9b (3) (3) 2.5 2.5 2.5 1.25 1.25 sstl-2 class ii jesd8-9b (3) (3) 2.5 2.5 2.5 1.25 1.25 sstl-18 class i jesd8-15 (3) (3) 1.8 1.8 2.5 0.90 0.90 sstl-18 class ii jesd8-15 (3) (3) 1.8 1.8 2.5 0.90 0.90 sstl-15 class i ? (3) (3) 1.5 1.5 2.5 0.75 0.75 sstl-15 class ii ? (3) (3) 1.5 ? 2.5 0.75 0.75 hstl-18 class i jesd8-6 (3) (3) 1.8 1.8 2.5 0.90 0.90 hstl-18 class ii jesd8-6 (3) (3) 1.8 1.8 2.5 0.90 0.90 hstl-15 class i jesd8-6 (3) (3) 1.5 1.5 2.5 0.75 0.75 hstl-15 class ii jesd8-6 (3) (3) 1.5 ? 2.5 0.75 0.75 hstl-12 class i jesd8-16a (3) (3) 1.2 1.2 2.5 0.6 0.6 hstl-12 class ii jesd8-16a (3) (3) 1.2 ? 2.5 0.6 0.6 differential sstl-2 class i jesd8-9b (3) (3) 2.5 2.5 2.5 ? 1.25 differential sstl-2 class ii jesd8-9b (3) (3) 2.5 2.5 2.5 ? 1.25 differential sstl-18 class i jesd8-15 (3) (3) 1.8 1.8 2.5 ? 0.90 differential sstl-18 class ii jesd8-15 (3) (3) 1.8 1.8 2.5 ? 0.90 differential sstl-15 class i ? (3) (3) 1.5 1.5 2.5 ? 0.75 differential sstl-15 class ii ? (3) (3) 1.5 ? 2.5 ? 0.75
3?16 chapter 3: mapping stratix iv device resources to hardcopy iv devices designing with hardcopy iv i/os hardcopy iv device handbook, volume 2 ? january 2010 altera corporation external memory interface i/os in stratix iv and hardcopy iv devices as with the stratix iv i/o structure, the redesign of the hardcopy iv i/o structure provides flexible and high-performance support for existing and emerging external memory standards including ddr3, ddr2, ddr sdram, qdrii+, qdrii sram, and rldram ii. hardcopy iv devices offer the same external memory interface features found in stratix iv devices. these features include delay-locked loops (dlls), phase-locked loops (plls), dynamic on-chip termination (oct), trace mismatch compensation, read and write leveling, deskew circuitry, half data rate (hdr) blocks, 4- to 36-bit dq group widths, and ddr external memory support on all sides of the hardcopy iv device. differential hstl-18 class i jesd8-6 (3) (3) 1.8 1.8 2.5 ? 0.90 differential hstl-18 class ii jesd8-6 (3) (3) 1.8 1.8 2.5 ? 0.90 differential hstl-15 class i jesd8-6 (3) (3) 1.5 1.5 2.5 ? 0.75 differential hstl-15 class ii jesd8-6 (3) (3) 1.5 ? 2.5 ? 0.75 differential hstl-12 class i jesd8-16a (3) (3) 1.2 1.2 2.5 ? 0.60 differential hstl-12 class ii jesd8-16a (3) (3) 1.2 ? 2.5 ? 0.60 lvd s (4) , (5) ansi/tia/ eia-644 (3) (3) 2.5 2.5 2.5 ? ? rsds (6) , (7) ? (3) (3) 2.5 2.5 2.5 ? ? mini-lvds (6) , (7) ? (3) (3) 2.5 2.5 2.5 ? ? lvpecl ? (4) 2.5 ? ? 2.5 ? ? notes to ta bl e 3? 10 : (1) v ccpd is either 2.5 or 3.0 v. for v ccio = 3.0 v, v ccpd = 3.0 v. for v ccio = 2.5 v or less, v ccpd = 2.5 v. (2) the 3.3-v lvttl/lvcmos standard is supported us ing vccio at 3.0 v. (3) single-ended hstl/sstl, differential sstl/hstl, and lvds input buffers are powered by v ccpd . row i/o banks support both true differential input buffers and true differential output buffers. column i/o banks support true differential input buffers, but not true diff erential output buffers. i/o pins are organized in pairs to support differential standards. column i/o differential hstl and sstl inputs use lvds differ ential input buffers without on-chip r d support. (4) column i/o banks support lvpecl i/o standards for input clock operation. clock inputs on column i/o are powered by v ccclkin when configured as differential clock input. they are powered by v ccio when configured as single-ended clock input. differential clock inputs in row i/o are powered by v ccpd. (5) column and row i/o banks support lvds outputs using two single-ended output buffers, an external one-resistor (lvds_e_1r), a nd a three-resistor (lvds_e_3r) network. (6) row i/o banks support rsds and mini-lvds i/o standards using a dedicated lvds output buffer without a resistor network. (7) column and row i/o banks support rsds and mini-lvds i/o standards using two single-ended output buffers with one-resistor (r sds_e_1r and mini-lvds_e_1r) and three-resistor (rsds_e_3r and mini-lvds_e_3r) networks. table 3?10. i/o standards and voltage levels for hardcopy iv devices (part 2 of 2) (note 1) i/o standard standard support v cc io (v) v ccpd (v) (pre-driver voltage) v ref (v) (input ref voltage) v tt (v) (board termination voltage) input operation output operation column i/o banks row i/o banks column i/o banks row i/o banks
chapter 3: mapping stratix iv device resources to hardcopy iv devices 3?17 designing with hardcopy iv i/os ? january 2010 altera corporation hardcopy iv device handbook, volume 2 as with stratix iv devices, hardcopy iv devices allow a memory interface to be located on any side of the device. the only limitation is if the left and right sides have to be reserved for high-speed i/o applications, as described in the following section. table 3?11 and table 3?12 show the number of dq and dqs buses supported per companion device pair. table 3?11. number of dqs/dq groups in hardcopy iv gx devices per side (note 1) hardcopy iv gx asic package side x4 (2) x8/x9 x16/x18 x32/x36 HC4GX15la 780-pin fineline bga left 14 6 2 0 bottom 17 8 2 0 right0000 top17820 HC4GX15l 780-pin fineline bga left0000 bottom 17 8 2 0 right0000 top17820 hc4gx25 1152-pin fineline bga left 13 6 2 0 bottom 26 12 4 0 right 13 6 2 0 top 26 12 4 0 hc4gx35 1152-pin fineline bga left 13 6 2 0 bottom 26 12 4 0 right 13 6 2 0 top 26 12 4 0 hc4gx35 1517-pin fineline bga left 26 12 4 0 bottom 26 12 4 0 right 26 12 4 0 top 26 12 4 0 notes to ta bl e 3? 11 : (1) these numbers are preliminary. (2) some of the dqs and dq pins can also be used as r up /r dn pins. you lose one dqs/dq group if you use these pins as r up /r dn pins for oct calibration. make sure that the dqs/dq groups that you have chosen are not also used for oct calibration. table 3?12. number of dqs/dq groups in hardcopy iv e devices per side (note 1) (part 1 of 2) hardcopy iv e asic package side x4 (2) x8/x9 x16/x18 x32/x36 hc4e25 484-pin fineline bga left 12 4 0 0 bottom5200 right 12 4 0 0 top5200
3?18 chapter 3: mapping stratix iv device resources to hardcopy iv devices designing with hardcopy iv i/os hardcopy iv device handbook, volume 2 ? january 2010 altera corporation f for more information about external memory interfaces, refer to the external memory interfaces in hardcopy iv devices chapter. mapping stratix iv high-speed differential i/o interfaces with hardcopy iv hardcopy iv asics have the same dedicated circuitry as stratix iv devices for high-speed differential i/o support: differential i/o buffer transmitter serializer receiver deserializer data realignment dynamic phase aligner (dpa) synchronizer (fifo buffer) analog plls (located on left and right sides of the device) for high-speed differential interfaces, hardcopy iv devices support the following differential i/o standards: low-voltage differential signaling (lvds) mini-lvds reduced swing differential signaling (rsds) differential hstl differential sstl hc4e25 780-pin fineline bga left 14 6 2 0 bottom 17 8 2 0 right 14 6 2 0 top17820 hc4e35 1152-pin fineline bga left 26 12 4 0 bottom 26 12 4 0 right 26 12 4 0 top 26 12 4 0 hc4e35 1517-pin fineline bga left 26 12 4 0 bottom 38 18 8 4 right 26 12 4 0 top 38 18 8 4 notes to ta bl e 3? 12 : (1) these numbers are preliminary. (2) some of the dqs and dq pins can also be used as r up /r dn pins. you lose one dqs/dq group if you use these pins as r up /r dn pins for oct calibration. make sure that the dqs/dq groups that you have chosen are not also used for oct calibration. table 3?12. number of dqs/dq groups in hardcopy iv e devices per side (note 1) (part 2 of 2) hardcopy iv e asic package side x4 (2) x8/x9 x16/x18 x32/x36
chapter 3: mapping stratix iv device resources to hardcopy iv devices 3?19 designing with hardcopy iv i/os ? january 2010 altera corporation hardcopy iv device handbook, volume 2 hardcopy iv asics support lvds on all i/o banks. true lvds makes use of dedicated lvds i/o buffers that are optimized for performance. there are true lvds input and output buffers at the left and right side i/o banks. there are true lvds input buffers on the top and bottom i/o banks only. you can configure all i/os in all banks as emulated lvds output buffers. emulated output buffers make use of single-ended buffers and an external resistor network to mimic lvds operation. emulated lvds is useful for low-speed, low-voltage differential applications. f for more information about high-speed i/o performance, refer to the high speed differential i/o interface with dpa in hardcopy iv devices chapter . all dedicated circuitry for high-speed differential i/o applications are located in the left and right i/o banks of the stratix iv and hardcopy iv devices. the top and bottom i/o banks also have support for high-speed receiver applications that do not require the use of the dpa, synchronizer, data realignment, and differential termination. top and bottom differential i/o buffers have a slower data rate than the high-speed receivers on the left and right i/o banks. table 3?13 shows the lvds channels supported in hardcopy iv gx and stratix iv gx companion devices. table 3?13. lvds channels supported in hardcopy iv gx and stratix iv gx companion devices (note 1) , (2) (part 1 of 3) bank 780-pin fineline bga 1152-pin fineline bga 1152-pin fineline bga 1152-pin fineline bga 1517-pin fineline bga hardcopy iv gx asic stratix iv gx fpga prototype hardcopy iv gx asic stratix iv gx fpga prototype hardcopy iv gx asic stratix iv gx fpga prototype hardcopy iv gx asic stratix iv gx fpga prototype hardcopy iv gx asic stratix iv gx fpga prototype HC4GX15 ep4sgx70 ep4sgx110 ep4sgx180 ep4sgx230 hc4gx25 ep4sgx110 hc4gx25 ep4sgx180 ep4sgx230 ep4sgx290 ep4sgx360 ep4sgx530 (3) hc4gx35 ep4sgx230 ep4sgx360 ep4sgx530 (3) hc4gx35 ep4sgx180 ep4sgx230 ep4sgx290 ep4sgx360 ep4sgx530 (4) 1a 8rx + 8tx 8rx + 8tx 8rx + 8tx 8rx + 8tx 12rx + 12tx 12rx + 12tx 12rx + 12tx 12rx + 12tx 12rx + 12tx 12rx + 12tx 1b?????????? 1c 6rx + 6tx 6rx + 6tx 6rx + 6tx 6rx + 6tx 10rx + 10tx 10rx + 10tx 10rx + 10tx 10rx + 10tx 10rx + 10tx 10rx + 10tx 2a 8rx + 8tx 8rx + 8tx 8rx + 8tx 8rx + 8tx - 12rx + 12tx - 12rx + 12tx 12rx + 12tx 12rx + 12tx 2b?????????? 2c 6rx + 6tx 6rx + 6tx 6rx + 6tx 6rx + 6tx - 10rx + 10tx - 10rx + 10tx 10rx + 10tx 10rx + 10tx 3a (5) 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 3b (5) ? ? ? ? 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx
3?20 chapter 3: mapping stratix iv device resources to hardcopy iv devices designing with hardcopy iv i/os hardcopy iv device handbook, volume 2 ? january 2010 altera corporation 3c (5) 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 4a (5) 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 4b (5) ? ? ? ? 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx 4c (5) 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 5a ? ? ? ? ? 12rx + 12tx ? 12rx + 12tx 12rx + 12tx 12rx + 12tx 5b????? - ???? 5c ? ? ? ? ? 10rx + 10tx ? 10rx + 10tx 10rx + 10tx 10rx + 10tx 6a ? ? ? 6rx + 6tx 12rx + 12tx 12rx + 12tx 12rx + 12tx 12rx + 12tx 12rx + 12tx 12rx + 12tx 6b?????????? 6c ? ? ? 6rx + 6tx 10rx + 10tx 10rx + 10tx 10rx + 10tx 10rx + 10tx 10rx + 10tx 10rx + 10tx 7a (5) 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 7b (5) ? ? ? ? 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx 7c (5) 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8a (5) 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 8b (5) ? ? ? ? 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx table 3?13. lvds channels supported in hardcopy iv gx and stratix iv gx companion devices (note 1) , (2) (part 2 of 3) bank 780-pin fineline bga 1152-pin fineline bga 1152-pin fineline bga 1152-pin fineline bga 1517-pin fineline bga hardcopy iv gx asic stratix iv gx fpga prototype hardcopy iv gx asic stratix iv gx fpga prototype hardcopy iv gx asic stratix iv gx fpga prototype hardcopy iv gx asic stratix iv gx fpga prototype hardcopy iv gx asic stratix iv gx fpga prototype HC4GX15 ep4sgx70 ep4sgx110 ep4sgx180 ep4sgx230 hc4gx25 ep4sgx110 hc4gx25 ep4sgx180 ep4sgx230 ep4sgx290 ep4sgx360 ep4sgx530 (3) hc4gx35 ep4sgx230 ep4sgx360 ep4sgx530 (3) hc4gx35 ep4sgx180 ep4sgx230 ep4sgx290 ep4sgx360 ep4sgx530 (4)
chapter 3: mapping stratix iv device resources to hardcopy iv devices 3?21 designing with hardcopy iv i/os ? january 2010 altera corporation hardcopy iv device handbook, volume 2 table 3?15 and table 3?14 show the lvds channels supported in hardcopy iv e and stratix iv e companion devices for the socket replacement and non-socket replacement flows, respectively. 8c (5) 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx 6rx + 6etx or 12etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx notes to ta bl e 3? 13 : (1) channel counts are preliminary. (2) rx = true lvds input buffers with oct rd, tx = true lvds output buffers, and etx = emulated lvds output buffers (either lvds _e_1r or lvds_e_3r). (3) the ep4sgx530 fpga is offered only in the h1152 package. (4) the ep4sgx530 fpga is offered only in the h1517 package. (5) top and bottom i/o banks do not have dpa, synchronizer, data realignment, and differential termination support in stratix iv gx and hardcopy iv gx devices. use left and right i/o banks if these features and maximum performance is required. table 3?13. lvds channels supported in hardcopy iv gx and stratix iv gx companion devices (note 1) , (2) (part 3 of 3) bank 780-pin fineline bga 1152-pin fineline bga 1152-pin fineline bga 1152-pin fineline bga 1517-pin fineline bga hardcopy iv gx asic stratix iv gx fpga prototype hardcopy iv gx asic stratix iv gx fpga prototype hardcopy iv gx asic stratix iv gx fpga prototype hardcopy iv gx asic stratix iv gx fpga prototype hardcopy iv gx asic stratix iv gx fpga prototype HC4GX15 ep4sgx70 ep4sgx110 ep4sgx180 ep4sgx230 hc4gx25 ep4sgx110 hc4gx25 ep4sgx180 ep4sgx230 ep4sgx290 ep4sgx360 ep4sgx530 (3) hc4gx35 ep4sgx230 ep4sgx360 ep4sgx530 (3) hc4gx35 ep4sgx180 ep4sgx230 ep4sgx290 ep4sgx360 ep4sgx530 (4) table 3?14. lvds channels supported in hardcopy iv e and stratix iv e companion devices with socket replacement flow (note 1) , (2) (part 1 of 3) bank 780-pin fineline bga 1152-pin fineline bga 1517-pin fineline bga hardcopy iv e asic stratix iv e fpga prototype hardcopy iv e asic stratix iv e fpga prototype hardcopy iv e asic stratix iv e fpga prototype hc4e25 ep4se230 ep4se360 (3) hc4e35 ep4se360 ep4se530 (4) ep4se820 (4) hc4e35 ep4se530 (5) ep4se820 1a 8rx + 8tx (7) 8rx + 8tx 12rx + 12tx 12rx + 12tx 12rx + 12tx 12rx + 12tx 1b ? ? ? ? ? 6rx + 6tx 1c 6rx + 6tx 6rx + 6tx 10rx + 10tx 10rx + 10tx 10rx + 10tx 10rx + 10tx 2a 8rx + 8tx (7) 8rx + 8tx 12rx + 12tx 12rx + 12tx 12rx + 12tx 12rx + 12tx 2b ? ? ? ? ? 6rx + 6tx 2c 6rx + 6tx 6rx + 6tx 10rx + 10tx 10rx + 10tx 10rx + 10tx 10rx + 10tx 3a (6) 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 12rx + 12etx or 24etx 12rx + 12etx or 24etx 3b (6) ? ? 6rx + 6etx or 12etx 6rx + 6etx or 12etx 12rx + 12etx or 24etx 12rx + 12etx or 24etx
3?22 chapter 3: mapping stratix iv device resources to hardcopy iv devices designing with hardcopy iv i/os hardcopy iv device handbook, volume 2 ? january 2010 altera corporation 3c (6) 6rx + 6etx or 12etx 6rx + 6etx or 12etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 4a (6) 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 12rx + 12etx or 24etx 12rx + 12etx or 24etx 4b (6) ? ? 6rx + 6etx or 12etx 6rx + 6etx or 12etx 12rx + 12etx or 24etx 12rx + 12etx or 24etx 4c (6) 6rx + 6etx or 12etx 6rx + 6etx or 12etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 5a 8rx + 8tx (7) 8rx + 8tx 12rx + 12tx 12rx + 12tx 12rx + 12tx 12rx + 12tx 5b ? ? ? ? ? 6rx + 6tx 5c 6rx + 6tx 6rx + 6tx 10rx + 10tx 10rx + 10tx 10rx + 10tx 10rx + 10tx 6a 8rx + 8tx (7) 8rx + 8tx 12rx + 12tx 12rx + 12tx 12rx + 12tx 12rx + 12tx 6b ? ? ? ? ? 6rx + 6tx 6c 6rx + 6tx 6rx + 6tx 10rx + 10tx 10rx + 10tx 10rx + 10tx 10rx + 10tx 7a (6) 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 12rx + 12etx or 24etx 12rx + 12etx or 24etx 7b (6) ? ? 6rx + 6etx or 12etx 6rx + 6etx or 12etx 12rx + 12etx or 24etx 12rx + 12etx or 24etx 7c (6) 6rx + 6etx or 12etx 6rx + 6etx or 12etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8a (6) 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 10rx + 10etx or 20etx 12rx + 12etx or 24etx 12rx + 12etx or 24etx 8b (6) ? ? 6rx + 6etx or 12etx 6rx + 6etx or 12etx 12rx + 12etx or 24etx 12rx + 12etx or 24etx table 3?14. lvds channels supported in hardcopy iv e and stratix iv e companion devices with socket replacement flow (note 1) , (2) (part 2 of 3) bank 780-pin fineline bga 1152-pin fineline bga 1517-pin fineline bga hardcopy iv e asic stratix iv e fpga prototype hardcopy iv e asic stratix iv e fpga prototype hardcopy iv e asic stratix iv e fpga prototype hc4e25 ep4se230 ep4se360 (3) hc4e35 ep4se360 ep4se530 (4) ep4se820 (4) hc4e35 ep4se530 (5) ep4se820
chapter 3: mapping stratix iv device resources to hardcopy iv devices 3?23 designing with hardcopy iv i/os ? january 2010 altera corporation hardcopy iv device handbook, volume 2 8c (6) 6rx + 6etx or 12etx 6rx + 6etx or 12etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx 8rx + 8etx or 16etx notes to ta bl e 3? 14 : (1) channel counts are preliminary. (2) rx = true lvds input buffers with oct rd, tx = true lvds output buffers, and etx = emulated lvds output buffers (either lvds _e_1r or lvds_e_3r). (3) the ep4se360 fpga is offe red only in the h780 package. (4) the ep4se530 and ep4se820 fpgas ar e offered only in the h1152 package. (5) the ep4se530 fpga is offered only in h1517 package. (6) top and bottom i/o banks do not have dpa, synchronizer, data realignment, and differential termination support in stratix iv e and hardcopy iv e devices. use left and right i/o banks if these features and maximum performance is required. (7) when the hardcopy iv e devices mapped to use 780-pin fineline bga wire bond package, i/o banks 1a, 2a , 5a, and 6a can suppor t 6 pairs of lvds channel (6rx + 6tx) only. table 3?14. lvds channels supported in hardcopy iv e and stratix iv e companion devices with socket replacement flow (note 1) , (2) (part 3 of 3) bank 780-pin fineline bga 1152-pin fineline bga 1517-pin fineline bga hardcopy iv e asic stratix iv e fpga prototype hardcopy iv e asic stratix iv e fpga prototype hardcopy iv e asic stratix iv e fpga prototype hc4e25 ep4se230 ep4se360 (3) hc4e35 ep4se360 ep4se530 (4) ep4se820 (4) hc4e35 ep4se530 (5) ep4se820 table 3?15. lvds channels supported in hardcopy iv e and stratix iv e companion devices with non-socket replacement flow (note 1) , (2) , (3) (part 1 of 2) bank 484-pin fineline bga 780-pin fineline bga hardcopy iv e asic stratix iv e fpga prototype hc4e25 ep4se230 1a 6rx + 6tx 8rx + 8tx 1b ? ? 1c 6rx + 6tx 6rx + 6tx 2a 6rx + 6tx 8rx + 8tx 2b ? ? 2c 6rx + 6tx 6rx + 6tx 3a (3) ? 10rx + 10etx or 20etx 3b (3) ?? 3c (3) 6rx + 6etx or 12etx 6rx + 6etx or 12etx 4a (3) ? 10rx + 10etx or 20etx
3?24 chapter 3: mapping stratix iv device resources to hardcopy iv devices designing with hardcopy iv i/os hardcopy iv device handbook, volume 2 ? january 2010 altera corporation 4b (3) ?? 4c (3) 6rx + 6etx or 12etx 6rx + 6etx or 12etx 5a 6rx + 6tx 8rx + 8tx 5b ? ? 5c 6rx + 6tx 6rx + 6tx 6a 6rx + 6tx 8rx + 8tx 6b ? ? 6c 6rx + 6tx 6rx + 6tx 7a (3) ? 10rx + 10etx or 20etx 7b (3) ?? 7c (3) 6rx + 6etx or 12etx 6rx + 6etx or 12etx 8a (3) ? 10rx + 10etx or 20etx 8b (3) ?? 8c (3) 6rx + 6etx or 12etx 6rx + 6etx or 12etx notes to table 3?15 : (1) channel counts are preliminary. (2) rx = true lvds input buffers with oct rd, tx = true lvds output buffers, and etx = emulated lvds output buffers (either lvds_e_1r or lvds_e_3r). (3) top and bottom i/o banks do not have dpa, synchronizer, data realignment, and differential termination support in stratix iv e and hardcopy iv e devices. use left and right i/o banks if these features and maximum performance is required. table 3?15. lvds channels supported in hardcopy iv e and stratix iv e companion devices with non-socket replacement flow (note 1) , (2) , (3) (part 2 of 2) bank 484-pin fineline bga 780-pin fineline bga hardcopy iv e asic stratix iv e fpga prototype hc4e25 ep4se230
chapter 3: mapping stratix iv device resources to hardcopy iv devices 3?25 hardcopy iv pll planning and utilization ? january 2010 altera corporation hardcopy iv device handbook, volume 2 hardcopy iv pll planning and utilization hardcopy iv devices offer up to 12 plls that support the same features as stratix iv plls. the same nomenclature is used for hardcopy iv and stratix iv plls that follow their geographical location in the device floorplan. the plls that reside on the top and bottom sides of the device are named pll_t1 , pll_t2 , pll_b1 , and pll_b2 ; the plls that reside on the left and right sides of the device are named pll_l1 , pll_l2 , pll_l3 , pll_l4 , pll_r1 , pll_r2 , pll_r3 , and pll_r4 , respectively. table 3?16 and table 3?17 show the number of plls available in hardcopy iv devices and their companion stratix iv devices. table 3?16. hardcopy iv gx and stratix iv gx pll mapping options (note 1) pll 780-pin fineline bga 780-pin fineline bga 1152-pin fineline bga 1152-pin fineline bga 1517-pin fineline bga hardcopy iv gx asic stratix iv gx fpga prototype hardcopy iv gx asic stratix iv gx fpga prototype hardcopy iv gx asic stratix iv gx fpga prototype hardcopy iv gx asic stratix iv gx fpga prototype hardcopy iv gx asic stratix iv gx fpga prototype HC4GX15 ep4sgx70 ep4sgx110 ep4sgx180 ep4sgx230 ep4sgx290 (2) ep4sgx360 (2) hc4gx25 ep4sgx290 (2) ep4sgx360 (2) hc4gx25 ep4sgx110 ep4sgx180 ep4sgx230 ep4sgx290 ep4sgx360 ep4sgx530 (3) hc4gx35 ep4sgx230 ep4sgx360 ep4sgx530 (3) hc4gx35 ep4sgx180 ep4sgx230 ep4sgx290 ep4sgx360 ep4sgx530 (4) pll_l1 ? ????????? pll_l2 v (5) vvvvvvvvv pll_l3 ? ??????? vv pll_l4 ? ????????? pll_t1 vvvvv v v v v v pll_t2 ? ? vvvvvvvv pll_b1 vvvvv v v v v v pll_b2 ? ? vvvvvvvv pll_r1 ? ????????? pll_r2 ? ? vvvvvvvv pll_r3 ? ??????? vv pll_r4 ? ????????? notes to ta bl e 3? 16 : (1) the pll availability table is preliminary. it is best to design with the quartus ii software to check if your design can use all available plls. (2) the ep4sgx290 and ep4sgx360 fpgas are offered only in the h780 package. (3) the ep4sgx530 fpga is offered only in the h1152 package. (4) the ep4sgx530 fpga is offered only in the h1517 package. (5) the HC4GX15 does not have pll_l2 if the fpga ep4sgx290 or ep4sgx360 is selected.
3?26 chapter 3: mapping stratix iv device resources to hardcopy iv devices hardcopy iv memory blocks hardcopy iv device handbook, volume 2 ? january 2010 altera corporation f for more information about hardcopy iv plls, refer to the clock networks and plls in hardcopy iv devices chapter. hardcopy iv memory blocks trimatrix memory in hardcopy iv devices supports the same memory functions and features as stratix iv devices. you can independently configure each embedded memory block to be a single- or dual-port ram, fifo, rom, or shift register via the megawizard ? plug-in manager in the quartus ii software. hardcopy iv embedded memory consists of mlab, m9k, and m144k memory blocks, and has one-to-one mapping from stratix iv memory. however, the number of available memory blocks differs based on physical density, package, and stratix iv device to hardcopy iv asic mapping paths. the quartus ii software may not allow all available stratix iv memory types to fit into a selected hardcopy iv device if your design has a very high resource utilization and performance target. 1 altera recommends that you compile your design with the quartus ii software and verify the device resource guide to check for available resources in the hardcopy iv device. table 3?17. hardcopy iv e and stratix iv e pll mapping options (note 1) pll 484-pin fineline bga 780-pin fineline bga 780-pin fineline bga 1152-pin fineline bga 1517-pin fineline bga hardcopy iv e asic stratix iv e fpga prototype hardcopy iv e asic stratix iv e fpga prototype hardcopy iv e asic stratix iv e fpga prototype hardcopy iv e asic stratix iv e fpga prototype hc4e25 ep4se230 hc4e25 ep4se230 ep4se360 (2) hc4e35 ep4se360 ep4se530 (3) ep4se820 (3) hc4e35 ep4se530 (4) ep4se820 pll_l1 ?????? vv pll_l2 vvvvvvvv pll_l3 ???? vvvv pll_l4 ?????? vv pll_t1 vvvvvvvv pll_t2 ???? vvvv pll_b1 vvvvvvvv pll_b2 ???? vvvv pll_r1 ?????? vv pll_r2 vvvvvvvv pll_r3 ???? vvvv pll_r4 ?????? vv notes to ta bl e 3? 17 : (1) the pll availability table is preliminary. it is best to design with the quartus ii software to check if your design can use all available plls. (2) the ep4se360 fpga is offe red only in the h780 package. (3) the ep4se530 and ep4se820 fpgas ar e offered only in the h1152 package. (4) the ep4se530 fpga is offe red only in the h1517 package.
chapter 3: mapping stratix iv device resources to hardcopy iv devices 3?27 hardcopy iv memory blocks ? january 2010 altera corporation hardcopy iv device handbook, volume 2 f for information about using the hardcopy device resource guide, refer to the quartus ii support for hardcopy series devices chapter in volume 1 of the quartus ii handbook. functionally, memory in hardcopy iv and stratix iv devices is identical. memory blocks can implement various types of memory with or without parity, including true dual-port, simple dual-port, and single-port ram, rom, and fifo. mlab implementation in stratix iv devices, mlabs are dedicated blocks and can be configured for regular logic functions or memory functions. in hardcopy iv devices, mlab memory blocks are implemented using hcells. the quartus ii software maps the stratix iv mlab function to the appropriate memory hcell macro that preserves memory function. this allows you to use the hardcopy iv core fabric more efficiently, freeing up unused hcells for alm or dsp functions. mlab, m9k, and m144k utilization hardcopy iv mlab, m9k, and m144k block functionality is similar to stratix iv memory blocks; however, you cannot pre-load hardcopy iv mlab, m9k, and m144k blocks with a .mif file when using them as ram. ensure that your stratix iv design does not require .mif files if the memory blocks are used as ram. however, if memory blocks are used as rom, they are mask-programmed to the design?s rom contents. 1 you can use the altmem_init megafunction to initialize a ram block after power-up for stratix iv and hardcopy iv devices. this megafunction reads from a rom defined with the megafunction and writes to the ram after power-up. this function allows you to have initialized contents on a ram block. refer to the quartus ii help for implementation information about this function. unlike stratix iv fpgas, hardcopy iv mlab, m9k, and m144k ram contents are unknown after power-up. however, like stratix iv devices, all hardcopy iv memory output registers power-up cleared, if used. when designing hardcopy iv memory blocks as ram, altera recommends a write-before-read of the memory block to avoid reading unknown initial power-up data conditions. if the hardcopy iv memory block is designated as rom, it powers up with the rom contents. one advantage over stratix iv ram blocks is that unused m9k and m144k blocks are disconnected from the power rails and mlabs are only implemented as required by your design. these unused resources do not contribute to overall power consumption on hardcopy iv devices. f for a list of supported features in hardcopy iv memory blocks, refer to the trimatrix embedded memory blocks in hardcopy iv devices chapter.
3?28 chapter 3: mapping stratix iv device resources to hardcopy iv devices using jtag features in hardcopy iv devices hardcopy iv device handbook, volume 2 ? january 2010 altera corporation using jtag features in hardcopy iv devices hardcopy iv asics support the same boundary-scan test (bst) functionality as stratix iv fpgas. however, no reconfiguration is possible because hardcopy iv devices are mask-programmed. therefore, hardcopy iv devices do not support instructions to reconfigure the device through the jtag pins. hardcopy iv boundary scan lengths also differ from stratix iv devices. f for information about hardcopy iv jtag functionality and support, refer to the ieee 1149.1 jtag boundary scan testing in hardcopy iv devices chapter. power-up and configuration pin compatibility with stratix iv devices when designing a board for both hardcopy iv and stratix iv devices, most configuration pins required by the stratix iv device are not required by the hardcopy iv device. the functions of these stratix iv configuration pins are not carried over to the hardcopy iv companion device because hardcopy iv devices are not programmable. to simplify the board connection for these configuration pins, altera recommends minimizing the power-up and configuration pins that do not carry over from a stratix iv device to a hardcopy iv device. you should ensure that the board can be used for both stratix iv and hardcopy iv devices. configuration pins for both devices must be properly connected. otherwise, separate boards are required for the two devices. table 3?18 lists the main and optional functions on the configuration pins used by stratix iv and hardcopy iv devices. table 3?18. mapping configuration pins into hardcopy iv devices (part 1 of 2) (note 1), (2), (3), (4) stratix iv fpga prototype hardcopy iv asic board connection main function optional function main function optional function msel[2..0] ? ? ? not required and no connection on board. nconfig (5) ? nconfig ? required connection. i/o pin data0 i/o pin data0 data[0] retains both user i/o and optional epcs access functions. data [7..1] retains user i/o functions only. i/o pin data [7..1] i/o pin ? dclk ? dclk ? no connection on board, except when epcs access is required in user mode. i/o pin init_done (6) i/o pin init_done retains the same i/o functions from stratix iv. i/o pin clkusr i/o pin ? retains the same i/o functions from stratix iv except clkusr , because no device programming is required. nstatus (5) ? nstatus ? required connection. conf_done (5) ? conf_done ? required connection. nce ? nce ? required connection. nceo ? nceo ? not required and no connection on board. porsel ? porsel ? required connection. i/o pin asdo i/o pin asdo no connection on board, except when epcs access is required in user mode.
chapter 3: mapping stratix iv device resources to hardcopy iv devices 3?29 power-up and configuration pin compatibility with stratix iv devices ? january 2010 altera corporation hardcopy iv device handbook, volume 2 i/o pin ncso i/o pin ncso no connection on board, except when epcs access is required in user mode. nio_pullup ? nio_pullup ? required connection. i/o pin crc_error (4) i/o pin ? retains the same i/o functions from stratix iv, but not crc_error , because no device programming is required. i/o pin dev_clrn i/o pin dev_clrn retains the same i/o functions from stratix iv. i/o pin dev_oe i/o pin dev_oe retains the same i/o functions from stratix iv. notes to ta bl e 3? 18 : (1) for correct operation of a hardcopy iv device, pull the nstatus , nconfig , and conf_done pins to v ccpgm . in hardcopy iv devices, these pins are designed with weak internal resistors pulled up to v cc pgm . stratix iv configuration schemes require pull-up resistors on these i/o pins, so they may already be present on the board. you can remove these external pull-up resistors, if doing so does not affect other fpgas on the board. (2) hardcopy iv devices have a maximum v ccio voltage of 3.0 v, but the input i/o pin can tolerate a 3.3 v level. this applies to v ccpgm voltage and all dedicated and dual-purpose pins. (3) for hardcopy iv devices, there is weak pull-up on the nstatus , conf_done , nconfig , and dclk pins. therefore, these pins can be left floating or remain connected to external pull-up resistors. if the epcs is used in user mode as a boot-up ram or data access fo r a nios ? ii processor, dclk , data[0] , asdo , and ncso must be connected to the epcs device. (4) in hardcopy iv devices, crc_error is hard-wired to logic 0 if the crc feature is enabled in stratix iv devices. (5) the porsel pin setting delays the por sequence for both hardcopy iv and stratix iv devices. (6) the init_done settings option is mask-programmed into the device. you must submit these settings to altera with the final design prior to mapping to a hardcopy iv device. the use of the init_done option and other dual-purpose pins (for example, dev_clrn device-wide reset and dev_oe device-wide output enable) are available in the fitter device options section of the quartus ii report file. table 3?18. mapping configuration pins into hardcopy iv devices (part 2 of 2) (note 1), (2), (3), (4) stratix iv fpga prototype hardcopy iv asic board connection main function optional function main function optional function
3?30 chapter 3: mapping stratix iv device resources to hardcopy iv devices power-up and configuration pin compatibility with stratix iv devices hardcopy iv device handbook, volume 2 ? january 2010 altera corporation for both the stratix iv and hardcopy iv devices, the quartus ii software allows you to set the i/o pins listed in table 3?18 as dual-purpose pins (as shown in figure 3?2 ). as dual-purpose pins, they have i/o functionality when the device enters user mode (when init_done is asserted). if these dual-purpose pins are required to configure the stratix iv device, but will be unused after configuration, these pins remain unused on the hardcopy iv device. it is important to consider the state of these pins after power-up and when the device is in user mode. for example, when replacing the stratix iv device with a hardcopy iv device, these pins may be left floating when the configuration device is removed if you assign such pins as inputs. in this case, you will either require an external means to drive them to a stable level, or set the pins to output driving ground. figure 3?2. device and pin options dialog box
chapter 3: mapping stratix iv device resources to hardcopy iv devices 3?31 revision history ? january 2010 altera corporation hardcopy iv device handbook, volume 2 revision history table 3?19 shows the revision history for this document. table 3?19. document revision history date version changes made january 2010 2.1 updated ta bl e 3? 1 , tab le 3 ?2 , table 3?4 , ta bl e 3? 5 , tab le 3 ?6 , table 3?8 , table 3?11 , ta bl e 3? 13 , ta ble 3? 14 , table 3?15 , tab le 3 ?1 7 , and tab le 3 ?1 8 . june 2009 2.0 added table 3?13. updated the following tables: table 3?1, table 3?5, table 3?8, table 3?12, table 3?17, table 3?18, updated figure 3?1. updated ?hardcopy iv and stratix iv mapping options? and ?mapping hardcopy iv and stratix iv i/os and modular i/o banks.? removed ?referenced documents.? december 2008 1.0 initial release.
3?32 chapter 3: mapping stratix iv device resources to hardcopy iv devices revision history hardcopy iv device handbook, volume 2 ? january 2010 altera corporation
? june 2009 altera corporation hardcopy iv device handbook, volume 2 4. matching stratix iv power and configuration requirements with hardcopy iv devices this chapter describes power-up options for both hardcopy ? iv e and hardcopy iv gx devices and provides examples of how to replace fpgas in the system with the hardcopy iv e and hardcopy iv gx devices. both variants of hardcopy iv devices have the same power-up options. configuring an fpga is the process of loading the design data into the device. the altera ? sram-based stratix ? iv fpga requires configuration each time the device is powered up. after the device is powered down, the configuration data within the stratix iv device is lost and must be loaded again on power up. hardcopy iv devices are mask-programmed and do not require configuration. one of the advantages of hardcopy iv devices is their instant-on capability upon power up. in addition, there are options to increase delay to postpone hardcopy iv devices power up. hardcopy iv power-up options hardcopy iv devices feature two power-up modes: instant on (no added delay) instant on after 50ms delay the intent of the power-up modes is to give customers the option of choosing between instant on and instant on after 50ms delay. instant on mode is the fastest power-up option on a hardcopy iv device. this mode is used when the hardcopy iv device powers up independently while other components on the board require initialization and configuration. therefore, you must verify all signals that propagate to and from the hardcopy iv device (for example, reference clocks and other input pins) are stable and do not interrupt hardcopy iv device operation. some customers use instant on after 50ms delay mode because the system might require the fpga and hardcopy iv devices to wait until a neighboring processor initializes completely. this mode holds the design in reset for 50ms prior to startup. in addition to the considerations of the system, the software expects the delay from the fpga device, which will now be replaced with the hardcopy device, and in these cases, customers choose this option. 1 you must choose the power-up option when submitting the design database to altera for hardcopy iv devices. after the hardcopy iv devices are manufactured, the power-up option cannot be changed. instant on mode is the traditional power-up scheme of most asic and non-volatile devices. similar to stratix iv devices, hardcopy iv devices go through four phases before transitioning to user mode. however, because hardcopy iv devices do not require configuration, the configuration phase is replaced by a delay phase with either no added delay or a 50 ms delay. hiv52004-2.0
4?2 chapter 4: matching stratix iv power and configuration requirements with hardcopy iv devices hardcopy iv power-up options hardcopy iv device handbook, volume 2 ? june 2009 altera corporation the four phases are listed in order: power-up phase initialization phase delay phase (replacing the configuration phase) start-up phase instant on (no added delay) in instant on mode, after the power supplies ramp up above the hardcopy iv device?s power-on reset (por) trip point, the device initiates an internal por sequence. after t por (as shown in figure 4?1 and figure 4?2 ), the power-up phase is complete and the hardcopy iv device transitions to an initialization phase, which releases the conf_done signal to be pulled high. pulling the conf_done signal high indicates that the hardcopy iv device is nearly ready for normal operation. for more information, refer to figure 4?1 . during the power-up sequence, weak internal pull-up resistors can pull the user i/o pins high. when the power-up and initialization phases are complete, the i/o pins are released. if the nio_pullup pin transitions high, the weak pull-up resistors are disabled. f you can find the value of the internal weak pull-up resistors on the i/o pins in the operating conditions table of the specific fpga?s device handbook. instant on after 50 ms delay the instant on after 50 ms delay mode is similar to instant on mode. however, the device waits an additional 50 ms during delay phase before releasing the conf_done pin. this delay is created by an on-chip oscillator. this option is beneficial if other devices on the board (such as a microprocessor) must be initialized prior to the normal operation of the hardcopy iv device. a start-up phase occurs immediately after the internal registers are reset, all plls used are initialized, and any i/o pins used are enabled as the device transitions into user mode. figure 4?1 shows an instant on power-up waveform in which the hardcopy iv device is powered up and the nconfig , nstatus , and conf_done pins are driven high externally.
chapter 4: matching stratix iv power and configuration requirements with hardcopy iv devices 4?3 hardcopy iv power-up options ? june 2009 altera corporation hardcopy iv device handbook, volume 2 figure 4?1. timing waveform for instant on option (note 1) , (2) , (3) , (4) , (5) notes to figure 4?1 : (1) v cc (all) represents either all the power pins or the last power pin powered up to specified operating conditions. (2) the nconfig , nstatus , and conf_done pins are weakly pulled high by an external 10 k ohm resistor to v ccpgm ; they must be high for this waveform to apply. (3) user i/o pins may be tri-stated or driven before and during power-up. the nio_pullup pin can affect the state of the user i/o pins during the initialization phase. (4) init_done is an optional pin that can be enabled on the fpga using the quartus ? ii software. hardcopy iv devices carry over the init_done functionality from the prototyped fpga design. (5) the nceo pin is asserted at approximately the same time as the conf_done pin is released. however, the nce pin must be driven low externally for this waveform to apply. v cc (all) nconfig nstatus conf_done user i/o init_done user mode high-z "don't care" "don't care" "don't care" "don't care" "don't care" t um t cd t add t por
4?4 chapter 4: matching stratix iv power and configuration requirements with hardcopy iv devices hardcopy iv power-up options hardcopy iv device handbook, volume 2 ? june 2009 altera corporation figure 4?2 shows an alternative to the power-up waveform shown in figure 4?1 . the nconfig pin is externally held low longer than the porsel delay. this delays the initialization sequence by a small amount. in addition, figure 4?2 shows an instant on power-up waveform where nconfig is momentarily held low and nstatus and conf_done are driven high externally. pulsing the nconfig signal on an fpga re-initializes the configuration sequence. this feature is the same for hardcopy asic devices; pulse the nconfig signal on a hardcopy asic device to restart the por sequence. figure 4?3 shows the instant-on behavior of the configuration signals and user i/o pins if the nconfig pin is pulsed while the v cc supplies are already powered up and stable. figure 4?2. timing waveform for instant on option where nconfig is held low after power-up notes to figure 4?2 : (1) this waveform applies if nconfig is held low longer than t por delay. (2) v cc (all) represents either all the power pins or the last power pin powered up to specified operating conditions. all hardcopy iv power pins must be powered within specifications. (3) the nconfig , nstatus , and conf_done pins are weakly pulled high by an external 10 k ohm resistor to v ccpgm ; they must be high for this waveform to apply. (4) user i/o pins may be tri-stated or driven before and during power-up. (5) init_done is an optional pin that can be enabled on the fpga using the quartus ii software. hardcopy iv devices carry over the init_done functionality from the prototype fpga design. (6) the nceo pin is asserted at approximately the same time as the conf_done pin is released. however, the nce pin must be driven low externally for this waveform to apply. pulsing the nconfig signal on an fpga re-initializes the configuration sequence. the nconfig signal on a hardcopy iv device also restarts the initialization sequence. v cc (all) nconfig nstatus conf_done user i/o init_done user mode high-z "don't care" "don't care" "don't care" "don't care" t um t cd t add t cf2st1 t por or longer
chapter 4: matching stratix iv power and configuration requirements with hardcopy iv devices 4?5 hardcopy iv power-up options ? june 2009 altera corporation hardcopy iv device handbook, volume 2 f for more information about hardcopy iv configuration specifications, refer to the hot socketing and power-on reset chapter in volume 1 of the hardcopy iv device handbook . figure 4?4 shows the instant-on behavior of the configuration signals and user i/o pins if the nconfig pin is pulsed while the v cc supplies are already powered up and stable. configuration pin compatibility when designing a board for both a stratix iv prototype device and its companion hardcopy iv device, most configuration pins required by the stratix iv device are not required by the hardcopy iv device. the programmable capabilities of these configuration pins in stratix iv devices cannot carry over to the hardcopy iv companion device because the hardcopy iv device is not programmable. to simplify the board connection for these configuration pins, altera recommends minimizing the power-up and configuration pins that do not carry over from the stratix iv device to the hardcopy iv device. table 4?1 lists the dedicated and optional configuration pins for stratix iv and hardcopy iv devices. if the hardcopy iv device uses the pins? optional function found in stratix iv devices, the quartus ii software allows you to set these pins as dual-purpose pins. as dual-purpose pins, they have i/o functionality after power up and initialization. these pins only switch to their i/o designation when the device enters user mode (when init_done is asserted). the design may require that some signals be present when the device transitions into user mode; therefore, it is important to consider the state of these pins after power up and after the device is in user mode when designing the board and selecting the state of dual-purpose pins. figure 4?3. timing waveform for the instant-on option when pulsing the nconfig signal (note 1) , (2) , (3) , (4) , (5) notes to figure 4?3 : (1) v cc (all) represents either all the power pins or the last power pin powered up to specified operating conditions. all hardcopy iv power pins must be powered within specifications as described in hot socketing sections. (2) the nstatus and conf_done pins must not be driven low externally for this waveform to apply. (3) the nio_pullup pin can affect the state of the user i/o pins during the initialization phase. (4) init_done is an optional pin that can be enabled on the fpga using the quartus ii software. hardcopy iv devices carry over the init_done functionality from the prototyped fpga design. (5) the nceo pin is asserted at approximately the same time as the conf_done pin is released. however, the nce pin must be driven low externally for this waveform to apply. v cc (all) nconfig nstatus conf_done user i/o init_done user mode high z "don't care" "don't care" t um t cd t add t cf2st1 t cf2st0
4?6 chapter 4: matching stratix iv power and configuration requirements with hardcopy iv devices hardcopy iv power-up options hardcopy iv device handbook, volume 2 ? june 2009 altera corporation f for more information about porsel settings for the fpga, refer to the configuration handbook . tab le 4 ?1 . configuration pin compatibility (note 1) , (2) , (3) stratix iv hardcopy iv pin name function board connection msel [2..0] dedicated no connect on board nconfig (5) dedicated required connection data [7..0] dual-purpose data[0] retains both user i/o and optional epcs access functions. data[7..1] retains user i/o functions only dclk dedicated no connect on board, except when epcs access is required in user mode init_done (6) dual-purpose (optional) retains the same i/o functions from the stratix iv device clkusr dual-purpose (optional) retains the same i/o functions from the stratix iv device nstatus (5) dedicated required connection conf_done (5) dedicated required connection nce dedicated required connection nceo dedicated required connection porsel (5) dedicated required connection asdo dedicated no connect on board, except when epcs access is required in user mode ncso dedicated no connect on board, except when epcs access is required in user mode nio_pullup dedicated required connection crc_error (4) dual-purpose (optional) retains the same i/o functions from the stratix iv device, but not crc_error because no device programming is needed. dev_clrn dual-purpose (optional) retains the same i/o functions from stratix iv dev_oe dual-purpose (optional) retains the same i/o functions from stratix iv notes to ta bl e 4? 1 : (1) for correct operation of the hardcopy iv device, pull the nstatus , nconfig , and conf_done pins to v ccpgm . in hardcopy iv devices, these pins are designed with weak internal resistors pulled up to v ccpgm . stratix iv configuration schemes require pull-up resistors on these i/o pins, so they may already be present on the board. you can remove these external pull-up resistors if doing so does not aff ect other fpgas on the board. (2) hardcopy iv devices have a maximum v ccio voltage of 3.0 v, but the input i/o pin can tolerate a 3.3-v level. this applies to v ccpgm voltage and all dedicated and dual-purpose pins. (3) for hardcopy iv devices, there is weak pull-up on the nstatus , conf_done , nconfig , and dclk pins. therefore, these pins can be left floating or remain connected to external pull-up resistors. if you use erasable programmable configurable serial (epcs) in user mode as a boot-up ram or da ta access for a nios ? ii processor, dclk , data[0] , asdo , and ncso need to be connected to the epcs device. (4) in hardcopy iv devices, crc_error is hard-wired to logic 0 if the crc feature is enabled in stratix iv devices. (5) the porsel pin setting delays the por sequence similar to the prototyping fpga. (6) the init_done settings option is mask-programmed into the device. you must submit these settings to altera with the final design prior to mapping to a hardcopy iv device. using the init_done option and other dual-purpose pins (for example, the dev_clrn device-wide reset and dev_oe device-wide output enable) are available in the fitter device options section of the quartus ii report file.
chapter 4: matching stratix iv power and configuration requirements with hardcopy iv devices 4?7 examples of mapping a stratix fpga configuration to a hardcopy asic ? june 2009 altera corporation hardcopy iv device handbook, volume 2 most optional configuration pins listed in table 4?1 on page 4?6 support the various configuration schemes available in stratix iv fpgas. parallel programming and remote update configuration modes use most of the pins in table 4?1 on page 4?6 . hardcopy iv devices are not configurable and do not support configuration emulation mode. therefore, altera recommends that you minimize using the optional functionality of the configuration pin in the stratix iv design by using another mode such as passive serial configuration mode. if some of these dual-purpose pins are needed to configure the stratix iv fpga, but will be unused after configuration, these pins remain unused on the hardcopy iv device. therefore, use caution when designing for these pins on the stratix iv and hardcopy iv boards. the removal of the stratix iv device and its corresponding configuration device may leave these pins floating on the hardcopy iv device if you assign them as inputs without any external means of driving them to a stable level. when selecting a stratix iv device and its device options, consider the after-configuration requirements of these pins and set them appropriately in the quartus ii software. examples of mapping a s tratix fpga configuration to a hardcopy asic this section provides examples of how hardcopy iv devices replace stratix iv fpgas using different configuration schemes. hardcopy iv device replacing a stand-alone stratix iv device figure 4?4 shows the stratix iv device before it is replaced with the hardcopy iv device. the example in figure 4?5 shows the single hardcopy iv device replacing a stand-alone stratix iv device. the configuration device, now redundant, is removed, and no further board changes are necessary. you can remove he pull-up resistors on the nconfig , nstatus , and conf_done pins. figure 4?4. configuration of a stand-alone stratix iv device stratix i v de v ice config u ration de v ice dclk data oe ncs ni n it_co n f msel dclk data0 nstatus co n f_do n e nco n fig v ccpgm v ccpgm g n d nce v ccpgm nceo ncasc n .c. n .c. n 10 k 10 k 10 k
4?8 chapter 4: matching stratix iv power and configuration requirements with hardcopy iv devices examples of mapping a stratix fpga configuration to a hardcopy asic hardcopy iv device handbook, volume 2 ? june 2009 altera corporation hardcopy iv device replacing a stratix iv device in a cascaded configuration chain figure 4?6 shows a design where the configuration data for the fpgas is stored in a single configuration device and the stratix iv devices are connected in a multiple-device configuration chain. the second device in the chain is replaced with a hardcopy iv device. figure 4?5. hardcopy iv device replacing a stand-alone stratix iv device hardcopy i v de v ice msel dclk data0 nstatus co n f_do n e nco n fig v ccpgm v cc g n d nce v ccpgm nceo n .c. n .c. n .c. n 10 k 10 k 10 k pgm figure 4?6. configuration of multiple fpgas in a cascade chain config u ration de v ice dclk data oe ncs ni n it_co n f dclk data0 nstatus co n f_do n e nco n fig v ccpgm v ccpgm g n d nce v ccpgm dclk data0 nstatus co n f_do n e nco n fig g n d nce msel2 msel1 nceo ncasc nceo msel0 v ccpgm g n d msel2 msel1 msel0 v ccpgm 10 k 10 k 10 k dclk data0 nstatus co n f_do n e nco n fig g n d nce msel2 msel1 nceo n .c. stratix i v de v ice 3 stratix i v de v ice 2 stratix i v de v ice 1 msel0 v ccpgm
chapter 4: matching stratix iv power and configuration requirements with hardcopy iv devices 4?9 examples of mapping a stratix fpga configuration to a hardcopy asic ? june 2009 altera corporation hardcopy iv device handbook, volume 2 to configure fpgas on a board with both hardcopy iv devices and fpgas, you must remove the hardcopy iv device from the cascade chain. figure 4?7 shows how the devices are connected with the hardcopy iv device removed from the chain. the data in the configuration device must be modified to exclude the hardcopy iv device configuration data. eliminating the hardcopy iv device from the configuration chain requires the following changes: the configuration data stored in the configuration device must be updated to exclude the configuration data for the hardcopy iv device. the nce pin of the hardcopy iv device must be tied to gnd. the nce pin of the fpga that was driven by the hardcopy iv nceo pin must now be driven by the nceo pin of the fpga that precedes the hardcopy iv device in the chain. the connections of the msel[2:0] pins are not required. figure 4?7. configuration with the hardcopy iv device removed from the cascade chain note to figure 4?7 : (1) the msel[2:0] pins are not used on the hardcopy iv device but they preserve the pin assignment and direction from the stratix iv device, allowing drop-in replacement. config u ration de v ice dclk data oe ncs ni n it_co n f dclk data0 nstatus co n f_do n e nco n fig v ccpgm v ccpgm g n d g n d nce v ccpgm dclk data0 nstatus co n f_do n e nco n fig g n d nce msel2 msel1 nceo ncasc nceo msel0 v ccpgm g n d msel2 msel1 msel0 v ccpgm 10 k 10 k 10 k dclk data0 nstatus co n f_do n e nco n fig g n d nce msel2 msel1 nceo n .c. n .c. stratix i v de v ice 2 hardcopy i v de v ice stratix i v de v ice 1 msel0 v ccpgm
4?10 chapter 4: matching stratix iv power and configuration requirements with hardcopy iv devices examples of mapping a stratix fpga configuration to a hardcopy asic hardcopy iv device handbook, volume 2 ? june 2009 altera corporation hardcopy iv device replacing a stratix iv device configured with a microprocessor when you replace a stratix iv fpga with a hardcopy iv device, the microprocessor code must be modified to treat the hardcopy iv device as a non-configurable device. figure 4?8 shows an example with two stratix iv devices configured using a microprocessor or max ? ii device and the fpp configuration scheme. this example does not require changes to the board. figure 4?8. multiple-device fpp configuration using a microprocessor or a max ii device note to figure 4?8 : (1) connect the pull-up resistor to a supply that provides an acceptable input signal for all devices in the chain. the v ccpgm voltage meets the i/o standard?s v ih specification on the device and the external host. co n f_do n e nstatus nce data[7..0] nco n fig stratix i v de v ice 1 memory addr data[7..0] g n d v ccpgm v ccpgm dclk nceo co n f_do n e nstatus nce data[7..0] nco n fig stratix i v de v ice 2 dclk nceo n .c. 10 k 10 k external host (max ii de v ice or microprocessor) msel[2..0] g n d msel[2..0] g n d
chapter 4: matching stratix iv power and configuration requirements with hardcopy iv devices 4?11 examples of mapping a stratix fpga configuration to a hardcopy asic ? june 2009 altera corporation hardcopy iv device handbook, volume 2 figure 4?9 shows how the first stratix iv device is replaced by a hardcopy iv device. in this case, the microprocessor code must be modified to send configuration data only to the second device (the stratix iv device) of the configuration chain. the microprocessor can only send this data after its nce pin is asserted by the first device (the hardcopy iv device). hardcopy iv device replacing an fpga configured in a jtag chain in this example, the circuit connectivity is maintained and there are no changes made to the board. you must modify the microprocessor code so that it treats the hardcopy iv device as a non-configurable device. the microprocessor can achieve this by issuing a bypass instruction to the hardcopy iv device. with the hardcopy iv device in bypass mode, the configuration data passes through it to the downstream fpgas. figure 4?10 shows an example where there are multiple fpgas. these devices are connected using the jtag i/o pins for each device and programmed using the jtag port. an on-board microprocessor generates the configuration data. figure 4?9. replacement of the first fpga in the fpp configuration chain with a hardcopy iv device (note 1) notes to figure 4?9 : (1) connect the pull-up resistor to a supply that provides an acceptable input signal for all devices in the chain. the v ccpgm voltage meets the i/o standard?s v ih specification on the device and the external host. (2) the data[7..0] and msel[2:0] pins are not used on the hardcopy iv device but they preserve the pin assignment and direction from the stratix iv device, allowing drop-in replacement. co n f_do n e nstatus nce data[7..0] (2) nco n fig hardcopy i v de v ice memory addr data[7..0] g n d v ccpgm (1) v ccpgm (1) dclk nceo co n f_do n e nstatus nce data[7..0] nco n fig stratix i v de v ice dclk nceo n .c. 10 k 10 k external host (max ii de v ice or microprocessor) msel[2..0] g n d msel[2..0] g n d (2) g n d n .c.
4?12 chapter 4: matching stratix iv power and configuration requirements with hardcopy iv devices examples of mapping a stratix fpga configuration to a hardcopy asic hardcopy iv device handbook, volume 2 ? june 2009 altera corporation figure 4?11 shows an example where the first stratix iv device in the jtag chain is replaced by a hardcopy iv device. figure 4?10. configuring fpgas in a jtag chain using a microprocessor notes to figure 4?10 : (1) you can place the stratix iv, stratix iii, stratix ii, stratix, cyclone ? iii, cyclone ii, and cyclone devices within the same jtag chain for device programming and configuration. (2) connect the nconfig , msel0 , msel1 , and msel2 pins to support a non-jtag configuration scheme. if you only use jtag configuration, connect nconfig to v ccpgm , and msel0 , msel1 , and msel2 to gnd. pull data0 and dclk to either high or low. (3) nce must be connected to gnd or driven low for successful jtag configuration. tms tck tdi tdo nstatus nco n fig msel2 msel1 nce v ccpgm co n f_do n e v ccpgm tms tck tdi tdo nco n fig msel2 msel1 nce v ccpgm co n f_do n e v ccpgm tms tck tdi tdo nco n fig msel2 msel1 nce v ccpgm co n f_do n e v ccpgm (2) (2) (2) msel0 (2) (2) (2) (2) msel0 (2) (2) dclk dclk dclk (2) (2) (2) data 0 data 0 data 0 (2) (2) (2) (2) (2) msel0 (2) stratix i v de v ice stratix i v de v ice stratix i v de v ice nstatus nstatus 10 k 10 k 10 k 10 k 10 k 10 k (3) (3) (3) memory addr data microprocessor figure 4?11. replacement of the first fpga in the jtag chain with a hardcopy iv device (note 1) notes to figure 4?11 : (1) you can place the stratix iv, stratix iii, stratix ii, stratix, cyclone iii, cyclone ii, and cyclone devices within the same jtag chain for device programming configuration. (2) connect the nconfig , msel0 , msel1 , and msel2 pins to support a non-jtag configuration scheme. if you use only jtag configuration, connect nconfig to v ccpgm , and msel0 , msel1 , and msel2 to gnd. pull data0 and dclk to either high or low. (3) nce must be connected to gnd or driven low for successful jtag configuration. tms tck tdi tdo nstatus nco n fig msel2 msel1 nce v cc co n f_do n e v ccpgm tms tck tdi tdo nco n fig msel2 msel1 nce v ccpgm co n f_do n e v ccpgm tms tck tdi tdo nco n fig msel2 msel1 nce v ccpgm co n f_do n e v ccpgm (2) (2) (2) msel0 (2) (2) msel0 (2) dclk dclk dclk (2) (2) data 0 data 0 data 0 (2) n c (2) (2) (2) msel0 (2) hardcopy i v de v ice stratix i v de v ice stratix i v de v ice nstatus nstatus 10 k 10 k 10 k 10 k 10 k 10 k (3) (3) (3) memory addr data microprocessor n c n c n c n c pgm
chapter 4: matching stratix iv power and configuration requirements with hardcopy iv devices 4?13 document revision history ? june 2009 altera corporation hardcopy iv device handbook, volume 2 document revision history table 4?2 shows the revision history for this chapter. tab le 4 ?2 . document revision history june 2009 2.0 updated for hardcopy iv gx devices. december 2008 1.0 initial release.
4?14 chapter 4: matching stratix iv power and configuration requirements with hardcopy iv devices document revision history hardcopy iv device handbook, volume 2 ? june 2009 altera corporation
? january 2010 altera corporation hardcopy iv device handbook, volume 2 additional information about this handbook this handbook provides comprehensive information about the altera ? hardcopy ? iv family of devices. how to contact altera for the most up-to-date information about altera products, see the following table. typographic conventions the following table shows the typographic conventions that this document uses. contact (note 1) contact method address technical support website www.altera.com/support technical training website www.altera.com/training email custrain@altera.com product literature website www.altera.com/literature non-technical support (general) email nacomp@altera.com (software licensing) email authorization@altera.com note: (1) you can also contact your local altera sales office or sales representative. visual cue meaning bold type with initial capital letters indicates command names, dialog box titles, dialog box options, and other gui labels. for example, save as dialog box. for gui elements, capitalization matches the gui. bold type indicates directory names, project names, disk drive names, file names, file name extensions, dialog box options, software utility names, and other gui labels. for example, \qdesigns directory, d: drive, and chiptrip.gdf file. italic type with initial capital letters indicates document titles. for example, an 519: stratix iv design guidelines. italic type indicates variables. for example, n + 1. variable names are enclosed in angle brackets (< >). for example, and .pof file. initial capital letters indicates keyboard keys and menu names. for example, delete key and the options menu. ?subheading title? quotation marks indicate references to sections within a document and titles of quartus ii help topics. for example, ?typographic conventions.?
info?2 additional information hardcopy iv device handbook, volume 2 ? january 2010 altera corporation courier type indicates signal, port, register, bit, block, and primitive names. for example, data1 , tdi , and input . active-low signals are denoted by suffix n . for example, resetn . indicates command line commands and anything that must be typed exactly as it appears. for example, c:\qdesigns\tutorial\chiptrip.gdf . also indicates sections of an actual file, such as a report file, references to parts of files (for example, the ahdl keyword subdesign ), and logic function names (for example, tri ). 1., 2., 3., and a., b., c., and so on. numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. bullets indicate a list of items when the sequence of the items is not important. 1 the hand points to information that requires special attention. c a caution calls attention to a condition or possible situation that can damage or destroy the product or your work. w a warning calls attention to a condition or possible situation that can cause you injury. r the angled arrow instructs you to press enter . f the feet direct you to more information about a particular topic. visual cue meaning
101 innovation drive san jose, ca 95134 www.altera.com hardcopy iv device handbook, volume 3 hc4_h5v3-1.0
copyright ? 2009 altera corporation. all rights reserved. altera, the programmable solutions company, the stylized altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of altera corporation in the u.s. and other countries. all other product or service names are the property of their respective holders. altera products are protected under numerous u.s. and foreign patents and pending ap- plications, maskwork rights, and copyrights. altera warrants performance of its semiconductor products to current specification s in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibilit y or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera corporation. altera cu stomers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services .
? june 2009 altera corporation hardcopy iv device handbook, volume 3 contents chapter revision dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi section i. transceiver architecture revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i-1 chapter 1. hardcopy iv gx transceiver architecture introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 transceiver channel locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 transceiver block architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 transceiver port list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 cmu channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 configuring cmu channels for clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -22 cmu0 channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24 cmu1 channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 power down cmu1 pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 configuring cmu channels as transceiver channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 serializer and deserializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 cmu clock divider block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 clocks for the transmitter serializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 input reference clocks for the receiver cdr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 clocks for the receiver deserializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 other cmu channel features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 dynamic reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 auxiliary transmit (atx) pll block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32 input reference clocks for the atx pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33 architecture of the atx pll block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33 transceiver channel architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34
iv contents hardcopy iv device handbook, volume 3 ? june 2009 altera corporation transmitter channel datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36 tx phase compensation fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37 input data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38 output data destination block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38 tx phase compensation fifo status signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38 byte serializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38 single-width mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39 double-width mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40 8b/10b encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40 single-width mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41 double-width mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43 controlling running disparity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45 transmitter polarity inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-47 transmitter bit reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-49 serializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51 transmitter output buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 programmable transmitter termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-53 programmable output differential voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-53 programmable pre-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54 programmable transmitter output buffer power (vcch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55 common mode voltage (vcm) settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55 link coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55 pci express (pipe) receiver detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-56 pci express (pipe) electrical idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57 transmitter local clock divider block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57
contents v ? june 2009 altera corporation hardcopy iv device handbook, volume 3 receiver channel datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-58 receiver input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-59 programmable differential on-chip termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-60 programmable common mode voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -60 link coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-60 programmable equalization and dc gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-66 signal threshold detection circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-67 clock and data recovery unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-67 lock-to-reference mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-68 lock-to-data mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-70 pci express (pipe) clock switch circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-70 ltr/ltd controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-71 deserializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-72 word aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-73 word aligner in single-width mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-74 word aligner in double-width mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-80 programmable run length violation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 5 receiver polarity inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-86 receiver bit reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-88 receiver byte reversal in basic double-width modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-90 deskew fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-91 rate match (clock rate compensation) fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-93 rate match fifo in pci express (pipe) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -94 rate match fifo in xaui mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-96 rate match fifo in gige mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-98 rate match fifo in basic single-width mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -99 rate match fifo in basic double-width mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-101 8b/10b decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-104 8b/10b decoder in single-width mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-105 8b/10b decoder in double-width mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -107 byte deserializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-108 byte deserializer in single-width mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-109 byte deserializer in double-width mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-109 byte ordering block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-110 byte ordering block in single-width modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 111 byte ordering block in double-width modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 2 word-alignment-based byte ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-113 user-controlled byte ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-114 receiver phase compensation fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-115 receiver phase compensation fifo error flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 6 offset cancellation in the receiver buffer and receiver cdr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-116
vi contents hardcopy iv device handbook, volume 3 ? june 2009 altera corporation functional modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-118 basic functional mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-118 low latency pcs datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-119 basic single-width mode configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-120 basic double-width mode configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -122 deterministic latency options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-123 rx bit slipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-124 receiver phase comp fifo in register mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-125 transmitter bit slipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-125 pci express (pipe) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-125 pci express (pipe) mode configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-126 pci express (pipe) mode datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-128 pci express (pipe) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-130 fast recovery mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-135 electrical idle inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-136 pci express (pipe) gen2 (5 gbps) support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -137 pci express (pipe) cold reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-148 xaui mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-149 xaui mode datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-154 xgmii-to-pcs code conversion at the transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-155 pcs-to-xgmii code conversion at the receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-156 word aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-157 deskew fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-158 rate match fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-160 gige mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-161 gige mode datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-164 8b/10b encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-164 word aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-166 rate match fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-167 sonet/sdh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-168 sonet/sdh frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-168 sonet/sdh oc-12 datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-171 sonet/sdh oc-48 datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-171 sonet/sdh oc-96 datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-172 sonet/sdh transmission bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-172 word alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-172 oc-48 and oc-96 byte serializer and deserializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-173 oc-48 byte ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-173 sdi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-174 sdi mode datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-176 (oif) cei phy interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-177 (oif) cei phy interface mode datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-178 (oif) cei phy interface mode clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-178 serial rapidio mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-180 synchronization state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-181 basic (pma-direct) functional mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-183 basic pma-direct x1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-184 basic pma-direct xn configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-184 built-in self test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-185 bist mode pattern generators and verifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -185 prbs in single-width mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-186 prbs in double-width mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-187
contents vii ? june 2009 altera corporation hardcopy iv device handbook, volume 3 loopback modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-188 serial loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-188 parallel loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-189 reverse serial loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-190 reverse serial pre-cdr loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-190 pci express (pipe) reverse parallel loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-191 calibration blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-192 calibration block location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-192 calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-193 input signals to the calibration block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-194 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-194 chapter 2. hardcopy iv gx dynamic reconfiguration introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 conventions used in this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 dynamic reconfiguration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 offset cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 pma controls reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 transceiver channel reconfiguration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 regular transceiver channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration . . . . . . . . 2-5 altgx megawizard plug-in manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 altgx_reconfig megawizard plug-in manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 dynamic reconfiguration controller architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 dynamic reconfiguration controller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 dynamic reconfiguration controller port list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 clock requirements for the altgx instance and altgx_reconfig instance . . . . . . . . . . . . . . 2-20 clock requirements for the altgx instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -20 clock requirements for the altgx_reconfig instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 interfacing altgx_reconfig and altgx instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 logical channel addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 total number of channels controlled by the altgx_reconfig instance . . . . . . . . . . . . . . . 2-35 connecting the reconfig_fromgxb and reconfig_togxb ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40 connecting reconfig_fromgxb for regular transceiver channels . . . . . . . . . . . . . . . . . . . . . . . . . 2-41 connecting reconfig_fromgxb for the pma-only channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42 offset cancellation control for receiver channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44 example for the offset cancellation process of a receiver channel . . . . . . . . . . . . . . . . . . . . . . . 2-48 the rx_tx_duplex_sel[1:0] port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 the logical_channel_address port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 pma controls reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52 cmu channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52 dynamic reconfiguration controller ports for pma controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53 dynamically reconfiguring pma controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53 method 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54 method 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-56
viii contents hardcopy iv device handbook, volume 3 ? june 2009 altera corporation description of transceiver channel reconfiguration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2- 62 data rate division in tx mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63 blocks reconfigured in the data rate division in tx mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-64 altgx megawizard plug-in manager setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-64 altgx_reconfig megawizard plug-in manager setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65 data rate division in tx: operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66 channel and tx pll select/reconfig modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-68 .mif generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69 the logical_channel_address port in .mif-based dynamic reconfiguration modes . . . . . . . . . . 2-73 channel and cmu pll reconfiguration mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-74 channel reconfiguration with tx pll select mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-102 cmu pll reconfiguration mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-106 the logical_tx_pll_sel and logical_tx_pll_sel_en ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-109 general guidelines for specifying the input reference clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 2-115 design examples: dynamic reconfiguration controller (altgx_reconfig) . . . . . . . . . . . . . . . . 2-120 example 1: one reconfiguration controller connected to multiple altgx instances . . . . . . . . 2-120 altgx instances and altgx_reconfig instances connections . . . . . . . . . . . . . . . . . . . . . . 2-122 dynamically reconfiguring the tx_vodctrl and rx_eqctrl pma controls using method 1 . . . 2-123 example 2: two altgx_reconfig instances connected to two altgx instances . . . . . . . . 2-123 altgx instances and altgx_reconfig instances connections . . . . . . . . . . . . . . . . . . . . . . 2-125 dynamically reconfiguring the tx_vodctrl pma control of altgx instance 1 from altgx_reconfig instance 1 using method 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-125 dynamically reconfiguring the rx_eqctrl pma control of altgx instance 2 from altgx_reconfig instance 2 using method 1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-125 example 3: one altgx_reconfig instance connected to an altgx instance stamped five times . . . . 2-125 altgx instance with one transceiver channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-125 dynamic reconfiguration controller instance (altgx_reconfig instance) . . . . . . . . . . . . 2-126 altgx instances and altgx_reconfig instance connections . . . . . . . . . . . . . . . . . . . . . . . 2-126 dynamically reconfiguring the tx_vodctrl of instance 1 using method 2 . . . . . . . . . . . . . . . . . 2-126 example 4: data rate division in tx mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-127 example 5: cmu pll reconfiguration mode with altgx instances in transmitter only configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-129 example 6: dynamically reconfiguring a transceiver channel between a gige configuration and a sonet/sdh oc48 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-131 section i?configure the altgx instance to generate the .mif . . . . . . . . . . . . . . . . . . . . . . . . . 2-133 section ii?control the logic for the dynamic reconfiguration controller . . . . . . . . . . . . . . . 2-137 section iii?logic and clocking for the gige and sonet/sdh oc48 datapath . . . . . . . . . . 2-138 section iv?reset control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-139 simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-139 error indication in the altgx_reconfig megawizard plug-in manager . . . . . . . . . . . . . . . . . . . 2-139 combining transceiver channels with dynamic reconfiguration enabled . . . . . . . . . . . . . . . . . . . . 2-140 requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-141 combining a transmitter only instance and receiver only instance . . . . . . . . . . . . . . . . . . . . 2-141 merging transceiver channels with channel and cmu pll reconfiguration mode enabled into the same transceiver block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-141 merging transceiver channels listening to two transmitter plls . . . . . . . . . . . . . . . . . . . . . . 2-142 merging transceiver channels listening to one transmitter pll . . . . . . . . . . . . . . . . . . . . . . . 2-143 dynamic reconfiguration duration and core fabric resource utilization . . . . . . . . . . . . . . . . . . . . . 2-143 dynamic reconfiguration duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-143 pma controls reconfiguration duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-143 offset cancellation duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-145 dynamic reconfiguration duration for channel and tx pll select/reconfig modes . . . . . . 2-145 dynamic reconfiguration (altgx_reconfig instance) resource utilization . . . . . . . . . . . . . 2-146
contents ix ? june 2009 altera corporation hardcopy iv device handbook, volume 3 functional simulation of the offset cancellation process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-147 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-147 chapter 3. hardcopy iv gx altgx_re config m egafunction user guide introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 dynamic reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 additional information about this handbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info-1 how to contact altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info-1 typographic conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info-1
x contents hardcopy iv device handbook, volume 3 ? june 2009 altera corporation
? june 2009 altera corporation hardcopy iv device handbook, volume 3 chapter revision dates the chapters in this book, hardcopy iv device handbook, volume 3 , were revised on the following dates. where chapters or groups of chapters are available separately, part numbers are listed. chapter 1 hardcopy iv gx transceiver architecture revised: june 2009 part number: hiv53001-1.0 chapter 2 hardcopy iv gx dynamic reconfiguration revised: june 2009 part number: hiv53002-1.0 chapter 3 hardcopy iv gx altgx_reconfig megafunction user guide revised: june 2009 part number: hiv53003-1.0
xii chapter revision dates hardcopy iv device handbook, volume 3 ? june 2009 altera corporation
? june 2009 altera corporation hardcopy iv device handbook, volume 3 section i. transceiver architecture this section provides a description of transceiver architecture and dynamic reconfiguration for the hardcopy ? iv device family. this section includes the following chapters: revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook.
i?2 section i: transceiver architecture hardcopy iv device handbook, volume 3 ? june 2009 altera corporation
? june 2009 altera corporation hardcopy iv device handbook volume 3 1. hardcopy iv gx transceiver architecture introduction this chapter provides details about hardcopy ? iv transceiver architecture, transceiver channels, available modes, and a description of transmitter and receiver channel datapaths. hardcopy iv gx devices deliver a very high level of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise. hardcopy iv gx devices provide up to 24 full-duplex cdr-based transceivers with physical coding sublayer (pcs) and physical medium attachment (pma), at serial data rates between 600 mbps and 6.5 gbps. up to 12 additional full-duplex cdr-based transceivers with pma, supporting serial data rates between 600 mbps and 6.5 gbps, are also provided. the transceiver channels are designed to support the following serial protocols: f r vc v r r c r r fr r r c rfr r r 11
1?2 chapter 1: hardcopy iv gx transceiver architecture transceiver channel locations hardcopy iv device handbook volume 3 ? june 2009 altera corporation this chapter includes the following sections: transceiver channel locations the hardcopy iv gx transceivers are structured into full-duplex (transmitter and receiver) four-channel groups called transceiver blocks. the total number of transceiver channels and the location of transceiver blocks varies from device to device. table 1?1 summarizes the total number of transceiver channels and transceiver block locations in each hardcopy iv gx device member. tab le 1 ?1 . number of transceiver channels and transceiver block locations in hardcopy iv gx devices (part 1 of 2) device member tot al n umbe r of transceiver channels transceiver channel location HC4GX15lf780n 8 eight transceiver channels located in two transceiver blocks, gxbr0 and gxbr1 , on the right side of the device. hc4gx25lf1152n hc4gx25lf780n 16 eight transceiver channels located in two transceiver blocks, gxbr0 and gxbr1 , on the right side of the device. eight transceiver channels located in two transceiver blocks, gxbl0 and gxbl1 , on the left side of the device. hc4gx25ff1152n hc4gx35ff1152n 24 eight regular transceiver channels supporting data rates between 600 mbps and 6.5 gbps and four cmu channels supporting data rates between 600 mbps and 6.5 gbps located in two transceiver blocks, gxbr0 and gxbr1 , on the right side of the device. eight regular transceiver channels supporting data rates between 600 mbps and 6.5 gbps and four cmu channels supporting data rates between 600 mbps and 6.5 gbps located in two transceiver blocks, gxbl0 and gxbl1 , on the left side of the device.
chapter 1: hardcopy iv gx transceiver architecture 1?3 transceiver channel locations ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?1 through figure 1?5 show transceiver channel locations in each hardcopy iv gx device member. hc4gx35lf1517n 24 twelve regular transceiver channels located in three transceiver blocks, gxbr0 , gxbr1 , and gxbr2 on the right side of the device. twelve regular transceiver channels located in three transceiver blocks, gxbl0 , gxbl1 , and gxbl2 on the left side of the device. hc4gx35ff1517n 36 twelve regular transceiver channels supporting data rates between 600 mbps and 6.5 gbps and six cmu channels supporting data rates between 600 mbps and 6.5 gbps located in three transceiver blocks, gxbr0 , gxbr1 , and gxbr2 on the right side of the device. twelve regular transceiver channels supporting data rates between 600 mbps and 6.5 gbps and six cmu channels supporting data rates between 600 mbps and 6.5 gbps located in three transceiver blocks, gxbl0 , gxbl1 , and gxbl2 on the left side of the device. tab le 1 ?1 . number of transceiver channels and transceiver block locations in hardcopy iv gx devices (part 2 of 2) device member tot al n umbe r of transceiver channels transceiver channel location figure 1?1. hardcopy iv gx devices with eight transceiver channels HC4GX15lf780n transceiver block gxbr1 transceiver block gxbr0 channel 3 channel 2 channel 1 channel 0 channel 3 channel 2 channel 1 channel 0
1?4 chapter 1: hardcopy iv gx transceiver architecture transceiver channel locations hardcopy iv device handbook volume 3 ? june 2009 altera corporation figure 1?2. hardcopy iv gx devices with sixteen transceiver channels figure 1?3. hardcopy iv gx devices with twenty-four transceiver channels hc4gx25lf1152n, hc4gx25lf780n transceiver block gxbl1 channel 3 channel 2 channel 1 channel 0 transceiver block gxbl0 transceiver block gxbr1 transceiver block gxbr0 channel 3 channel 2 channel 1 channel 0 channel 3 channel 2 channel 1 channel 0 channel 3 channel 2 channel 1 channel 0 hc4gx25ff1152n, hc4gx35ff1152n transcei v er block gxbl1 transcei v er block gxbr1 channel 3 channel 2 cmu channel 1 cmu channel 0 channel 1 channel 0 channel 3 channel 2 cmu channel 1 cmu channel 0 channel 1 channel 0 transcei v er block gxbl0 channel 3 channel 2 cmu channel 1 cmu channel 0 channel 1 channel 0 channel 3 channel 2 cmu channel 1 cmu channel 0 channel 1 channel 0 transcei v er block gxbr0
chapter 1: hardcopy iv gx transceiver architecture 1?5 transceiver channel locations ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?4. hardcopy iv gx devices with twenty-four transceiver channels transcei v er block gxbl2 transcei v er block gxbr2 channel 3 channel 2 channel 1 channel 0 channel 3 channel 2 channel 1 channel 0 transcei v er block gxbl1 channel 3 channel 2 channel 1 channel 0 channel 3 channel 2 channel 1 channel 0 transcei v er block gxbr1 transcei v er block gxbl0 channel 3 channel 2 channel 1 channel 0 channel 3 channel 2 channel 1 channel 0 transcei v er block gxbr0 hc4gx35lf1517n
1?6 chapter 1: hardcopy iv gx transceiver architecture transceiver block architecture hardcopy iv device handbook volume 3 ? june 2009 altera corporation transceiver block architecture each transceiver block has the following components: cmu0 and cmu1 channels?that provide the high-speed serial and low-speed parallel clock to the transceiver channels figure 1?5. hardcopy iv gx devices with thirty-six transceiver channels transcei v er block gxbl2 transcei v er block gxbr2 channel 3 channel 2 cmu channel 1 cmu channel 0 channel 1 channel 0 channel 3 channel 2 cmu channel 1 cmu channel 0 channel 1 channel 0 transcei v er block gxbl1 channel 3 channel 2 cmu channel 1 cmu channel 0 channel 1 channel 0 channel 3 channel 2 cmu channel 1 cmu channel 0 channel 1 channel 0 transcei v er block gxbr1 transcei v er block gxbl0 channel 3 channel 2 cmu channel 1 cmu channel 0 channel 1 channel 0 channel 3 channel 2 cmu channel 1 cmu channel 0 channel 1 channel 0 transcei v er block gxbr0 hc4gx35ff1517n
chapter 1: hardcopy iv gx transceiver architecture 1?7 transceiver port list ? june 2009 altera corporation hardcopy iv device handbook volume 3  central control unit (ccu) that implements xaui state machine for xgmii-to-pcs code group conversion, xaui deskew state machine, shared control signal generation block, pci express (pipe) rateswitch controller block, and reset control logic  the shared control signal generation block provides control signals to the transceiver channels in bonded functional modes such as xaui, pipe, and basic 4.  the pipe rateswitch controller block controls the rateswitch circuit in the cmu0 channel, in 4 configurations. in pipe 8 configuration, the pipe rateswitch controller block of the ccu in the master transceiver block is active. for more information about rateswitch in pipe, refer to ?pci express (pipe) gen2 (5 gbps) support? on page 1?137 . figure 1?6 shows a block diagram of the transceiver block architecture. 1 for architecture information about cmu channels and transceiver channels, refer to ?cmu channels? on page 1?22 and ?transceiver channel architecture? on page 1?34 . transceiver port list instantiate the hardcopy iv gx transceivers using the altgx megafunction instance in the quartus ? ii megawizard ? plug-in manager. the altgx megafunction instance allows you to configure transceivers for your intended protocol and select optional control and status ports to and from the instantiated transceiver channels. figure 1?6. top-level view of a transceiver block transceiver block gxbl1 transceiver channel 3 transceiver channel 2 transceiver channel 1 transceiver channel 0 transceiver block transceiver block gxbl0 transceiver block gxbr1 transceiver block gxbr0 channel 3 channel 2 channel 1 channel 0 channel 3 channel 2 channel 1 channel 0 channel 3 channel 2 channel 1 channel 0 channel 3 channel 2 channel 1 channel 0 cmu1 channel cmu0 channel central control unit (ccu)
1?8 chapter 1: hardcopy iv gx transceiver architecture transceiver port list hardcopy iv device handbook volume 3 ? june 2009 altera corporation table 1?2 provides a brief description of the altgx megafunction ports. tab le 1 ?2 . hardcopy iv gx altgx megafunction ports (part 1 of 14) port name input/output description scope clock multiplier unit (cmu) pll_inclk input input reference clock for the cmu phase-locked loop (pll). transceiver block pll_locked output cmu pll lock indicator. a high level indicates that the cmu pll is locked to the input reference clock; a low level indicates that the cmu pll is not locked to the input reference clock. asynchronous signal. transceiver block pll_powerdown input cmu pll power down. when asserted high, the cmu pll is powered down. when de-asserted low, the cmu pll is active and locks to the input reference clock. note: asserting the pll_powerdown signal does not power down the refclk buffers. asynchronous signal. the minimum pulse-width is 1 s (pending characterization). transceiver block coreclkout output core fabric-transceiver interface clock. generated by the cmu0 clock divider in the transceiver block in 4 bonded channel configurations. generated by the cmu0 clock divider in the master transceiver block in 8 bonded channel configurations. not available in non-bonded channel configurations. this clock is used to clock the write port of the transmitter phase compensation fifos in all bonded channels. use this clock signal to clock parallel data tx_datain from the core fabric into the transmitter phase compensation fifo of all bonded channels. this clock is used to clock the read port of the receiver phase compensation fifos in all bonded channels with rate match fifo enabled. use this signal to clock parallel data rx_dataout from the receiver phase compensation fifos of all bonded channels (with rate match fifo enabled) into the core fabric. transceiver block
chapter 1: hardcopy iv gx transceiver architecture 1?9 transceiver port list ? june 2009 altera corporation hardcopy iv device handbook volume 3 receiver physical coding sublayer (pcs) ports word aligner rx_enapatternalign input manual word alignment enable control. enables the word aligner configured in manual alignment mode to align to the word alignment pattern. in single-width modes with 10-bit pma-pcs interface, this signal is level-sensitive. when high, the word aligner re-aligns if the word alignment pattern appears in a new word boundary. in single-width modes with 8-bit pma-pcs interface and all double-width modes, a low-to-high transition causes the word aligner to re-align once, if the word alignment pattern appears in a new word boundary. asynchronous signal. the minimum pulse-width is two recovered clock cycles. channel rx_patterndetect output word alignment pattern detect indicator. a high level indicates that the word alignment pattern is found on the current word boundary. the width of this signal depends on the following channel width: channel width rx_patterndetect 8/10 1 16/20 2 32/40 4 channel tab le 1 ?2 . hardcopy iv gx altgx megafunction ports (part 2 of 14) port name input/output description scope
1?10 chapter 1: hardcopy iv gx transceiver architecture transceiver port list hardcopy iv device handbook volume 3 ? june 2009 altera corporation rx_syncstatus output word alignment synchronization status indicator. for the word aligner in automatic synchronization state machine mode, this signal is driven high if the conditions required to remain in synchronization are met. it is driven low if the conditions required to lose synchronization are met. for the word aligner in manual alignment mode, the behavior of this signal depends on whether the transceiver is configured in single-width or double-width mode. for more information, refer to ?word aligner in single-width mode? on page 1?74 and ?word aligner in double-width mode? on page 1?80 . this signal is not available for the word aligner in bit-slip mode. the width of this signal depends on the following channel width: channel width rx_syncstatus 8/10 1 16/20 2 32/40 4 channel rx_bitslip input bit-slip control for the word aligner configured in bit-slip mode. at every rising edge of this signal, word aligner slips one bit into the received data stream, effectively shifting the word boundary by 1 bit. asynchronous signal. the minimum pulse-width is two recovered clock cycles. channel rx_ala2size input available only in sonet oc-12 and oc-48 modes to select between one of the following two word alignment options: 0 -16-bit a1a2 1 - 32-bit a1a1a2a2 channel rx_rlv output run-length violation indicator. a high pulse is driven when the number of consecutive 1s or 0?s in the received data stream exceeds the programmed run length violation threshold. asynchronous signal. driven for a minimum of two recovered clock cycles in configurations without byte serializer and a minimum of three recovered clock cycles in configurations with byte serializer. channel tab le 1 ?2 . hardcopy iv gx altgx megafunction ports (part 3 of 14) port name input/output description scope
chapter 1: hardcopy iv gx transceiver architecture 1?11 transceiver port list ? june 2009 altera corporation hardcopy iv device handbook volume 3 rx_invpolarity input generic receiver polarity inversion control. useful feature for correcting situations where the positive and negative signals of the differential serial link are accidentally swapped during board layout. when asserted high in single-width modes, the polarity of every bit of the 8-bit or 10-bit input data word to the word aligner gets inverted. when asserted high in double-width mode, the polarity of every bit of the 16-bit or 20-bit input data to the word aligner gets inverted. asynchronous signal. channel rx_revbitorderwa input receiver bit reversal control. this is available only in basic single-width and double-width modes with the word aligner configured in bit-slip mode. this is a useful feature where the link transmission order is msbit to lsbit. when asserted high in basic single-width modes, the 8-bit or 10-bit data d[7:0] or d[9:0] at the output of the word aligner gets rewired to d[0:7] or d[0:9] , respectively. when asserted high in basic double-width modes, the 16-bit or 20-bit data d[15:0] or d[19:0] at the output of the word aligner gets rewired to d[0:15] or d[0:19] , respectively. asynchronous signal. channel rx_revbyteorderwa input receiver byte reversal control. this is available only in basic double-width mode. this is a useful feature in situations where the msbyte and lsbyte of the transmitted data are erroneously swapped. when asserted high, the msbyte and lsbyte of the 16 and 20 bit data at the output of the word aligner get swapped. asynchronous signal. channel tab le 1 ?2 . hardcopy iv gx altgx megafunction ports (part 4 of 14) port name input/output description scope
1?12 chapter 1: hardcopy iv gx transceiver architecture transceiver port list hardcopy iv device handbook volume 3 ? june 2009 altera corporation deskew fifo rx_channelaligned output ten-gigabit attachment unit interface (xaui) deskew fifo channel aligned indicator. available only in xaui mode. a high level indicates that the xaui deskew state machine is either in align_acquired_1 , align_acquired_2 , align_acquired_3 , or align_acquired_4 state, as specified in the pcs deskew state diagram in the ieee p802.3ae specification. a low level indicates that the xaui deskew state machine is either in loss_of_alignment , align_detect_1 , align_detect_2 , or align_detect_3 state, as specified in the pcs deskew state diagram in the ieee p802.3ae specification. transceiver block rate match (clock rate compensation) fifo rx_rmfifodatainserted output rate match fifo insertion status indicator. a high level indicates that the rate match pattern byte has inserted to compensate for the parts-per-million (ppm) difference in reference clock frequencies between the upstream transmitter and the local receiver. channel rx_rmfifodatadeleted output rate match fifo deletion status indicator. a high level indicates that the rate match pattern byte got deleted to compensate for the ppm difference in reference clock frequencies between the upstream transmitter and the local receiver. channel rx_rmfifofull output rate match fifo full status indicator. a high level indicates that the rate match fifo is full. driven for a minimum of two recovered clock cycles in configurations without byte serializer and a minimum of three recovered clock cycles in configurations with byte serializer. channel rx_rmfifoempty output rate match fifo empty status indicator. a high level indicates that the rate match fifo is empty. driven for a minimum of two recovered clock cycles in configurations without byte serializer and a minimum of three recovered clock cycles in configurations with byte serializer. channel tab le 1 ?2 . hardcopy iv gx altgx megafunction ports (part 5 of 14) port name input/output description scope
chapter 1: hardcopy iv gx transceiver architecture 1?13 transceiver port list ? june 2009 altera corporation hardcopy iv device handbook volume 3 8b/10b decoder rx_ctrldetect output receiver control code indicator. available in configurations with 8b/10b decoder. a high level indicates that the associated received code group is a control (/kx.y/) code group. a low level indicates that the associated received code group is a data (/dx.y/) code group. the width of this signal depends on the following channel width: channel width rx_ctrldetect 8 1 16 2 32 4 channel rx_errdetect output 8b/10b code group violation or disparity error indicator. available in configurations with 8b/10b decoder. a high level indicates that a code group violation or disparity error was detected on the associated received code group. use with the rx_disperr signal to differentiate between a code group violation and/or a disparity error as follows: [rx_errdetect: rx_disperr ] 2?b00?no error 2?b10?code group violation 2?b11?disparity error or both the width of this signal depends on the following channel width: channel width rx_errdetect 8 1 16 2 32 4 channel rx_disperr output 8b/10b disparity error indicator port. available in configurations with 8b/10b decoder. a high level indicates that a disparity error was detected on the associated received code group. the width of this signal depends on the following channel width: channel width rx_disperr 8 1 16 2 32 4 channel tab le 1 ?2 . hardcopy iv gx altgx megafunction ports (part 6 of 14) port name input/output description scope
1?14 chapter 1: hardcopy iv gx transceiver architecture transceiver port list hardcopy iv device handbook volume 3 ? june 2009 altera corporation rx_runningdisp output 8b/10b running disparity indicator. this feature is available in configurations with the 8b/10b decoder. a high level indicates that data on the rx_dataout port was received with a negative running disparity. a low level indicates that data on the rx_dataout port was received with a positive running disparity. the width of this signal depends on the following channel width: channel width rx_runningdisp 8 1 16 2 32 4 channel byte ordering block rx_enabyteord input enable byte ordering control. this feature is available in configurations with the byte ordering block enabled. the byte ordering block is rising-edge sensitive to this signal. a low-to-high transition triggers the byte ordering block to restart the byte ordering operation. asynchronous signal. channel rx_byteorderalignstatus output byte ordering status indicator. this feature is available in configurations with the byte ordering block enabled. a high level indicates that the byte ordering block has detected the programmed byte ordering pattern in the lsbyte of the received data from the byte deserializer. channel receiver phase compensation fifo rx_dataout output parallel data output from the receiver to the core fabric. the bus width depends on the channel width multiplied by the number of channels per instance. channel rx_clkout output recovered clock from the receiver channel. this feature is available only when the rate match fifo is not used in the receiver datapath. channel rx_coreclk input optional read clock port for the receiver phase compensation fifo. if not selected, the quartus ii software automatically selects rx_clkout/tx_clkout/coreclkout as the read clock for the receiver phase compensation fifo. if selected, you must drive this port with a clock that has 0 ppm difference with respect to rx_clkout/tx_clkout/ coreclkout . channel tab le 1 ?2 . hardcopy iv gx altgx megafunction ports (part 7 of 14) port name input/output description scope
chapter 1: hardcopy iv gx transceiver architecture 1?15 transceiver port list ? june 2009 altera corporation hardcopy iv device handbook volume 3 rx_phase_comp_fifo_error output receiver phase compensation fifo full or empty indicator. a high level indicates that the receiver phase compensation fifo is either full or empty. channel receiver physical media attachment (pma) rx_datain input receiver serial data input port. channel rx_cruclk input input reference clock for the receiver clock and data recovery. channel rx_pll_locked output receiver cdr lock-to-reference (ltr) indicator. a high level indicates that the receiver cdr is locked to the input reference clock. a low level indicates that the receiver cdr is not locked to the input reference clock. asynchronous signal. channel rx_freqlocked output receiver cdr lock mode indicator. a high level indicates that the receiver cdr is in lock-to-data (ltd) mode. a low level indicates that the receiver cdr is in lock-to-reference mode. asynchronous signal. channel rx_locktodata input receiver cdr lock-to-data mode control signal. when asserted high, the receiver cdr is forced to lock-to-data mode. when de-asserted low, the receiver cdr lock mode depends on the rx_locktorefclk signal level. channel rx_locktorefclk input receiver cdr lock-to-reference mode control signal. the rx_locktorefclk signal along with the rx_locktodata signal controls whether the receiver cdr is in lock-to-reference or lock-to-data mode, as follows: rx_locktodata/ rx_locktorefclk 0/0?receiver cdr is in automatic mode 0/1?receiver cdr is in ltr mode 1/x?receiver cdr is in ltd mode asynchronous signal. channel tab le 1 ?2 . hardcopy iv gx altgx megafunction ports (part 8 of 14) port name input/output description scope
1?16 chapter 1: hardcopy iv gx transceiver architecture transceiver port list hardcopy iv device handbook volume 3 ? june 2009 altera corporation rx_signaldetect output signal threshold detect indicator. this feature is available only in pci express (pipe) mode. a high level indicates that the signal present at the receiver input buffer is above the programmed signal detection threshold value. if the electrical idle inference block is disabled in pipe mode, the rx_signaldetect signal is inverted and driven on the pipeelecidle port. asynchronous signal. channel rx_seriallpbken input serial loopback control port. 0?normal datapath, no serial loopback 1?serial loopback channel transmitter physical coding sublayer ports transmitter phase compensation fifo tx_datain input parallel data input from the core fabric to the transmitter. the bus width depends on the channel width multiplied by the number of channels per instance. channel tx_clkout output core fabric-transceiver interface clock. each channel has a tx_clkout signal in non-bonded channel configurations. use this clock signal to clock the parallel data tx_datain from the core fabric into the transmitter. this signal is not available in bonded channel configurations. channel tx_coreclk input optional write clock port for the transmitter phase compensation fifo. if not selected, the quartus ii software automatically selects tx_clkout/coreclkout as the write clock for transmitter phase compensation fifo. if selected, you must drive this port with a clock that is frequency locked to tx_clkout/coreclkout . channel tx_phase_comp_fifo_error output transmitter phase compensation fifo full or empty indicator. a high level indicates that the transmitter phase compensation fifo is either full or empty. channel tab le 1 ?2 . hardcopy iv gx altgx megafunction ports (part 9 of 14) port name input/output description scope
chapter 1: hardcopy iv gx transceiver architecture 1?17 transceiver port list ? june 2009 altera corporation hardcopy iv device handbook volume 3 8b/10b encoder tx_ctrlenable input 8b/10b encoder /kx.y/ or /dx.y/ control. when asserted high, the 8b/10b encoder encodes the data on the tx_datain port as a /kx.y/ control code group. when de-asserted low, it encodes the data on the tx_datain port as a /dx.y/ data code group. the width of this signal depends on the following channel width: channel width tx_ctrlenable 8 1 16 2 32 4 channel tx_forcedisp input 8b/10b encoder force disparity control. when asserted high, it forces the 8b/10b encoder to encode the data on the tx_datain port with a positive or negative disparity depending on the tx_dispval signal level. when de-asserted low, the 8b/10b encoder encodes the data on the tx_datain port according to the 8b/10b running disparity rules. the width of this signal depends on the following channel width: channel width tx_forcedisp 8 1 16 2 32 4 channel tx_dispval input 8b/10b encoder force disparity value. a high level on the tx_dispval signal when the tx_forcedisp signal is asserted high forces the 8b/10b encoder to encode the data on the tx_datain port with a negative starting running disparity. a low level on the tx_dispval signal when the tx_forcedisp signal is asserted high forces the 8b/10b encoder to encode the data on the tx_datain port with a positive starting running disparity. the width of this signal depends on the following channel width: channel width tx_dispval 8 1 16 2 32 4 channel tab le 1 ?2 . hardcopy iv gx altgx megafunction ports (part 10 of 14) port name input/output description scope
1?18 chapter 1: hardcopy iv gx transceiver architecture transceiver port list hardcopy iv device handbook volume 3 ? june 2009 altera corporation tx_invpolarity input transmitter polarity inversion control. this feature is useful for correcting situations in which the positive and negative signals of the differential serial link are accidentally swapped during board layout. when asserted high in single-width modes, the polarity of every bit of the 8-bit or 10-bit input data to the serializer gets inverted. when asserted high in double-width modes, the polarity of every bit of the 16-bit or 20-bit input data to the serializer gets inverted. asynchronous signal. channel transmitter physical media attachment tx_dataout output transmitter serial data output port. channel fixedclk input 125-mhz clock for receiver detect and offset cancellation in pci express (pipe) mode. channel dynamic reconfiguration reconfig_clk input dynamic reconfiguration clock. this clock is also used for offset cancellation in all modes except pipe mode. the frequency range of this clock is 2.5 mhz to 50 mhz when the transceiver channel is configured in transmitter only mode. the frequency range of this clock is 37.5 mhz to 50 mhz when the transceiver channel is configured in receiver only or receiver and transceiver mode. reconfig_togxb input from the dynamic reconfiguration controller. reconfig_fromgxb output to the dynamic reconfiguration controller. pci express (pipe) interface (available only in pipe functional mode) powerdn input pipe power state control. functionally equivalent to the powerdown[1:0] signal defined in the pipe specification revision 2.0. the width of this signal is two bits and is encoded as follows: 2'b00: p0?normal operation 2'b01: p0s?low recovery time latency, low power state 2'b10: p1?longer recovery time latency, lower power state 2'b11: p2?lowest power state channel tab le 1 ?2 . hardcopy iv gx altgx megafunction ports (part 11 of 14) port name input/output description scope
chapter 1: hardcopy iv gx transceiver architecture 1?19 transceiver port list ? june 2009 altera corporation hardcopy iv device handbook volume 3 tx_forcedispcompliance input force 8b/10b encoder to encode with a negative running disparity. functionally equivalent to the txcompliance signal defined in pci express (pipe) specification revision 2.0. must be asserted high only when transmitting the first byte of the pipe compliance pattern to force the 8b/10b encode with a negative running disparity as required by the pipe protocol. channel tx_forceelecidle input force transmitter buffer to pipe electrical idle signal levels. functionally equivalent to the txelecidle signal defined in the pci express (pipe) specification revision 2.0. channel rateswitch input pipe rateswitch control. 1?b0?gen1 (2.5 gbps) 1?b1?gen2 (5 gbps) tx_pipemargin input transmitter differential output voltage (v od ) level control. this feature is functionally equivalent to the txmargin signal defined in the pipe specification revision 2.0. available only in pipe gen2 configuration. the width of this signal is 3 bits per channel and is decoded as follows: 3?b000?normal operating range 3?b001?full swing = 800 ? 1200 mv low swing = 400 ? 700m v 3?b010?tbd 3?b011?tbd 3?b100?if last value full swing = 200 ? 400 mv 3?b101?if last value full swing = 200 ? 400 mv 3?b110?if last value full swing = 200 ? 400 mv 3?b111?if last value full swing = 200 ? 400 mv tx_pipedeemph input transmitter buffer de-emphasis level control. this feature is functionally equivalent to the txdeemph signal defined in the pipe specification revision 2.0. available only in pci express (pipe) gen2 configuration. 1?b0: -6 db de-emphasis 1?b1:-3.5 db de-emphasis tab le 1 ?2 . hardcopy iv gx altgx megafunction ports (part 12 of 14) port name input/output description scope
1?20 chapter 1: hardcopy iv gx transceiver architecture transceiver port list hardcopy iv device handbook volume 3 ? june 2009 altera corporation pipe8b10binvpolarity input pci express (pipe) polarity inversion control. functionally equivalent to the rxpolarity signal defined in the pipe specification revision 2.0. this feature is available only in pipe mode. when asserted high, the polarity of every bit of the 10-bit input data to the 8b/10b decoder gets inverted. channel tx_detectrxloopback input receiver detect or pci express (pipe) loopback control. this feature is functionally equivalent to the txdetectrx/loopback signal defined in the pipe specification revision 2.0. when asserted high in the p1 power state with the tx_forceelecidle signal asserted, the transmitter buffer begins the receiver detection operation. after the receiver detect completion is indicated on the pipephydonestatus port, this signal must be de-asserted. when asserted high in the p0 power state with the tx_forceelecidle signal de-asserted, the transceiver datapath gets dynamically configured to support parallel loopback as described in ?pci express (pipe) reverse parallel loopback? on page 1?191 . channel pipestatus output pipe receiver status port. this feature is functionally equivalent to the rxstatus[2:0] signal defined in the pipe specification revision 2.0. the width of this signal is 3-bits per channel. the encoding of receiver status on the pipestatus port is as follows: 000?received data ok 001?1 skip added 010?1 skip removed 011?receiver detected 100?8b/10b decoder error 101?elastic buffer overflow 110?elastic buffer underflow 111?received disparity error channel pipephydonestatus output phy function completion indicator. this feature is functionally equivalent to the phystatus signal defined in the pipe specification revision 2.0. assert this signal high for one parallel clock cycle to communicate completion of several phy functions, such as power state transition, receiver detection, and signaling rate change between gen1 (2.5 gbps) and gen2 (5 gbps). channel tab le 1 ?2 . hardcopy iv gx altgx megafunction ports (part 13 of 14) port name input/output description scope
chapter 1: hardcopy iv gx transceiver architecture 1?21 transceiver port list ? june 2009 altera corporation hardcopy iv device handbook volume 3 rx_pipedatavalid output valid data and control on the rx_dataout and rx_ctrldetect ports indicator. functionally equivalent to the rxvalid signal defined in the pipe specification revision 2.0. channel pipeelecidle output electrical idle detected or inferred at the receiver indicator. this feature is functionally equivalent to the rxelecidle signal defined in the pci express (pipe) specification revision 2.0. if the electrical idle inference block is enabled, it drives this signal high when it infers an electrical idle condition, as described in ?electrical idle inference? on page 1?136 . otherwise, it drives this signal low. if the electrical idle inference block is disabled, the rx_signaldetect signal from the signal detect circuitry in the receiver buffer is inverted and driven on this port. asynchronous signal. channel reset and power down gxb_powerdown input transceiver block power down. when asserted high, all digital and analog circuitry within the pcs, pma, cmu channels, and the ccu of the transceiver block is powered down. asserting the gxb_powerdown signal does not power down the refclk buffers. asynchronous signal. the minimum pulse width is 1 s (pending characterization). transceiver block rx_digitalreset input receiver pcs reset. when asserted high, the receiver pcs blocks are reset. the minimum pulse width is two parallel clock cycles. channel rx_analogreset input receiver pma reset. when asserted high, analog circuitry within the receiver pma gets reset. the minimum pulse width is two parallel clock cycles. channel tx_digitalreset input transmitter pcs reset. when asserted high, the transmitter pcs blocks are reset. the minimum pulse width is two parallel clock cycles. channel calibration block cal_blk_clk input clock for transceiver calibration blocks. device cal_blk_powerdown input calibration block power down control. device tab le 1 ?2 . hardcopy iv gx altgx megafunction ports (part 14 of 14) port name input/output description scope
1?22 chapter 1: hardcopy iv gx transceiver architecture cmu channels hardcopy iv device handbook volume 3 ? june 2009 altera corporation cmu channels the hardcopy iv gx device contains two cmu channels?the cmu0 and cmu1 channels?within each transceiver block. the cmu channels can be configured as a transceiver channel or as a clock generation block. the building blocks used in the cmu channels to achieve this are described below. each cmu channel contains a cmu pll that provides clocks to the transmitter channels within the same transceiver block. configuring cmu channels for clock generation the cmu0 channel has additional capabilities to support bonded protocol functional modes such as basic 4, xaui, and pci express (pipe). you can select these functional modes from the altgx megawizard plug-in manager. you can enable basic 4 functional mode in the altgx megawizard plug-in manager by selecting the 4 option in basic mode.
chapter 1: hardcopy iv gx transceiver architecture 1?23 cmu channels ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?7 shows a top-level block diagram of the cmu channels in a transceiver block. figure 1?7. top-level diagram of cmu channels in a transceiver block note to figure 1?7 : (1) clocks are provided to suppor t bonded channel f unctional mode. hardcopy iv gx transceiver block local clock divider block high-speed serial clock low-speed parallel clock transmitter channel 2 transmitter channel 3 to transmitter pma to transmitter pcs cmu1 pll high-speed clock cmu0 pll high-speed clock high-speed serial clock (1) low-speed parallel clock (1) local clock divider block high-speed serial clock low-speed parallel clock transmitter channel 0 transmitter channel 1 to transmitter pma to transmitter pcs cmu1 channel cmu0 channel input reference clocks input reference clocks
1?24 chapter 1: hardcopy iv gx transceiver architecture cmu channels hardcopy iv device handbook volume 3 ? june 2009 altera corporation cmu0 channel the cmu0 channel, shown in figure 1?8 , contains the following blocks: cmu0 pll cmu0 clock divider cmu0 pll figure 1?9 shows a block diagram of the cmu0 pll. figure 1?8. block diagram of the cmu0 channel notes to figure 1?8 : (1) in non-bonded functional modes (for example, gige functional mode), the transmitter channel uses the transmitter local clock divider to divide this high-speed clock output to provide clocks for its pma and pcs blo cks. (2) used in xaui, basic 4, and pci express (pipe) 4 f unctional modes. in pipe 8 functional mode, only the cmu0 channel of the master transceiver block provides clock output to all eight transceiver channels configured in pipe functional mode. 6 pll_powerdown pll cascade clock global clock line dedicated refclk0 dedicated refclk1 itb clock lines cmu0 pll input reference clock cmu0 pll cmu0 pll high-speed clock (1) cmu0 channel cmu1 pll high-speed clock cmu0 clock divider pcie_gen2switch (to pci express rateswitch controller block in the ccu) pcie_gen2switch_done (to pci express rateswitch controller block in the ccu) high-speed serial clock for bonded modes (2) low-speed parallel clock for bonded modes pll_powerdown pll_locked figure 1?9. block diagram of the cmu0 pll note to figure 1?9 : (1) the inter transceiver block (itb) clock lines shown are the maximum value. the actual number of itb lines in your device dep ends on the number of transceiver blocks on one side of the device. pfd 6 cmu0 pll pll cascade clock global clock line dedicated refclk0 dedicated refclk1 itb clock lines (1) cmu0 pll input reference clock /m charge pump + loop filter v co /l cmu0 high-speed clock /1, /2, /4, /8
chapter 1: hardcopy iv gx transceiver architecture 1?25 cmu channels ? june 2009 altera corporation hardcopy iv device handbook volume 3 you can select the input reference clock to the cmu0 pll from multiple clock sources. the various clock sources are: refclk0 ?dedicated refclk in the transceiver block refclk1 ?dedicated refclk in the transceiver block refclk0 and refclk1 of all other transceiver blocks on the same side of the device the cmu0 pll generates the high-speed clock from the input reference clock. the phase frequency detector (pfd) tracks the voltage-controlled oscillator (vco) output with the input reference clock. the vco in the cmu0 pll is half rate and runs at half the serial data rate. the cmu0 pll uses two multiplier blocks (/m and /l) in the feedback path (shown in figure 1?9 ) to generate the high-speed clock needed to support a native data rate range of 600 mbps to 6.5 gbps. 1 the altgx megawizard plug-in manager provides the list of input reference clock frequencies based on the data rate selected. the quartus ii software automatically selects the /m and /l settings based on the input reference clock frequency and serial data rate. each cmu pll ( cmu0 pll and cmu1 pll) has a dedicated pll_locked signal that is asserted to indicate that the cmu pll is locked to the input reference clock. pll bandwidth setting you can program the pll bandwidth setting using the altgx megawizard plug-in manager. the bandwidth of a pll is the measure of its ability to track input clock and jitter. it is determined by the ?3 db frequency of the closed-loop gain of the pll. there are three bandwidth settings: high, medium, and low. cmu0 pll by asserting the pll_powerdown signal.
1?26 chapter 1: hardcopy iv gx transceiver architecture cmu channels hardcopy iv device handbook volume 3 ? june 2009 altera corporation cmu0 clock divider block the high-speed clock output from the cmu0 pll is forwarded to two clock divider blocks: the cmu0 clock divider block and the transmitter channel local clock divider block. this clock divider block is used only in bonded channel functional modes. in all non-bonded functional modes (such as gige functional mode), the local clock divider block divides the high-speed clock to provide clocks for its pcs and pma blocks. this section only describes the cmu0 clock divider block. you can configure the cmu0 clock divider block, shown in figure 1?10 , to select the high-speed clock output from the cmu0 pll or cmu1 pll. the cmu1 pll is present in the cmu1 channel. high-speed serial clock generation the /n divider receives the high-speed clock output from one of the cmu plls and produces a high-speed serial clock. this high-speed serial clock is used for bonded functional modes such as basic 4, xaui, and pci express (pipe) 4 configurations. in xaui and basic 4 modes, the quartus ii software chooses the path (shown by ?1? in the multiplexer) and provides the high-speed serial clock to all the transmitter channels within the transceiver block. in pipe 4 mode, the clock path through the pipe rateswitch circuit block is selected. this high-speed serial clock is provided to all the transmitter channels. in pipe 8 mode, only the cmu0 clock divider of the master transceiver block provides the high-speed serial clock to all eight channels. in pipe 1 mode, the cmu0 clock divider does not provide a high-speed serial clock. instead, the local clock divider block in the transmitter channel receives the cmu0 pll or cmu1 pll high-speed clock output and generates the high-speed serial clock to its serializer. pcie rateswitch circuit the pcie rateswitch circuit is enabled only in pipe 4 mode. in pipe 8 mode, the pcie rateswitch circuit of the cmu0 clock divider of the master transceiver block is active. there are two paths in the pcie rateswitch circuit. one path divides the /n output by two. the other path forwards the /n divider output. figure 1?10. cmu0 clock divider block pcie_gen2switch_done pcie_gen2switch cmu0 high-speed clock output cmu1 high-speed clock output cmu0 clock divider block /n (1, 2, 4) pcie rateswitch circuit /s (4, 5, 8, 10) coreclkout to core fabric (for bonded modes) high-speed serial clock (for bonded modes) low-speed parallel clock for transmitter channel pcs (for bonded modes) /2 1 0
chapter 1: hardcopy iv gx transceiver architecture 1?27 cmu channels ? june 2009 altera corporation hardcopy iv device handbook volume 3 when you set the rateswitch port to 0 , the pci express (pipe) rateswitch controller (in the ccu) signals the pcie rateswitch circuit to select the divide by /2 to provide a high-speed serial clock for the gen1 (2.5 gbps) data rate. when the rateswitch port is set to 1 , the /n divider output is forwarded, providing a high-speed serial clock for the gen2 (5 gbps) data rate to the transmitter channels. 1 the pcie rateswitch circuit performs the rateswitch operation only for the transmitter channels. for the receiver channels, the rateswitch circuit within the receiver cdr performs the rateswitch operation. the pcie rateswitch circuit is controlled by the pipe rateswitch controller in the ccu. the pipe rateswitch controller asserts the pipephydonestatus signal for one clock cycle after the rateswitch operation is completed for both the transmit and receive channels. figure 1?11 shows the timing diagram for the rateswitch operation. for more information about pci express (pipe) functional mode rateswitch, refer to ?pci express (pipe) gen2 (5 gbps) support? on page 1?137 . 1 when you create a pipe gen2 configuration, configure the cmu pll to 5 gbps. this helps to generate the 2.5 gbps and 5 gbps high-speed serial clock using the rateswitch circuit. low-speed parallel clock generation the /s divider receives the clock output from the /n divider or pcie rateswitch circuit (only in pipe mode) and generates the low-speed parallel clock for the pcs block of all transmitter channels and coreclkout for the core fabric. if the byte serializer block is enabled in bonded channel modes, the /s divider output is divided by the /2 divider and sent out as coreclkout to the core fabric. the quartus ii software automatically selects the /s values based on the deserialization width setting (single-width mode or double-width mode) that you select in the altgx megawizard plug-in manager. for more information about single-width or double- width mode, refer to ?transceiver channel architecture? on page 1?34 . 1 the quartus ii software automatically selects all the divider settings based on the input clock frequency, data rate, deserialization width, and channel width settings. figure 1?11. rateswitch in pci express (pipe) mode (note 1) note to figure 1?11 : (1) time t1 is pending characterization. rateswitch pipephydonestatus t1 t1 low-speed parallel clock 250 mhz (gen 1) 500 mhz (gen 2) 250 mhz (gen 1)
1?28 chapter 1: hardcopy iv gx transceiver architecture cmu channels hardcopy iv device handbook volume 3 ? june 2009 altera corporation cmu1 channel the cmu1 channel shown in figure 1?12 contains the cmu1 pll that provides the high-speed clock to the transmitter channels within the transceiver block. the cmu1 pll is similar to the cmu0 pll. the functionality of the cmu0 pll is described in ?cmu0 pll? on page 1?24 . the cmu1 pll generates the high-speed clock that is only used in non-bonded functional modes. in non-bonded functional modes, the transmitter channels within the transceiver block can receive a high-speed clock from either of the two cmu plls and uses local dividers to provide clocks to its pcs and pma blocks. power down cmu1 pll yo u c a n p o we r d o w n t he cmu1 pll by asserting the pll_powerdown signal. figure 1?12. cmu1 channel (grayed area shows the inactive block) 6 pll cascade clock global clock line dedicated refclk0 dedicated refclk1 itb clock lines cmu1 pll input reference clock cmu1 pll cmu1 channel cmu1 pll high-speed clock cmu1 clock divider pll_powerdown pll_locked
chapter 1: hardcopy iv gx transceiver architecture 1?29 cmu channels ? june 2009 altera corporation hardcopy iv device handbook volume 3 configuring cmu channels as transceiver channels the two cmu channels in the transceiver block can be configured as a transceiver channel to run between 600 mbps and 6.5 gbps. figure 1?13 shows the functional blocks that are enabled to support the transceiver channel functionality. 1 cfr rcvr c rfrc cc cfr rcv r 1 w r r rcv r figure 1?13. functional blocks enabled to support transceiver channel functionality cmu pll co n figured as rx cdr serializer deserializer high-speed clock from the adjacent cmu channel x4 clock line from x n top clock line from x n bottom clock line from the core fa b ric to t h e core fa b ric cmu channel cmu clock divider b lock (/1, /2, /4) tx_data_out tx_data_in tab le 1 ?3 . pins used as transmit and receive serial pins (part 1 of 2) pins (1) when a cmu channel is configured as a transceiver channel when a cmu channel is configured for clock generation refclk_[l,r][0,2,4,6]p, gxb_cmurx_[l_r][0,2,4,6]p (2) receive serial input for cmu channel0 input reference clocks gxb_tx_[l,r][0,2,4,6] (2) transmit serial output for cmu channel0 not available for use refclk_[l,r][1,3,5,7]p, gxb_cmurx_[l_r][1,3,5,7]p (3) receive serial input for cmu channel1 input reference clocks
1?30 chapter 1: hardcopy iv gx transceiver architecture cmu channels hardcopy iv device handbook volume 3 ? june 2009 altera corporation interpret the pin column as follows: for pins refclk_[l,r][0,2,4,6]p, gxb_cmurx_[l_r][0,2,4,6] , the l, r indicates the left and right side and the 0, 2, 4, 6 indicates the different pins. for example, a pin on the left side with index 0 is named: refclk_l0p, gxb_cmurx_l0p. 1 rcvr r r rwr r crr c fr 1 serializer and deserializer the serializer and deserializer convert the parallel-to-serial and serial-to-parallel data on the transmitter and receiver side, respectively. the altgx megawizard plug-in manager provides a new functional mode ?basic (pma-direct) mode? (with a none and n option) to configure a transceiver channel to enable the transmitter serializer and receiver deserializer. to configure a cmu channel as a transceiver channel, you must use this functional mode. the input data width options to serializer / from deserializer for a channel configured in this mode are 8, 10, 16, and 20. cmu clock divider block when you configure a cmu channel in basic (pma-direct)1 mode, this block divides the high-speed clock from the other cmu channel (used as a clock generation unit) within the same transceiver block and provides the high-speed serial clock and low-speed parallel clocks to the transmitter side of the cmu channel. the cmu clock divider block can divide the high-speed clock by /1, /2, and /4. clocks for the transmitter serializer when the cmu channel is configured as a transceiver channel, the clocks for the transmitter side can be provided by one of these sources:  the other cmu channel in the same transceiver block that is configured as a clock multiplication unit gxb_tx_[l,r][1,3,5,7]p (3) transmit serial output for cmu channel1 not available for use notes to ta bl e 1? 3 : (1) these indexes are for the hardcopy iv gx device with the maximum number of transceiver blocks. for exact information about how many of these pins are available for a specific device family, refer to the hardcopy iv device family overview chapter in volume 1 of the hardcopy iv device handbook . (2) pins 0,2,4,6 are hardwired to cmu channel0 in the corresponding transceiver blocks. (3) pins 1,3,5,7 are hardwired to cmu channel1 in the corresponding transceiver blocks. tab le 1 ?3 . pins used as transmit and receive serial pins (part 2 of 2) pins (1) when a cmu channel is configured as a transceiver channel when a cmu channel is configured for clock generation
chapter 1: hardcopy iv gx transceiver architecture 1?31 cmu channels ? june 2009 altera corporation hardcopy iv device handbook volume 3  from cmu channel0 on the other transceiver block on the same side of the device through the n clock line ( n_top or n_bottom clock line). if you configure a cmu channel in basic (pma-direct) n mode, you can use this clocking option  from one of the atx pll blocks on the same side of the device through the n clock line ( n_top or n_bottom clock line) input reference clocks for the receiver cdr when a cmu channel is configured as a transceiver channel, there are multiple sources of input reference clocks for the receiver cdr: 1. from adjacent refclks within the same transceiver block, if the adjacent cmu channel is not used as a transceiver channel 2. from the refclk of adjacent transceiver blocks on the same side of the device, if the corresponding cmu channels are not used as transceiver channels. for refclk connections to the cmu channel from the global clock lines and pll cascade network, refer to table 1?4 on page 1?36 . clocks for the receiver deserializer the cdr provides the high-speed serial and low-speed parallel clock to the receiver deserializer high-speed clock. the receiver deserializer is provided by the high-speed serial and parallel clock of the cdr from the recovered data. there are multiple sources to provide input reference clocks to the cdr of the cmu channel. other cmu channel features the cmu channels provide the following features:  analog control options?differential output voltage ( v od ), pre-emphasis, equalization, and dc gain settings present in the regular channels are also available in the cmu channels.  on-chip termination (oct)?cmu channels can have an on-chip termination feature. the allowed termination values are the same as regular channels (85, 100, 120, 150  ).  loopback?the available loop back options are serial, reverse serial (pre-cdr), and reverse serial (cdr) loopback. for more information about analog controls and on-chip termination, refer to ?transmitter output buffer? on page 1?52 , and ?receiver input buffer? on page 1?59 . for more information about loopback, refer to ?loopback modes? on page 1?188 . dynamic reconfiguration you can dynamically reconfigure the analog controls of the cmu channel using the dynamic reconfiguration controller. f for more information about dynamic reconfiguration options, refer to the hardcopy iv gx dynamic reconfiguration chapter in volume 3 of the hardcopy iv device handbook .
1?32 chapter 1: hardcopy iv gx transceiver architecture auxiliary transmit (atx) pll block hardcopy iv device handbook volume 3 ? june 2009 altera corporation auxiliary transmit (atx) pll block the hardcopy iv gx transceiver contains the atx pll block that you can use to generate high-speed clocks for the transmitter channels on the same side of the device. the following data rates are supported by the atx plls: figure 1?14. location of atx pll block in a two-transceiver block device figure 1?15. location of atx pll blocks in a four-transceiver block device (two on each side) figure 1?16. location of atx pll blocks in a six-transceiver block device gxbr1 atx pll r0 gxbr0 gxbl1 gxbr1 atx pll l0 atx pll r0 gxbl0 gxbr0 gxbl2 gxbl1 gxbl0 atx pll l0 atx pll l1 atx pll r1 atx pll r0 gxbr2 gxbr1 gxbr0
chapter 1: hardcopy iv gx transceiver architecture 1?33 auxiliary transmit (atx) pll block ? june 2009 altera corporation hardcopy iv device handbook volume 3 input reference clocks for the atx pll the atx pll block does not have a dedicated reference clock pin. the following are the possible input reference clock sources: architecture of the atx pll block the atx pll block contains the atx pll, atx clock divider, and a shared control signal generation block, as shown in figure 1?17 . the functional blocks on the atx pll are similar to the blocks explained in ?cmu0 pll? on page 1?24 . the values of the /m and /l divider settings in the atx pll are automatically selected by the quartus ii software based on the transceiver channel configuration. the atx pll high-speed clock output provides high-speed serial clocks for non-bonded functional modes such as cei (with the subprotocol ?none?). figure 1?17. atx pll block notes to figure 1?17 : (1) in non-bonded functional modes (for example, cei functional mode), the transmitter channel uses the transmitter local clock divider to divide this high-speed clock output to provide clocks for its pma and pcs blocks. (2) this is used in basic 4, 8, and pci express (pipe) 4 and 8 functional modes. 8 atx pll high-speed clock (1) atx pll block pll_po w erdo wn cascaded pll clock glob al clock line itb clock lines pcierates witch atx pll inp ut reference clock atx pll high-speed serial clock for bonded modes (2) atx clock divider b lock pcie_gen2s witch pcie_gen2s witch_done pci express rates witch controller
1?34 chapter 1: hardcopy iv gx transceiver architecture transceiver channel architecture hardcopy iv device handbook volume 3 ? june 2009 altera corporation atx clock divider the atx clock divider divides the atx pll high-speed clock and provides high-speed serial and low-speed parallel clock for bonded functional modes such as pci express (pipe) (4, 8), basic 4 and 8, and pma-direct mode with n configuration. for pipe functional mode support, the atx clock divider consists of the pipe rateswitch circuit to enable dynamic rateswitch between pipe gen1 and gen2 data rates. for more information about this circuit, refer to ?cmu0 channel? on page 1?24 . the clock outputs from the atx pll block are provided to the transmitter channels through the n_top or n_bottom clock lines, as shown in figure 1?18 . transceiver channel architecture figure 1?19 shows the hardcopy iv gx transceiver channel datapath. each transceiver channel consists of the following:  transmitter channel, further divided into  transmitter channel pcs  transmitter channel pma figure 1?18. atx clock divider 0 1 atx clock di vider b lock pcie_gen2s witch_done pcie_gen2s witch atx pll high-speed clock o utput pci express clocks witch circuit /s (4, 5, 8, 10) /2 lo w-speed parallel clocks (for bonded modes) coreclko u t to core fab ric (for bonded modes) high-speed serial clock (for bonded modes) figure 1?19. hardcopy iv transceiver datapath serializer transmitter channel pcs transmitter channel pma cdr receiver channel pcs receiver channel pma core fabric pipe interface pci express hardip tx phase compensation fifo byte serializer 8b/10b encoder tx_dataout rx_datain de- serializer word aligner deskew fifo rate match fifo 8b/10 decoder byte de- serializer byte ordering rx phase compensation fifo
chapter 1: hardcopy iv gx transceiver architecture 1?35 transceiver channel architecture ? june 2009 altera corporation hardcopy iv device handbook volume 3  receiver channel, further divided into  receiver channel pcs  receiver channel pma each transceiver channel interfaces to either the pci express (pipe) hard ip block (pipe hard ip-transceiver interface) or directly to the core fabric (core fabric? transceiver interface). the transceiver channel interfaces to the pipe hard ip block if the hard ip block is used to implement the pci express phy mac, data link layer, and transaction layer. otherwise, the transceiver channel interfaces directly to the core fabric. 1 the pipe hard ip?transceiver interface is out of the scope of this chapter. this chapter describes the core fabric-transceiver interface. f for more information about the pci express (pipe) hard ip block, refer to the pci express compiler user guide . figure 1?20 shows the core fabric-transceiver interface and transceiver pma-pcs interface. the transceiver channel datapath can be divided into the following two modes based on the fpga fabric-transceiver interface width (channel width) and the transceiver channel pma-pcs width (serialization factor):  single-width mode  double-width mode figure 1?20. core fabric-transceiver interface and transceiver pma-pcs interface serializer transmitter channel pcs transmitter channel pma cdr receiver channel pcs receiver channel pma core fabric pipe interface pci express hardip tx phase compensation fifo byte serializer 8b/10b encoder tx_dataout rx_datain de- serializer word aligner deskew fifo rate match fifo 8b/10 decoder byte de- serializer byte ordering rx phase compensation fifo core fabric- transceiver interface pma-pcs interface
1?36 chapter 1: hardcopy iv gx transceiver architecture transmitter channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation table 1?4 shows the core fabric-transceiver interface widths (channel width) and transceiver pma-pcs widths (serialization factor) allowed in single-width and double-width modes. transmitter channel datapath the transmitter channel datapath, shown in figure 1?21 , consists of the following blocks: enable low latency pcs mode option in the altgx megawizard plug-in manager. if you select this option, the 8b/10b encoder in the datapath is disabled. tab le 1 ?4 . core fabric-transceiver interface width and transceiver pma-pcs widths name single-width double-width pma-pcs interface widths 8/10 bit 16/20 bit core fabric-transceiver interface width 8/10 bit 16/20 bit 16/20 bit 32/40 bit supported functional modes pci express (pipe) gen1 and gen2 xaui gige serial rapidio sonet/sdh oc12 and oc48 sdi basic single width (oif) cei phy interface sonet/sdh oc96 basic double-width data rate range in basic functional mode 0.6 gbps to 3.75 gbps 1 gbps to 6.5 gbps
chapter 1: hardcopy iv gx transceiver architecture 1?37 transmitter channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 tx phase compensation fifo the tx phase compensation fifo interfaces the transmitter channel pcs and the core fabric pci express (pipe) interface. it compensates for the phase difference between the low-speed parallel clock and the core fabric interface clock. the tx phase compensation fifo operates in low-latency and high-latency mode. figure 1?22 shows the datapath and clocking of the tx phase compensation fifo. tx phase compensation fifo: tx_clkout port of the associated channel. figure 1?21. transmitter channel datapath serializer transmitter channel pcs transmitter channel pma core fabric pci express hardip pipe interface tx phase compensation fifo byte serializer 8b/10b encoder figure 1?22. tx phase compensation fifo data path from the core fabric or pipe interface tx_coreclk tx_clkout coreclkout data path to the byte serializer or the 8b/10b encoder or serializer tx phase compensation fifo wr_clk rd_clk
1?38 chapter 1: hardcopy iv gx transceiver architecture transmitter channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation in bonded functional modes such as xaui, the write clock of the fifo is clocked by coreclkout provided by the cmu0 clock divider block . you can clock the write side using tx_coreclk provided from the core fabric by enabling the tx_coreclk port in the altgx megawizard plug-in manager. if you use this port, ensure that there is 0 ppm difference in frequency between the write and read side. the quartus ii software requires that you provide a 0 ppm assignment in the assignment editor. input data in pci express (pipe) functional mode, the input data comes from the pipe interface. in all other functional modes, the input data comes directly from the core fabric. output data destination block the output from the tx phase compensation fifo is used by the byte serializer block, 8b/10b encoder, or serializer block. table 1?5 lists the conditions under which the tx phase compensation fifo outputs are provided to these blocks. tx phase compensation fifo status signal an optional tx_phase_comp_fifo_error port is available in all functional modes to indicate a receiver phase compensation fifo overflow or under-run condition. the tx_phase_comp_fifo_error signal is asserted high when the tx phase compensation fifo either overflows or under-runs due to any frequency ppm difference between the fifo read and write clocks. if the tx_phase_comp_fifo_error flag is asserted, verify the core fabric-transceiver interface clocking to ensure that there is 0 ppm difference between the tx phase compensation fifo read and write clocks. byte serializer the byte serializer divides the input datapath by two. this allows the transceiver channel to run at higher data rates while keeping the core fabric interface frequency within the maximum limit of 250 mhz. in single-width mode, it converts the two byte wide datapath to a one byte wide datapath. in double-width mode, it converts the four-byte wide datapath to a two byte wide datapath. tab le 1 ?5 . output data destination block for tx phase compensation fifo output data byte serializer 8b/10b encoder serializer if you select: single-width mode and channel width = 16 or 20 if you select: single-width mode and channel width = 8 and 8b/10b encoder enabled if you select: low-latency pcs bypass mode enabled or single-width mode and channel width = 8 or 10 if you select: double-width mode and channel width = 32 or 40 if you select: double-width mode and channel width = 16 and 8b/10b encoder enabled if you select: low-latency pcs bypass mode enabled or double-width mode and channel width = 16 or 20
chapter 1: hardcopy iv gx transceiver architecture 1?39 transmitter channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 for example, if you want to run the transceiver channel at 6.25 gbps, without the byte serializer, in double-width mode, the core fabric interface clock frequency must be 312.5 mhz (6.25/20). this violates the core fabric interface frequency limit. when you use the byte serializer, the core fabric interface frequency is 156.25 mhz (6.25g/40). you can enable the byte serializer in single-width or double-width mode. 1 rr rr cfr c cr frcrcvr rfc frc cfr c cr frcrcvr rfc frc f r r fr frc fr rcvr rfc rfr hardcopy iv device datasheet in volume 4 of the hardcopy iv device handbook . single-width mode figure 1?23 shows the byte serializer datapath in single-width mode. the byte serializer forwards the least significant byte first, followed by the most significant byte. the input data width to the byte serializer depends on the channel width option that you selected in the altgx megawizard plug-in manager. for example, in single-width mode, assuming a channel width of 20, the byte serializer sends out the least significant word datain[9:0] of the parallel data from the core fabric, followed by datain[19:10]. table 1?6 shows the input and output data widths of the byte serializer in single-width mode. figure 1?23. byte serializer datapath in single-width mode (note 1) , (2) notes to figure 1?23 : (1) refer to table 1?6 on page 1?39 for the datain[] and dataout[] port widths. (2) the datain signal is the input from the core fabric that has already passed through the tx phase compensation fifo. tab le 1 ?6 . input and output data width of the byte serializer in single-width mode deserialization width input data width to the byte serializer output data width from the byte serializer single-width mode 16 8 20 10 /2 datain[] dataout[] low-speed parallel clock byte serializer
1?40 chapter 1: hardcopy iv gx transceiver architecture transmitter channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation double-width mode figure 1?24 shows the byte serializer datapath in double-width mode. the operation in double-width mode is similar to that of single-width mode. for example, assuming a channel width of 40, the byte serializer forwards datain[19:0] first, followed by datain[39:20]. table 1?7 shows the input and output data widths of the byte serializer in double-width mode. asserting the tx_digitalreset signal resets the byte serializer block. if you select the 8b/10b encoder option in the altgx megawizard plug-in manager, the 8b/10b encoder uses the output from the byte serializer. otherwise, the byte serializer output is forwarded to the serializer. 8b/10b encoder the 8b/10b encoder generates 10-bit code groups from the 8-bit data and 1-bit control identifier. the 8b/10b encoder operates in two modes: single-width and double-width.  in single-width mode, the 8b/10b encoder generates a 10-bit code group from the 8-bit data and 1-bit control identifier.  in double-width mode, there are two 8b/10b encoders that are cascaded together to generate two 10-bit code groups from two 8-bit data and their respective control identifiers. figure 1?24. byte serializer datapath in double-width mode (note 1) , (2) notes to figure 1?24 : (1) refer to table 1?7 for the datain[] and dataout[] port width. (2) the datain signal is the input from the core fabric that has already passed through the tx phase compensation fifo. tab le 1 ?7 . input and output data width of the byte serializer in double-width mode deserialization width input data width to the byte serializer output data width from the byte serializer double-width mode 32 16 40 20 /2 byte serializer datain[] dataout[] low-speed parallel clock
chapter 1: hardcopy iv gx transceiver architecture 1?41 transmitter channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 single-width mode figure 1?25 shows the 8b/10b encoder in single-width mode. in single-width mode, the 8b/10b encoder translates the 8-bit data to a 10-bit code group (control word or data word) with proper disparity. if the control_code input is high, the 8b/10b encoder translates the input data[7:0] to a 10-bit control word. if the control_code input is low, the 8b/10b encoder translates the input data[7:0] to a 10-bit data word. you can use the tx_forcedisp and tx_dispval ports to control the running disparity of the generated output data. for more information, refer to ?controlling running disparity? on page 1?45 . figure 1?26 shows the conversion format. the lsb is transmitted first. control code encoding the altgx megawizard plug-in manager provides the tx_ctrlenable port to indicate whether the 8-bit data at the tx_datain port should be encoded as a control word (kx.y). when tx_ctrlenable is low, the 8b/10b encoder block encodes the byte at the tx_datain port (the user-input port) as data (dx.y). when tx_ctrlenable is high, the 8b/10b encoder encodes the input data as a kx.y code group. the waveform in figure 1?27 shows the second 0 bc encoded as a control word (k28.5). the rest of the tx_datain bytes are encoded as a data word (dx.y). figure 1?25. 8b/10b encoder in single-width mode figure 1?26. 8b/10b conversion format from the byte serializer datain[7:0] control_code tx_forcedisp tx_dispval 8b/10b encoder dataout[9:0] to the serializer 7 6 5 4 3 2 1 0 hgf edcba 7 6 5 4 3 2 1 0 9 8 gf iedcba jh lsb msb control_code 8b/10b conversion
1?42 chapter 1: hardcopy iv gx transceiver architecture transmitter channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation the ieee 802.3 8b/10b encoder specification identifies only a set of 8-bit characters for which tx_ctrlenable should be asserted. if you assert tx_ctrlenable for any other set of bytes, the 8b/10b encoder might encode the output 10-bit code as an invalid code (it does not map to a valid dx.y or kx.y code), or unintended valid dx.y code, depending on the value entered. it is possible for a downstream 8b/10b decoder to decode an invalid control word into a valid dx.y code without asserting code error flags. 1 r crr r r v c 1 tx_datain = 8'h38 + tx_ctrl = 1'b1) can be encoded to 10'b0110001100 (0 18c), which is equivalent to a d24.6+ (8'hd8 from the rd+ column). altera recommends that you do not assert tx_ctrlenable for unsupported 8-bit characters. reset condition the tx_digitalreset signal resets the 8b/10b encoder. during reset, running disparity and data registers are cleared. also, the 8b/10b encoder outputs a k28.5 pattern from the rd- column continuously until tx_digitalreset is de-asserted. the input data and control code from the core fabric is ignored during the reset state. once out of reset, the 8b/10b encoder starts with a negative disparity (rd-) and transmits three k28.5 code groups for synchronization before it starts encoding and transmitting the data on its output. 1 tx_digitalreset is asserted, the downstream 8b/10b decoder that receives the data might observe synchronization or disparity errors. figure 1?28 shows the reset behavior of the 8b/10b encoder. when in reset ( tx_digitalreset is high), a k28.5 (k28.5 10-bit code group from the rd-column) is sent continuously until tx_digitalreset is low. due to some pipelining of the transmitter channel pcs, some ?don?t cares? (10'hxxx) are sent before the three synchronizing k28.5 code groups. user data follows the third k28.5 code group. figure 1?27. control word and data word transmission clock tx_datain[7:0] tx_ctrlenable code group 83 78 bc bc 0f 00 bf 3c d3.4 d24.3 d28.5 k28.5 d15.0 d0.0 d31.5 d28.1 figure 1?28. 8b/10b encoder output during tx_digitalreset assertion clock tx_digitalreset dataout[9:0] k28.5- k28.5- k28.5- xxx ... k28.5- xxx k28.5- k28.5+ dx.y+
chapter 1: hardcopy iv gx transceiver architecture 1?43 transmitter channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 double-width mode in double-width mode, the 8b/10b encoder operates in a cascaded mode, as shown in figure 1?29 . the lsbyte of the input data is encoded and transmitted prior to the msbyte. figure 1?29. 8b/10b encoder in double-width mode from the byte serializer datain[15:8] control_code[1] tx_forcedisp[1] tx_dispval[1] to the serialize r dataout[19:10] 8b/10b encoder msb encoding lsb encoding dataout[9:0] datain[7:0] control_code[0] tx_forcedisp[0] tx_dispval[0]
1?44 chapter 1: hardcopy iv gx transceiver architecture transmitter channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation in double-width mode, the cascaded 8b/10b encoder generates two 10-bit code groups from two 8-bit data and their respective control code identifiers. figure 1?30 shows the conversion format. the lsb shown in figure 1?30 is transmitted first. control code encoding in double-width mode, the tx_ctrlenable[1:0] port is used to identify which 8-bit data is to be encoded as a control word. the lower bit, tx_ctrlenable[0] , is associated with the lsbyte; the upper bit, tx_ctrlenable[1] , is associated with the msbyte. when tx_ctrlenable is low, the byte at the tx_datain port of the transceiver is encoded as data (dx.y); otherwise, it is encoded as a control code (kx.y). figure 1?31 shows that only the lower byte of the tx_datain[15:0] port is encoded as a control code because tx_ctrlenable[0] is high in the second clock cycle. the 8b/10b encoder does not check to see if the code word entered is one of the 12 valid control code groups specified in the ieee 802.3 8b/10b encoder specification. if an invalid control code is entered, the resulting 10-bit code may be encoded as an invalid code (it does not map to a valid dx.y or kx.y code), or unintended valid dx.y code, depending on the value entered. figure 1?30. 8b/10b conversion format in double-width mode g' f' e' d' c' b' a' h' gf edcba h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lsb msb g' f' i' e' d' c' b' a' j'h' gf i edcba jh 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ctrl[1:0] parallel data cascaded 8b/10b conversion figure 1?31. encoded control word and data word transmission clock tx_datain[15:0] tx_ctrlenable[1:0] code group 8378 bcbc 0f00 bf3c 00 1 d3.4 d24.3 d28.5 k28.5 d15.0 d0.0 d31.5 d28.1
chapter 1: hardcopy iv gx transceiver architecture 1?45 transmitter channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 the following is an example of an invalid control word encoded into a valid dx.y code. with an encoding of an invalid code k24.1 ( tx_datain = 8'h38 + tx_ctrl = 1'b1), depending on the current running disparity, the k24.1 can be encoded to be 10'b0110001100 (0 18c), which is equivalent to a d24.6+ (8'hd8 from the rd+ column). an 8b/10b decoder can decode this and not assert a code error flag. 1 r rc v cr wr 1 cr tx_digitalreset signal resets the 8b/10b encoder. during reset, the running disparity and data registers are cleared. also, the 8b/10b encoder outputs a k28.5 pattern with proper disparity continuously until tx_digitalreset goes low. the inputs from the tx_datain and tx_ctrlenable ports are ignored during the reset state. after reset, the 8b/10b encoder starts the lsbyte with a negative disparity (rd-) and the msbyte with a positive disparity (rd+) and transmits six k28.5 code groups (three on the lsbyte and three on the msbyte encoder) for synchronizing before it starts encoding and transmitting data. 1 f tx_digitalreset signal is asserted, the downstream 8b/10b decoder receiving the data might get synchronization or disparity errors. figure 1?32 shows the reset behavior of the 8b/10b encoder. when in reset ( tx_digitalreset is high), a k28.5- is sent continuously until tx_digitalreset is low. due to pipelining of the tx channel, there will be some ?don?t cares? (10'hxxx) until the first k28.5 is sent ( figure 1?32 shows six ?don?t cares?, but the number of ?don?t cares? can vary). both the lsbyte and msbyte transmit three k28.5s before the data at the tx_datain port is encoded and sent out. controlling running disparity after power on or reset, the 8b/10b encoder has a negative disparity and chooses the 10-bit code from the rd- column (refer to the 8b/10b encoder specification for the rd+ and rd- column values). the altgx megawizard plug-in manager provides the tx_forcedisp and tx_dispval ports to control the running disparity of the output from the 8b/10b encoder. these ports are available only in basic single-width and basic double-width modes. figure 1?32. transmitted output data when tx_digitalreset is asserted clock tx_digitalreset dataout[19:10] dataout[9:0] k28.5- k28.5- k28.5- xxx xxx xxx k28.5+ k28.5+ k28.5+ dx.y+ k28.5- k28.5- k28.5- dx.y- xxx xxx xxx k28.5+ k28.5+ k28.5+
1?46 chapter 1: hardcopy iv gx transceiver architecture transmitter channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation a high value on the tx_forcedisp port is the control signal to the disparity value of the output data. the disparity value (rd+ or rd?) is indicated by the value on the tx_dispval port. if the tx_forcedisp port is low, tx_dispval is ignored and the current running disparity is not altered. forcing disparity can either maintain the current running disparity calculations if the forced disparity value (on the tx_dispval bit) happens to match the current running disparity, or flip the current running disparity calculations if it does not. if the forced disparity flips the current running disparity, the downstream 8b/10b decoder might detect a disparity error. table 1?8 shows the tx_forcedisp and tx_dispval port values. figure 1?33 shows the current running disparity being altered in basic single-width mode by forcing a positive disparity k28.5 when it was supposed to be a negative disparity k28.5. in this example, a series of k28.5 code groups are continuously being sent. the stream alternates between a positive running disparity (rd+) k28.5 and a negative running disparity (rd?) k28.5 to maintain a neutral overall disparity. the current running disparity at time n + 3 indicates that the k28.5 in time n + 4 should be encoded with a negative disparity. because tx_forcedisp is high at time n + 4, and tx_dispval is also high, the k28.5 at time n + 4 is encoded as a positive disparity code group. figure 1?34 shows the current running disparity being altered in basic double-width mode by forcing a positive disparity on a negative disparity k28.5. in this example, a series of k28.5 are continuously being sent. the stream alternates between a positive ending running disparity (rd+) k28.5 and a negative ending running disparity (rd?) k28.5 as governed by the 8b/10b encoder specification to maintain a neutral overall disparity. the current running disparity at the end of time n + 2 indicates that the tab le 1 ?8 . tx_forcedisp and tx_dispval port values tx_forcedisp tx_dispval disparity value 0 x current running disparity has no change 1 0 encoded data has positive disparity 1 1 encoded data has negative disparity figure 1?33. 8b/10b encoder force running disparity operation in single-width mode current running disparity clock tx_in[7:0] tx_forcedisp bc bc bc bc bc bc bc tx_ctrlenable bc dataout[9:0] 17c 283 17c 283 283 283 17c 17c rd- rd+ rd+ rd- rd+ rd- rd+ rd- n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 tx_dispval
chapter 1: hardcopy iv gx transceiver architecture 1?47 transmitter channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 k28.5 at the low byte position in time n + 4 should be encoded with a positive disparity. because tx_forcedisp is high at time n + 4, the low signal level of tx_dispval is used to convert the lower byte k28.5 to be encoded as a positive disparity code word. as the upper bit of tx_forcedisp is low at n + 4, the high byte k28.5 takes the current running disparity from the low byte. transmitter polarity inversion the positive and negative signals of a serial differential link might accidentally be swapped during board layout. solutions like a board re-spin or major updates to the logic in the core fabric can be expensive. the transmitter polarity inversion feature is provided to correct this situation. an optional tx_invpolarity port is available in all functional modes except (oif) cei phy to dynamically enable the transmitter polarity inversion feature. in single-width mode, a high value on the tx_invpolarity port inverts the polarity of every bit of the 8-bit or 10-bit input data word to the serializer in the transmitter datapath. in double-width mode, a high value on the tx_invpolarity port inverts the polarity of every bit of the 16-bit or 20-bit input data word to the serializer in the transmitter datapath. because inverting the polarity of each bit has the same effect as swapping the positive and negative signals of the differential link, correct data is seen by the receiver. tx_invpolarity is a dynamic signal and might cause initial disparity errors at the receiver of an 8b/10b encoded link. the downstream system must be able to tolerate these disparity errors. figure 1?34. 8b/10b encoder force current running disparity in double-width mode current running disparity clock bc bc bc bc bc bc bc bc tx_dataout[19:0] 17c 283 17c 283 283 283 17c 17c rd - rd + rd + rd - rd+ rd- rd+ rd- n 01 00 00 00 tx_datain[15:0] tx_ctrlenable[1:0] tx_forcedisp[1:0] tx_dispval[1:0] 11 n + 2 n + 4
1?48 chapter 1: hardcopy iv gx transceiver architecture transmitter channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation figure 1?35 shows the transmitter polarity inversion feature in a single-width 10-bit wide datapath configuration. figure 1?35. transmitter polarity inversion in single-width mode 0 1 1 1 0 0 0 1 0 0 1 0 0 0 1 1 1 0 1 1 output from transmitter pcs converted data output to the transmitter serializer tx _invpolarity = high lsb msb msb lsb
chapter 1: hardcopy iv gx transceiver architecture 1?49 transmitter channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?36 shows the transmitter polarity inversion in double-width mode. transmitter bit reversal by default, the hardcopy iv gx transmit bit order is lsbit to msbit. in single-width mode, the least significant bit of the 8- or 10-bit data word is transmitted first, followed by the most significant bit. in double-width mode, the least significant bit of the 16- or 20-bit data word is transmitted first, followed by the most significant bit. the transmitter bit reversal feature allows reversing the transmit bit order as msbit to lsbit before it is forwarded to the serializer. if you enable the transmitter bit reversal feature in basic single-width mode, the 8-bit d[7:0] or 10-bit d[9:0] data at the input of the serializer is rewired to d[0:7] or d[0:9] , respectively. if you enable the transmitter bit reversal feature in basic double-width mode, the 16-bit d[15:0] or 20-bit d[19:0] data at the input of the serializer is rewired to d[0:15] or d[0:19] , respectively. figure 1?36. transmitter polarity inversion in double-width mode 0 1 1 1 0 0 0 1 0 0 output from transmitter pcs converted data output to the transmitter serializer tx _invpolarity = high 1 0 0 0 1 1 0 1 1 1 0 0 0 1 0 0 1 0 0 0 1 1 1 0 1 1 1 0 1 1 lsb lsb msb msb
1?50 chapter 1: hardcopy iv gx transceiver architecture transmitter channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation figure 1?37 shows the transmitter bit reversal feature in basic single-width for a 10-bit wide datapath configuration. figure 1?37. transmitter bit reversal operation in basic single-width mode output from transmitter pcs converted data output to the transmitter serializer tx bit reversal option enabled in the altgx megawizard d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] d[0] d[1] d[2] d[3] d[4] d[5] d[6] d[7] d[8] d[9]
chapter 1: hardcopy iv gx transceiver architecture 1?51 transmitter channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?38 shows the transmitter bit reversal feature in basic double-width mode for a 20-bit wide datapath configuration. serializer the serializer converts the incoming low-speed parallel signal from the transceiver pcs to high-speed serial data and sends it to the transmitter buffer. the serializer supports an 8-bit or 10-bit serialization factor in single-width mode and a 16-bit or 20-bit serialization factor in double-width mode. the serializer block drives the serial data to the output buffer, as shown in figure 1?39 . the serializer block sends out the least significant bit of the input data. figure 1?40 shows the serial bit order of the serializer block output. in this example, a constant 8'h6a (01101010) value is serialized and the serial data is transmitted from lsbit to msbit. figure 1?38. transmitter bit reversal operation in basic double-width mode output from transmitter pcs converted data output to the transmitter serializer d[0] d[2] d[1] d[4] d[3] d[6] d[5] d[8] d[7] d[10] d[9] d[12] d[11] d[15] d[13] d[14] d[17] d[16] d[19] d[18] d[18] d[19] d[16] d[17] d[15] d[13] d[14] d[11] d[12] d[9] d[10] d[7] d[8] d[5] d[6] d[3] d[4] d[1] d[2] d[0] tx bit reversal option enabled in the altgx megawizard
1?52 chapter 1: hardcopy iv gx transceiver architecture transmitter channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation transmitter output buffer the hardcopy iv gx transmitter buffers support 1.4-v and 1.5-v pseudo current mode logic (pcml) and can drive 40 inches of fr4 trace across two connectors. you can set the transmitter buffer voltage levels (v cch ) through the altgx megawizard plug-in manager. with the 1.4 v and 1.5 v settings, you can run the transmitter channel from 600 mbps to 6.5 gbps and 600 mbps to 4.25 gbps, respectively. the figure 1?39. serializer block in 8-bit pcs-pma interface note to figure 1?39 : (1) the cmu0 clock divider of the master transceiver block provides the cl ocks. it is used only in bonded modes (for example, basic 8, pci express [pipe] 8 mode). figure 1?40. serializer bit order (note 1) note to figure 1?40 : (1) it is assumed that the input data to the serializer is 8 bits (channel width = 8 bits or 16 bits with the 8b/10b encoder disabled). d7 d6 d5 d4 d3 d2 d1 d0 8 d7 d6 d5 d4 d3 d2 d1 d0 to output buffer low-speed parallel clock high-speed serial clock parallel clock from local divider block parallel clock from cmu0 clock divider parallel clock from master transceiver block (1) serial clock from local divider block serial clock from cmu0 clock divider serial clock from master transceiver block (1) low-speed parallel clock 01101010 01 0 0 0 11 1 00000000 high-speed serial clock tx_datain[7..0] tx_dataout[0]
chapter 1: hardcopy iv gx transceiver architecture 1?53 transmitter channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 transmitter buffer power supply only provides voltage to the transmitter output buffers in the transceiver channels. the transmitter output buffer, shown in figure 1?41 , has additional circuitry to improve signal integrity, such as v od , programmable three-tap pre-emphasis circuit, internal termination circuitry, and receiver detect capability to support pci express (pipe) functional mode. programmable transmitter termination the hardcopy iv gx transmitter buffer includes programmable on-chip differential termination of 85, 100, 120, or 150 . 2 , , , . . , v od is a function of the transmitter termination value. for more information about resultant v od values, refer to ?programmable output differential voltage? on page 1?53 . you can disable oct and use external termination. if you select external termination, the transmitter common mode is tri-stated. you can set the transmitter termination in the altgx megawizard plug-in manager. you can also set the oct through the assignment editor. set the assignment shown in table 1?9 to the transmitter serial output pin. programmable output differential voltage the hardcopy iv gx device allows you to customize the differential output voltage to handle different trace lengths, various backplanes, and receiver requirements, as shown in figure 1?42 . you can change the v od values using the dynamic reconfiguration controller. set the v od value through the tx_vodctrl[2:0] port of the dynamic reconfiguration controller. for example, to set v od to a value of 3, set the tx_vodctrl[2:0] to 011 . figure 1?41. transmitter output buffer tab le 1 ?9 . hardcopy iv gx oct assignment settings assign to transmitter serial output data pin assignment name: output termination available values: oct 85 , oct 100 , oct 120 , oct 150 50 ?? , 60 , 75 transmitter output pins programmable pre-emphasis and v od +vtt- receiver detect 42.5, 50 ? , 60 , 75 42.5,
1?54 chapter 1: hardcopy iv gx transceiver architecture transmitter channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation table 1?10 shows the v od values for different termination resistor settings. programmable pre-emphasis the programmable pre-emphasis module in each transmit buffer boosts high frequencies in the transmit data signal, which might be attenuated in the transmission media. using pre-emphasis can maximize the data eye opening at the far-end receiver. the transmission line?s transfer function can be represented in the frequency domain as a low-pass filter. any frequency components below ?3db can pass through with minimal loss. frequency components greater than ?3db are attenuated. this variation in frequency response yields data-dependent jitter and other inter-symbol interference (isi) effects. by applying pre-emphasis, the high-frequency components are boosted; that is, pre-emphasized. pre-emphasis equalizes the frequency response at the receiver so the difference between the low-frequency and high-frequency components is reduced, which minimizes the isi effects from the transmission medium. pre-emphasis requirements increase as data rates through legacy backplanes increase. you set the pre-emphasis settings in the altgx megawizard plug-in manager. the hardcopy iv gx transceiver provides three pre-emphasis taps: pre-tap, 1st post-tap, and 2nd post-tap. the altgx megawizard plug-in manager provides options to select the different values on these three taps. the pre-tap sets the figure 1?42. v od (differential) signal level single-ended waveform differential waveform v a v b +v od +v od -v od v od (differential) 0-v differential +700 -700 - v od (differential) = v a ? v b table 1?10. programmable v od differential peak-to-peak (mv) (note 1) values shown in the altgx megawizard plug-in manager 85 100 120 150 unit 0 170 200 240 300 mv 1 340 400 480 600 mv 2 510 600 720 900 mv 3 595 700 840 1050 mv 4 680 800 960 1200 mv 5 765 900 1080 1350 mv 6 850 1000 1200 ? mv 7 1020 1200 ? ? mv note to tab l e 1 ?1 0 : (1) these values are preliminary.
chapter 1: hardcopy iv gx transceiver architecture 1?55 transmitter channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 pre-emphasis on the data bit before the transition. the 1st post-tap and 2nd post-tap sets the pre-emphasis on the transition bit and the successive bit, respectively. the pre-tap and 2nd post-tap also provide inversion control, shown by negative values on the corresponding tap settings in the altgx megawizard plug-in manager. the altgx megawizard plug-in manager only shows the valid pre-emphasis tap values for a selected v od and transmitter termination resistance setting. programmable transmitter output buffer power (vcch) the altgx megawizard plug-in manager provides an option to select v cch . 1 w r v fr 1 r 1 1 r r w 1 r r common mode voltage (vcm) settings hardcopy iv gx devices provide a vcm of 650 mv. link coupling a high-speed serial link can be ac-coupled or dc-coupled, depending on the serial protocol being implemented. ac-coupled links in an ac-coupled link, the ac-coupling capacitor blocks the transmitter dc common mode voltage. the on-chip or off-chip receiver termination and biasing circuitry automatically restores the selected common mode voltage. figure 1?43 shows an ac-coupled link. figure 1?43. ac-coupled link physical medium transmitter receiver tx v cm rx v cm tx termination rx termination ac coupling capacitor ac coupling capacitor physical medium
1?56 chapter 1: hardcopy iv gx transceiver architecture transmitter channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation the following protocols supported by hardcopy iv gx devices mandate ac-coupled links: dc-coupled links in a dc-coupled link, the transmitter dc common mode voltage is seen unblocked at the receiver buffer. the link common mode voltage depends on the transmitter common mode voltage and the receiver common mode voltage. the on-chip or off-chip receiver termination and biasing circuitry must ensure compatibility between the transmitter and the receiver common mode voltage. figure 1?44 shows a dc-coupled link. the hardcopy iv gx transmitter can be dc-coupled to a hardcopy iv gx receiver for the entire operating data rate range of hardcopy iv gx devices, from 600 mbps to 6.5 gbps. pci express (pipe) receiver detect the hardcopy iv gx transmitter buffer has a built-in receiver detection circuit for use in the pipe mode for gen1 and gen2 data rates. this circuit detects if there is a receiver downstream by sending out a pulse on the common mode of the transmitter and monitoring the reflection. this mode requires the transmitter buffer to be tri-stated (in electrical idle mode), oct utilization, and a 125 mhz fixedclk signal. you can enable this feature in pipe mode by setting the tx_forceelecidle and tx_detectrxloopback ports to 1'b1 . receiver detect circuitry is active only in the p1 power state. figure 1?44. dc-coupled link physical medium transmitter receiver tx v cm rx v cm tx termination rx termination physical medium
chapter 1: hardcopy iv gx transceiver architecture 1?57 transmitter local clock divider block ? june 2009 altera corporation hardcopy iv device handbook volume 3 f for more information about power states, refer to the pci express (pipe) 2.0 specification available from intel. in the p1 power state, the transmitter output buffer is tri-stated because the transmitter output buffer is in electrical idle. a high on the tx_detectrxloopback port triggers the receiver detect circuitry to alter the transmitter output buffer common mode voltage. the sudden change in common mode voltage effectively appears as a step voltage at the tri-stated transmitter buffer output. if a receiver (that complies with pipe input impedance requirements) is present at the far end, the time constant of the step voltage is higher. if a receiver is not present or is powered down, the time constant of the step voltage is lower. the receiver detect circuitry snoops the transmitter buffer output for the time constant of the step voltage to detect the presence of the receiver at the far end. a high pulse is driven on the pipephydonestatus port and 3'b011 is driven on the pipestatus port to indicate that a receiver has been detected. there is some latency after asserting the tx_detectrxloopback signal, before the receiver detection is indicated on the pipephydonestatus port. for the signal timing to perform the receiver detect operation, refer to figure 1?108 on page 1?132 . 1 the tx_forceelecidle port must be asserted at least 10 parallel clock cycles prior to the tx_detectrxloopback port to ensure that the transmitter buffer is tri-stated. pci express (pipe) electrical idle the hardcopy iv gx transmitter output buffer supports transmission of pipe electrical idle (or individual transmitter tri-state). this feature is only active in pipe mode. the tx_forceelecidle port puts the transmitter buffer in electrical idle mode. this port has a specific functionality in each power state. for the signal timing to perform the electrical idle transmission in pipe mode, refer to figure 1?107 on page 1?131 . for use of the tx_forceelecidle signal under different power states, refer to the pipe specification 2.0. transmitter local clock divider block each transmitter channel contains a local clock divider block. it receives the high-speed clock from the cmu0 pll or cmu1 pll and generates the high-speed serial clock for the serializer and the low-speed parallel clock for the transmitter pcs datapath. the low-speed parallel clock is also forwarded to the core fabric ( tx_clkout ). the local clock divider block allows each transmitter channel to run at /1, /2, or /4 of the cmu pll data rate. the local clock divider block is used only in non-bonded functional modes (for example, gige, sonet/sdh, and sdi mode).
1?58 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation figure 1?45 shows the transmitter local clock divider block. receiver channel datapath this section describes hardcopy iv gx receiver channel datapath architecture. the sub-blocks in the receiver datapath are described in order from the serial receiver input buffer to the receiver phase compensation fifo buffer at the core fabric-transceiver interface. figure 1?46 shows the receiver channel datapath in hardcopy iv gx devices. the receiver channel pma datapath consists of the following blocks: figure 1?45. transmitter local clock divider block 4, 5, 8, or 10 high-speed serial cloc k low-speed parallel clock cmu0 pll high-speed clock cmu1 pll high-speed clock 1, 2, or 4 n figure 1?46. receiver channel datapath receiver channel pcs receiver channel pma core fabric pci express hardip pipe interface rx phase compensation fifo byte ordering byte de- serializer 8b/10b decoder deskew fifo rate match fifo de- serializer cdr input reference clock serial input data rx_datain word aligner
chapter 1: hardcopy iv gx transceiver architecture 1?59 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 the receiver datapath is very flexible and allows multiple configurations, depending on the selected functional mode. you can configure the receiver datapath using the altgx megawizard plug-in manager. receiver input buffer the receiver input buffer receives serial data from the rx_datain port and feeds it to the cdr unit. in the reverse serial loopback (pre-cdr) configuration, it also feeds the received serial data to the transmitter output buffer. figure 1?47 shows the receiver input buffer. table 1?11 shows the electrical features supported by the receiver input buffer. the hardcopy iv gx receiver buffer supports the following features: figure 1?47. receiver input buffer rx vcm to cdr receiver input buffer signal detect from serial data input pins (rx_datain) 85/100/ 120/150- .2. table 1?11. electrical features supported by the receiver input buffer data rate (gbps) i/o standard differential on-chip termination with calibration ( ) common mode voltage (v) coupling 0.6 to 6.5 1.4 v pcml 85, 100, 120, 150 0.82 ac, dc 1.5 v pcml 85, 100, 120, 150 0.82 ac, dc 2.5 v pcml 85, 100, 120, 150 0.82 ac lvpecl 85, 100, 120, 150 0.82 ac lvds 85, 100, 120, 150 1.1 ac, dc
1?60 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation  signal threshold detection circuitry programmable differential on-chip termination the hardcopy iv gx receiver buffers support optional differential on-chip termination resistors of 85, 100, 120, and 150 . to select the desired receiver oct resistor, make the assignments shown in table 1?12 in the quartus ii software assignment editor. 1 the hardcopy iv gx receiver oct resistors have calibration support to compensate for process, voltage, and temperature variations. for more information about oct calibration support, refer to ?calibration blocks? on page 1?192 . programmable common mode voltage the hardcopy iv gx receiver buffers have on-chip biasing circuitry to establish the required common mode voltage at the receiver input. it supports common mode voltage settings of 0.82 v and 1.1 v that you can select in the altgx megawizard plug-in manager. you must select 0.82 v as the receiver buffer common mode voltage for the following receiver input buffer i/o standards:  1.4-v pcml  1.5-v pcml  2.5-v pcml  lv p e c l you must select 1.1 v as the receiver buffer common mode voltage for the lvds receiver input buffer i/o standard. 1 on-chip biasing circuitry is effective only if you select on-chip receiver termination . if you select external termination , you must implement off-chip biasing circuitry to establish the common mode voltage at the receiver input buffer. link coupling a high-speed serial link can either be ac-coupled or dc-coupled, depending on the serial protocol being implemented. most of the serial protocols require links to be ac-coupled, but protocols such as common electrical i/o (cei) optionally allow dc coupling. ac-coupled links in an ac-coupled link, the ac coupling capacitor blocks the transmitter dc common mode voltage. the on-chip or off-chip receiver termination and biasing circuitry automatically restores the selected common mode voltage. figure 1?48 shows an ac-coupled link. table 1?12. hardcopy iv gx receiver on-chip termination assignment settings assign to rx_datain (receiver input data pins) assignment name: input termination available values: oct 85 , oct 100 , oct 120 , oct 150 , off
chapter 1: hardcopy iv gx transceiver architecture 1?61 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 the following protocols supported by hardcopy iv gx devices mandate ac-coupled links: dc-coupled links in a dc-coupled link, the transmitter dc common mode voltage is seen unblocked at the receiver buffer. link common mode voltage depends on the transmitter common mode voltage and the receiver common mode voltage. the on-chip or off-chip receiver termination and biasing circuitry must ensure compatibility between the transmitter and the receiver common mode voltage. figure 1?49 shows a dc-coupled link. figure 1?48. ac-coupled link note to figure 1?48 : (1) the receiver termination and biasing can be on-chip or off-chip. physical medium transmitter receiver tx v cm rx v cm tx termination rx termination ac coupling capacitor ac coupling capacitor physical medium
1?62 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation you might choose to use the dc-coupled high-speed link for these functional modes only: figure 1?49. dc-coupled link note to figure 1?49 : (1) the receiver termination and biasing can be on-chip or off-chip. physical medium transmitter receiver tx v cm rx v cm tx termination rx termination physical medium
chapter 1: hardcopy iv gx transceiver architecture 1?63 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?50 shows a typical hardcopy iv gx transmitter (pcml) to hardcopy iv gx receiver (pcml) dc-coupled link. table 1?13 shows the allowed transmitter and receiver settings in a hardcopy iv gx transmitter (pcml) to hardcopy iv gx receiver (pcml) dc-coupled link. figure 1?50. hardcopy iv gx transmitter (pcml) to hardcopy iv gx receiver (pcml) note to figure 1?50 : (1) r s is the parasitic resistance present in the on-chip rx termination and biasing circuitry. physical medium hardcopy iv gx receiver tx v cm rx v cm v cch = 1.4 v/1.5 v hardcopy iv gx transmitter 42.5/50/60/75- tx termination  0.65 v 0.82 v r s 42.5/50/60/75- tx termination  42.5/50/60/75- rx termination  42.5/50/60/75- rx termination  physical medium (1) table 1?13. settings for a hardcopy iv gx transmitter (pcml) to hardcopy iv gx receiver (pcml) dc-coupled link transmitter (hardcopy iv gx) settings receiver (hardcopy iv gx) settings data rate vcch (1) tx vcm differential termination data rate rx vcm differential termination 600 - 6500 mbps 1.4 v/1.5 v 0.65 v 85/100/120/150-  600 - 6500 mbps 0.82 v 85/100/120/150-  note to tab l e 1 ?1 3 : (1) v cch = 1.5 v can support data rates from 600 mbps to 4250 mbps. v cch = 1.4 v can support data rates from 600 mbps to 6500 mbps.
1?64 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation figure 1?51 shows the stratix ii gx transmitter (pcml) to hardcopy iv gx receiver (pcml) coupled link. table 1?14 shows the allowed transmitter and receiver settings in a stratix ii gx to hardcopy iv gx dc-coupled link. figure 1?51. stratix ii gx transmitter (pcml) to hardcopy iv gx receiver (pcml) note to figure 1?51 : (1) r s is the parasitic resistance present in the on-chip rx termination and biasing circuitry. physical medium hardcopy iv gx receiver tx v cm rx v cm v cch = 1.2 v/1.5 v stratix ii gx transmitter 50/60/75- tx termination  50/60/75- tx termination  0.6 v/0.7 v 42.5/50/60/75- rx termination  0.82 v r s 42.5/50/60/75- rx termination  (1) physical medium table 1?14. settings for a stratix ii gx to hardcopy iv gx dc-coupled link transmitter (stratix ii gx) settings receiver (hardcopy iv gx) settings data rate vcch (1) tx vcm (1) differential termination data rate rx vcm differential te rmin ati on 600 - 6375 mbps 1.5 v (1.5 v pcml) 0.6 v/0.7 v 100/120/150  600 - 6375 mbps 0.82 v 100/120/150  note to tab l e 1 ?1 4 : (1) v cch = 1.5 v with tx vcm = 0.7 v can support data rates from 600 mbps to 3125 mbps. v cch = 1.5 v with tx vcm = 0.6 v can support data rates from 600 mbps to 6375 mbps.
chapter 1: hardcopy iv gx transceiver architecture 1?65 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?52 shows the hardcopy iv gx transmitter (pcml) to stratix ii gx receiver (pcml) dc-coupled link. table 1?15 shows the allowed transmitter and receiver settings in a hardcopy iv gx transmitter (pcml) to stratix ii gx receiver (pcml) dc-coupled link. figure 1?52. hardcopy iv gx transmitter (pcml) to stratix ii gx receiver (pcml) note to figure 1?52 : (1) r s is the parasitic resistance present in the on-chip rx termination and biasing circuitry. physical medium stratix ii gx receiver tx v cm rx v cm 50/60/75- rx termination  v cch = 1.4/1.5 v hardcopy iv gx transmitter 42.5/50/60/75- tx termination  0.65 v 50/60/75- rx termination  0.85 v r s 42.5/50/60/75- tx termination  physical medium (1) table 1?15. settings for a hardcopy iv gx to stratix ii gx dc-coupled link transmitter (hardcopy iv gx) settings receiver (stratix ii gx) settings data rate vcch (1) tx vcm differential termination data rate i/o standard rx vcm differential ter mi na tio n 600 - 6375 mbps 1.4/1.5 v 0.65 v 100/120/150  600 - 6375 mbps 1.4/1.5 v pcml 0.85 v 100/120/150  note to tab l e 1 ?1 5 : (1) v cch = 1.5 v can support data rates from 600 mbps to 4250 mbps. v cch = 1.4 v can support data rates from 600 mbps to 6375 mbps.
1?66 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation figure 1?53 shows the lvds transmitter to hardcopy iv gx receiver (pcml) coupled link. table 1?16 shows the allowed transmitter and receiver settings in a lvds transmitter to hardcopy iv gx receiver dc-coupled link. programmable equalization and dc gain the transfer function of the physical medium can be represented as a low-pass filter in the frequency domain. frequency components below ?3 db frequency pass through with minimal loss. frequency components greater than ?3 db frequency are attenuated as a function of frequency due to skin-effect and dielectric losses. this variation in frequency response yields data-dependent jitter and other isi effects, which can cause incorrect sampling of the input data. each hardcopy iv gx receiver buffer has independently programmable equalization circuitry that boosts the high-frequency gain of the incoming signal, thereby compensating for the low-pass filter effects of the physical medium. the amount of high-frequency gain required depends on the loss characteristics of the physical medium. the hardcopy iv gx equalization circuitry supports 16 equalization settings that provide up to 16 db of high-frequency boost. you can select the appropriate equalization setting in the altgx megawizard plug-in manager. figure 1?53. lvds transmitter to hardcopy iv gx receiver (pcml) note to figure 1?53 : (1) r s is the parasitic resistance present in the on-chip rx termination and biasing circuitry. table 1?16. settings for a lvds transmitter to hardcopy iv gx receiver dc-coupled link (note 1) receiver (hardcopy iv gx) settings rx vcm differential termination r s 1.1 v 100-  (2) notes to ta bl e 1? 16 : (1) when dc-coupling an lvds transmitter to the hardcopy iv gx receiver, use rx vcm = 1.1 v and series resistance value rs to verify compliance with the lvds specification. (2) pending characterization. physical medium (1) hardcopy iv gx receiver rx v cm lvds transmitter 50- rx termination  1.1 v r s 50- rx termination  physical medium
chapter 1: hardcopy iv gx transceiver architecture 1?67 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 the hardcopy iv gx receiver buffer also supports programmable dc gain circuitry. unlike equalization circuitry, dc gain circuitry provides equal boost to the incoming signal across the frequency spectrum. the receiver buffer supports dc gain settings of 0, 3, 6, 9, and 12 db. you can select the appropriate dc gain setting in the altgx megawizard plug-in manager. signal threshold detection circuitry in pci express (pipe) mode, you can enable the optional signal threshold detection circuitry by not selecting the force signal detection option in the altgx megawizard plug-in manager. if enabled, this option senses whether the signal level present at the receiver input buffer is above the signal detect threshold voltage that you specified in the what is the signal detect and signal loss threshold? option in the altgx megawizard plug-in manager. 1 rr c r v c w cc rr crcr r c crcr r r fr frc r c r rfrc r frc r f r c crcr v r rcvr ffr r c r r rc rw r c crcr r rc w f c force signal detection option in the altgx megawizard plug-in manager, rx_signaldetect is always asserted high, irrespective of the signal level on the receiver input buffer. the rx_signaldetect signal is also used by the lock-to-reference/lock-to-data (ltr/ltd) controller in the receiver cdr to switch between the ltr and ltd lock modes. when the signal threshold detection circuitry de-asserts the rx_signaldetect signal, the ltr/ltd controller switches the receiver cdr from ltd to ltr lock mode. for more information, refer to ?ltr/ltd controller? on page 1?71 . clock and data recovery unit each hardcopy iv gx receiver channel has an independent cdr unit to recover the clock from the incoming serial data stream. the high-speed and low-speed recovered clocks are used to clock the receiver pma and pcs blocks. figure 1?54 shows the cdr block diagram.
1?68 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation the cdr operates either in ltr mode or ltd mode. in ltr mode, the cdr tracks the input reference clock. in ltd mode, the cdr tracks the incoming serial data. after the receiver power up and reset cycle, the cdr must be kept in ltr mode until it locks to the input reference clock. once locked to the input reference clock, the cdr output clock is trained to the configured data rate. the cdr can now switch to ltd mode to recover the clock from incoming data. the ltr/ltd controller controls the switch between ltr and ltd modes. lock-to-reference mode in ltr mode, the phase frequency detector in the cdr tracks the receiver input reference clock, rx_cruclk. the pfd controls the charge pump that tunes the vco in the cdr. depending on the data rate and the selected input reference clock frequency, the quartus ii software automatically selects the appropriate /m and /l divider values such that the cdr output clock frequency is half the data rate. an active high, the rx_pll_locked status signal is asserted to indicate that the cdr has locked to phase and frequency of the receiver input reference clock. figure 1?55 shows active blocks when cdr is in ltr mode. 1 the phase detector (pd) is inactive in ltr mode. figure 1?54. clock and data recovery unit /2 clock and data recovery (cdr) unit up down up down rx_locktorefclk rx_locktodata signal detect rx_freqlocked rx_datain rx_cruclk ltr/ltd controller phase detector (pd) phase frequency detector (pfd) /1, /2, /4 /2 charge pump + loop filter v co /l /m rx_pll_locked low-speed recovered cloc k high-speed recovered cloc k
chapter 1: hardcopy iv gx transceiver architecture 1?69 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 you can drive the receiver input reference clock with the following clock sources: refclk0 and refclk1 ) of the associated transceiver block figure 1?55. cdr in lock-to-reference mode up down up down rx_locktorefclk rx_locktodata signal detect rx_freqlocked rx_cruclk ltr/ltd controller phase detector (pd) phase frequency detector (pfd) /1, /2, /4 /2 charge pump + loop filter v co /l /m rx_pll_locked low-speed recovered clock high-speed recovered clock active blocks inactive blocks rx_datain /2 pcie_gen2switch clock and data recover (cdr) unit table 1?17. cdr specifications in lock-to-reference mode parameter value input reference clock frequency 50 mhz to 637.5 mhz pfd input frequency 50 mhz to 325 mhz /m divider 4, 5, 8, 10, 16, 20, 25 /l divider 1, 2, 4, 8
1?70 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation lock-to-data mode the cdr must be in ltd mode to recover the clock from the incoming serial data during normal operation. in ltd mode, the phase detector (pd) in the cdr tracks the incoming serial data at the receiver buffer. depending on the phase difference between the incoming data and the cdr output clock, the pd controls the cdr charge pump that tunes the vco. figure 1?56 shows active blocks when the cdr is in lt d m o d e . 1 cv rx_pll_locked signal toggles randomly and has no significance in ltd mode. after switching to ltd mode, it can take a maximum of 1 ms for the cdr to get locked to the incoming data and produce a stable recovered clock. the actual lock time depends on the transition density of the incoming data and the ppm difference between the receiver input reference clock and the upstream transmitter reference clock. the receiver pcs logic must be held in reset until the cdr produces a stable recovered clock. pci express (pipe) clock switch circuitry the feedback path from the cdr vco to the pd has a /2 divider that is used in pipe mode configured at gen2 (5 gbps) data rate for the dynamic switch between gen1 (2.5 gbps) and gen2 (5 gbps) signaling rates. when the phy-mac layer instructs a gen2-to-gen1 signaling rateswitch, the /2 divider is enabled. when the phy-mac layer instructs a gen1-to-gen2 signaling rateswitch, the /2 divider is disabled. for more information about the pipe signaling rateswitch, refer to ?dynamic switch between gen1 (2.5 gbps) and gen2 (5 gbps) signaling rate? on page 1?138 . 1 vr rcvr w r fc figure 1?56. cdr in lock-to-data mode /2 up down up down rx_locktorefclk rx_locktodata signal detect rx_freqlocked rx_datain rx_cruclk ltr/ltd controller phase detector (pd) phase frequency detector (pfd) /1, /2, /4 /2 charge pump + loop filter v co /l /m rx_pll_locked low-speed recovered clock high-speed recovered clock active blocks inactive blocks pcie_gen2switch clock and data recovery (cdr) unit
chapter 1: hardcopy iv gx transceiver architecture 1?71 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 ltr/ltd cont roller the ltr/ltd controller controls whether the cdr is in ltr or ltd mode. you can configure the ltr/ltd controller either in automatic lock mode or manual lock mode. two optional input ports ( rx_locktorefclk and rx_locktodata ) allow you to configure the ltr/ltd controller in either automatic lock mode or manual lock mode. table 1?18 shows the relationship between these optional input ports and the ltr/ltd controller lock mode. 1 if you do not instantiate the optional rx_locktorefclk and rx_locktodata signals, the quartus ii software automatically configures the ltr/ltd controller in automatic lock mode. automatic lock mode in automatic lock mode, the ltr/ltd controller initially sets the cdr to lock to the input reference clock (ltr mode). after the cdr locks to the input reference clock, the ltr/ltd controller automatically sets it to lock to the incoming serial data (ltd mode) when the following three conditions are met: rx_freqlocked signal. in ltd mode, the cdr uses a phase detector to keep the recovered clock phase-matched to the data. if the cdr does not stay locked to data due to frequency drift or severe amplitude attenuation, the ltr/ltd controller switches the cdr back to ltr mode to lock to the input reference clock. in automatic lock mode, the ltr/ltd controller switches the cdr from ltd to ltr mode when the following conditions are met: rx_freqlocked signal . table 1?18. optional input ports and ltr/ltd controller lock mode rx_locktorefclk rx_locktodata ltr/ltd controller lock mode 1 0 manual ? ltr mode x 1 manual ? ltd mode 0 0 automatic lock mode
1?72 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation manual lock mode in automatic lock mode, the ltr/ltd controller relies on the ppm detector and the phase relationship detector to set the cdr in ltr or ltd mode. the ppm detector and phase relationship detector reaction times can be too long for some applications that require faster cdr lock time. you can manually control the cdr to reduce its lock time using the rx_locktorefclk and rx_locktodata ports. in manual lock mode, the ltr/ltd controller sets the cdr in ltr or ltd mode depending on the logic level on the rx_locktorefclk and rx_locktodata signals. when the rx_locktorefclk signal is asserted high, the ltr/ltd controller forces the cdr to lock to the reference clock. when the rx_locktodata signal is asserted high , it forces the cdr to lock to data. when both signals are asserted, the rx_locktodata signal takes precedence over the rx_locktorefclk signal, forcing the cdr to lock to data. when the rx_locktorefclk signal is asserted high, the rx_freqlocked signal does not have any significance and is always driven low, indicating that the cdr is in ltr mode. when the rx_locktodata signal is asserted high, the rx_freqlocked signal is always driven high, indicating that the cdr is in ltd mode. if both signals are de-asserted, the cdr is in automatic lock mode. 1 the altera-recommended transceiver reset sequence varies depending on the cdr lock mode. deserializer the deserializer block clocks in serial input data from the receiver buffer using the high-speed serial recovered clock and deserializes it using the low-speed parallel recovered clock. it forwards the deserialized data to the receiver pcs channel. in single-width mode, the deserializer supports 8-bit and 10-bit deserialization factors. in double-width mode, the deserializer supports 16-bit and 20-bit deserialization factors.
chapter 1: hardcopy iv gx transceiver architecture 1?73 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?57 shows the deserializer operation in single-width mode with a 10-bit deserialization factor. figure 1?58 shows the serial bit order of the deserializer block input and the parallel data output of the deserializer block in single-width mode with a 10-bit deserialization factor. the serial stream (0101111 100) is deserialized to a value 10'h17c. the serial data is assumed to be received lsb to msb. word aligner because the data is serialized before transmission and then deserialized at the receiver, it loses the word boundary of the upstream transmitter upon deserialization. the word aligner receives parallel data from the deserializer and restores the word boundary based on a pre-defined alignment pattern that must be received during link synchronization. serial protocols such as pci express (pipe), xaui, gigabit ethernet, serial rapidio, and sonet/sdh, specify a standard word alignment pattern. for proprietary protocols, the hardcopy iv gx transceiver architecture allows you to select a custom word alignment pattern specific to your implementation. figure 1?57. deserializer operation in single-width mode d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 10 high-speed serial recovered clock low-speed parallel recovered clock clock recovery unit received data to word aligner figure 1?58. deserializer bit order in single-width mode 0101111100 1010000011 0 1 1 1 1 1 0 1 0 1 1 0 0 0 0 0 1 0 1 0 low-speed parallel clock high-speed serial clock datain dataout
1?74 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation in addition to restoring the word boundary, the word aligner also implements the following features: word aligner in single-width mode in single-width mode, the pma-pcs interface is either 8 bit or 10 bit wide. in 8 bit wide pma-pcs interface modes, the word aligner receives 8 bit wide data from the deserializer. in 10 bit wide pma-pcs interface modes, the word aligner receives 10 bit wide data from the deserializer. depending on the configured functional mode, you can configure the word aligner in manual alignment mode, automatic synchronization state machine mode, or bit-slip mode. word aligner in single-width mode with 8-bit pma-pcs interface modes the following functional modes support the 8-bit pma-pcs interface: figure 1?59. word aligner in all supported configurations pma-pcs interface width single-width 8-bit wide 10-bit wide manual alignment (oc-12, oc-48, basic single-width) bit-slip (basic single-width) manual alignment (basic single-width) automatic synchronization state machine (pci express [pipe] xaui, gige, basic single-width, serial rapidio) bit-slip (basic single-width, sdi) double-width 16-bit wide 20-bit wide manual alignment (basic double-width, oc-96) bit-slip (basic double-width) manual alignment (basic double-width) bit-slip (basic double-width)
chapter 1: hardcopy iv gx transceiver architecture 1?75 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 table 1?19 shows the word aligner configurations allowed in functional modes with an 8-bit pma-pcs interface. manual alignment mode word aligner with 8-bit pma-pcs interface modes in manual alignment mode, the word aligner operation is controlled by the input signal rx_enapatternalign . the word aligner operation is edge-sensitive to the rx_enapatternalign signal. after de-assertion of rx_digitalreset, a rising edge on the rx_enapatternalign signal triggers the word aligner to look for the word alignment pattern in the received data stream. in sonet/sdh oc-12 and oc-48 modes, the word aligner looks for 16'hf628 (a1a2) or 32'hf6f62828 (a1a1a2a2), depending on whether the input signal rx_a1a2size is driven low or high, respectively. in basic single-width mode, the word aligner looks for the 16-bit word alignment pattern programmed in the altgx megawizard plug-in manager. the word aligner aligns the 8-bit word boundary to the first word alignment pattern received after the rising edge on the rx_enapatternalign signal. two status signals, rx_syncstatus and rx_patterndetect, with the same latency as the datapath, are forwarded to the core fabric to indicate word aligner status. on receiving the first word alignment pattern after the rising edge on the rx_enapatternalign signal, both the rx_syncstatus and rx_patterndetect signals are driven high for one parallel clock cycle synchronous to the msbyte of the word alignment pattern. any word alignment pattern received thereafter in the same word boundary causes only the rx_patterndetect signal to go high for one clock cycle. 1 r wr r rcr w wr r r rx_enapatternalign and re-assert it again to create a rising edge. after a rising edge on the rx_enapatternalign signal, if the word alignment pattern is found in a different word boundary, the word aligner re-synchronizes to the new word boundary and asserts the rx_syncstatus and rx_patterndetect signals for one parallel clock cycle. figure 1?60 shows word aligner behavior in sonet/sdh oc-12 functional mode. the lsbyte (8'hf6) and the msbyte (8'h28) of the 16-bit word alignment pattern are received in parallel clock cycles n and n + 1, respectively. the rx_syncstatus and rx_patterndetect signals are both driven high for one parallel clock cycle synchronous to the msbyte (8'h28) of the word alignment pattern. after initial word alignment, the 16-bit word alignment pattern is again received across the word boundary in clock cycles m, m + 1, and m + 2. the word aligner does not re-align to the new word boundary because of the lack of a preceding rising edge on the table 1?19. word aligner configurations with an 8-bit pma-pcs interface functional mode allowed word configurations allowed word alignment pattern length sonet/sdh oc-12 manual alignment 16 bits sonet/sdh oc-48 manual alignment 16 bits basic single-width manual alignment, bit-slip 16 bits
1?76 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation rx_enapatternalign signal. if you create a rising edge on the rx_enapatternalign signal before the word alignment pattern is received across clock cycles m, m + 1, and m + 2, the word aligner re-aligns to the new word boundary, causing both the rx_syncstatus and rx_patterndetect signals to go high for one parallel clock cycle. bit-slip mode word aligner with 8-bit pma-pcs interface modes basic single-width mode with 8-bit pma-pcs interface width allows the word aligner to be configured in bit-slip mode. the word aligner operation is controlled by the input signal rx_bitslip in bit-slip mode. at every rising edge of the rx_bitslip signal, the bit-slip circuitry slips one bit into the received data stream, effectively shifting the word boundary by one bit. in bit-slip mode, the word aligner status signal rx_patterndetect is driven high for one parallel clock cycle when the received data after bit-slipping matches the 16-bit word alignment pattern programmed in the altgx megawizard plug-in manager. you can implement a bit-slip controller in the core fabric that monitors either the rx_dataout signal and/or the rx_patterndetect signal and controls the rx_bitslip signal to achieve word alignment. figure 1?61 shows an example of the word aligner configured in bit-slip mode. for this example, consider that 8'b11110000 is received back-to-back and 16'b0000 111100011110 is specified as the word alignment pattern. a rising edge on the rx_bitslip signal at time n + 1 slips a single bit 0 at the msb position, forcing the rx_dataout to 8'b01111000. another rising edge on the rx_bitslip signal at time n + 5 forces rx_dataout to 8'b00111100. another rising edge on the rx_bitslip signal at time n + 9 forces rx_dataout to 8'b00011110. another rising edge on the rx_bitslip signal at time n + 13 forces the rx_dataout to 8'b00001111. at this instance, rx_dataout in cycles n + 12 and n + 13 is 8'b00011110 and 8'b0000 1111, respectively, which matches the specified 16-bit alignment pattern 16'b0000 111100011110. this results in the assertion of the rx_patterndetect signal. figure 1?60. bit-slip mode in 8-bit pma-pcs interface mode 11110110 00101000 10001111 28 rx_dataout[7:0] rx_enapatternalign rx_patterndetect rx_syncstatus 0110xxxx xxxx0010 f6 6x 8f x2 n n + 1 m m + 1 m + 2
chapter 1: hardcopy iv gx transceiver architecture 1?77 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 word aligner in single-width mode with 10-bit pma-pcs interface modes the following functional modes support the 10-bit pma-pcs interface: pci express (pipe) gen1 and gen2 serial rapidio xaui gige sdi basic single-width mode this section describes the following word aligner 10-bit pma-pcs interface modes: automatic synchronization state machine mode with 10-bit pma-pcs interface mode manual alignment mode with 10-bit pma-pcs interface mode bit-slip mode in 10-bit pma-pcs interface mode table 1?20 shows the word aligner configurations allowed in functional modes with a 10-bit pma-pcs interface. figure 1?61. word aligner configured in bit-slip mode 01111000 n 11110000 00111100 00011110 00001111 rx_clkout rx_datain rx_dataout[7:0] rx_bitslip rx_patterndetect 11110000 n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 n + 11 n + 12 n + 13 n + 14 table 1?20. word aligner configurations with a 10-bit pma-pcs interface functional mode allowed word aligner configurations allowed word alignment pattern length pci express (pipe) automatic synchronization state machine 10 bits serial rapidio automatic synchronization state machine 10 bits xaui automatic synchronization state machine 7 bits, 10 bits gige automatic synchronization state machine 7 bits, 10 bits sdi bit-slip n/a basic single-width mode manual alignment, automatic synchronization state machine, bit-slip 7 bits, 10 bits
1?78 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation automatic synchronization state machine mode word aligner with 10-bit pma-pcs interface mode protocols such as pci express (pipe), xaui, gigabit ethernet, and serial rapidio require the receiver pcs logic to implement a synchronization state machine to provide hysteresis during link synchronization. each of these protocols defines a specific number of synchronization code groups that the link must receive to acquire synchronization and a specific number of erroneous code groups that it must receive to fall out of synchronization. in pipe, xaui, gigabit ethernet, and serial rapidio functional modes, the quartus ii software configures the word aligner in automatic synchronization state machine mode. it automatically selects the word alignment pattern length and pattern as specified by each protocol. in each of these functional modes, the protocol-compliant synchronization state machine is implemented in the word aligner. in basic single-width functional mode with 10-bit pma-pcs interface, you can configure the word aligner in automatic synchronization state machine mode by selecting the use the built-in synchronization state machine option in the altgx megawizard plug-in manager. it also allows you to program a custom 7-bit or 10-bit word alignment pattern that the word aligner uses for synchronization. 1 the 10-bit input data to the word aligner configured in automatic synchronization state machine mode must be 8b/10b encoded. table 1?21 shows the synchronization state machine parameters that the quartus ii software allows in supported functional modes. the synchronization state machine parameters are fixed for pipe, xaui, gige, and serial rapidio modes as specified by the respective protocol. for basic single-width mode, you can program these parameters as suited to your proprietary protocol implementation. after de-assertion of the rx_digitalreset signal in automatic synchronization state machine mode, the word aligner starts looking for the word alignment pattern or synchronization code groups in the received data stream. when the programmed number of valid synchronization code groups or ordered sets is received, the rx_syncstatus signal is driven high to indicate that synchronization is acquired. the rx_syncstatus signal is constantly driven high until the programmed number of erroneous code groups is received without receiving intermediate good groups; after which the rx_syncstatus is driven low. the word aligner indicates loss of synchronization ( rx_syncstatus remains low) until the programmed number of valid synchronization code groups are received again. table 1?21. synchronization state machine functional modes functional mode pci express (pipe) xaui gige serial rapidio basic single-width mode number of valid synchronization code groups or ordered sets received to achieve synchronization 4 4 3 127 1 to 256 number of erroneous code groups received to lose synchronization 17 4 4 3 1 to 64 number of continuous good code groups received to reduce the error count by one 16 4 4 255 1 to 256
chapter 1: hardcopy iv gx transceiver architecture 1?79 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 manual alignment mode word aligner with 10-bit pma-pcs interface mode in basic single-width mode with a 10-bit pma-pcs interface, you can configure the word aligner in manual alignment mode by selecting the use manual word alignment mode option in the altgx megawizard plug-in manager. in manual alignment mode, the word aligner operation is controlled by the input signal rx_enapatternalign . the word aligner operation is level-sensitive to the rx_enapatternalign signal. if the rx_enapatternalign signal is held high, the word aligner looks for the programmed 7-bit or 10-bit word alignment pattern in the received data stream. it updates the word boundary if it finds the word alignment pattern in a new word boundary. if the rx_enapatternalign signal is de-asserted low, the word aligner maintains the current word boundary even when it sees the word alignment pattern in a new word boundary. two status signals, rx_syncstatus and rx_patterndetect, with the same latency as the datapath, are forwarded to the core fabric to indicate the word aligner status. after receiving the first word alignment pattern after the rx_enapatternalign signal is asserted high, both the rx_syncstatus and rx_patterndetect signals are driven high for one parallel clock cycle. any word alignment pattern received thereafter in the same word boundary causes only the rx_patterndetect signal to go high for one clock cycle. any word alignment pattern received thereafter in a different word boundary causes the word aligner to re-align to the new word boundary only if the rx_enapatternalign signal is held high. the word aligner asserts the rx_syncstatus signal for one parallel clock cycle whenever it re-aligns to the new word boundary. figure 1?62 shows the manual alignment mode word aligner operation with 10-bit pma-pcs interface mode. in this example, a /k28.5/ (10'b010 1111 100) is specified as the word alignment pattern. the word aligner aligns to the /k28.5/ alignment pattern in cycle n because the rx_enapatternalign signal is asserted high. the rx_syncstatus signal goes high for one clock cycle, indicating alignment to a new word boundary. the rx_patterndetect signal also goes high for one clock cycle to indicate initial word alignment. at time n + 1, the rx_enapatternalign signal is de-asserted to instruct the word aligner to lock the current word boundary. the alignment pattern is detected again in a new word boundary across cycles n + 2 and n + 3. the word aligner does not align to this new word boundary because the rx_enapatternalign signal is held low. the /k28.5/ word alignment pattern is detected again in the current word boundary during cycle n + 5, causing the rx_patterndetect signal to go high for one parallel clock cycle. figure 1?62. word aligner with 10-bit pma-pcs manual alignment mode rx_clkout rx_enapatternalign rx_patterndetect rx_syncstatus rx_dataout[10..0] 111110000 0101111100 111110000 111110000 1000000101 0101111100 1111001010 n n + 1 n + 2 n + 3 n + 4 n + 5
1?80 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation 1 if the word alignment pattern is known to be unique and does not appear between word boundaries, you can constantly hold the rx_enapatternalign signal high because there is no possibility of false word alignment. if there is a possibility of the word alignment pattern occurring across word boundaries, you must control the rx_enapatternalign signal to lock the word boundary after the desired word alignment is achieved to avoid re-alignment to an incorrect word boundary. bit-slip mode word aligner with 10-bit pma-pcs interface mode in some basic single-width configurations with a 10-bit pma-pcs interface, you can configure the word aligner in bit-slip mode by selecting the use manual bit slipping mode option in the altgx megawizard plug-in manager. the word aligner operation for basic single-width with a 10-bit pma-pcs interface is similar to the word aligner operation in basic single-width mode with 8-bit pma-pcs interface. for word aligner operation in bit-slip mode, refer to ?manual alignment mode word aligner with 8-bit pma-pcs interface modes? on page 1?75 . the only difference is that the bit-slip word aligner with 10-bit pma-pcs interface modes allow 7-bit and 10-bit word alignment patterns, whereas 8-bit pma-pcs interface modes allow only 16-bit word alignment patterns. word aligner in double-width mode in double-width mode, the pma-pcs interface is either 16 bit or 20 bit wide. in 16-bit pma-pcs interface modes, the word aligner receives 16-bit wide data from the deserializer. in 20-bit pma-pcs interface modes, the word aligner receives 10 bit wide data from the deserializer. depending on the configured functional mode, you can configure the word aligner in manual alignment mode or bit-slip mode. the automatic synchronization state machine mode is not supported for word aligner in double-width mode. word aligner in double-width mode with 16-bit pma-pcs interface modes the following functional modes support the 16-bit pma-pcs interface: sonet/sdh oc-96 (oif) cei phy interface basic double-width table 1?22 shows the word aligner configurations allowed in functional modes with 16-bit pma-pcs interface. table 1?22. word aligner configurations with a 16-bit wide pma-pcs interface (note 1) functional mode allowed word aligner configurations allowed word alignment pattern length sonet/sdh oc-96 manual alignment 16 bits, 32 bits basic double-width manual alignment, bit-slip 8 bits, 16 bits, 32 bits note to tab l e 1 ?2 2 : (1) the word aligner is bypassed in (oif) cei phy interface mode.
chapter 1: hardcopy iv gx transceiver architecture 1?81 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 manual alignment mode word aligner with 16-bit pma-pcs interface modes in manual alignment mode, the word aligner starts looking for the programmed 8-bit, 16-bit, or 32-bit word alignment pattern in the received data stream as soon as rx_digitalreset is de-asserted low. it aligns to the first word alignment pattern received regardless of the logic level driven on the rx_enapatternalign signal. any word alignment pattern received thereafter in a different word boundary does not cause the word aligner to re-align to this new word boundary. after the initial word alignment following de-assertion of the rx_digitalreset signal, if a word re-alignment is required, you must use the rx_enapatternalign signal. word aligner operation is controlled by the input signal rx_enapatternalign and is edge-sensitive to the rx_enapatternalign signal. a rising edge on the rx_enapatternalign signal triggers the word aligner to look for the word alignment pattern in the received data stream. the word aligner aligns the 16-bit word boundary to the first word alignment pattern received after the rising edge on the rx_enapatternalign signal. any word alignment pattern received thereafter in a different word boundary does not cause the word aligner to re-align to this new word boundary. if another word re-alignment is required, you must de-assert and re-assert the rx_enapatternalign signal to create a rising edge on this signal. two status signals, rx_syncstatus and rx_patterndetect , with the same latency as the datapath, are forwarded to the core fabric to indicate word aligner status. after receiving the first word alignment pattern, the rx_patterndetect signal is driven high for one parallel clock cycle synchronous to the data that matches the msbyte of the word alignment pattern. any word alignment pattern received thereafter in the same word boundary causes rx_patterndetect to go high for one parallel clock cycle. after receiving the first word alignment pattern, the rx_syncstatus signal is constantly driven high until the word aligner sees another rising edge on the rx_enapatternalign signal. the rising edge on the rx_enapatternalign signal re-triggers the word alignment operation. figure 1?63 shows the manual alignment mode word aligner operation in 16-bit pma-pcs interface mode. in this example, a 16'hf628 is specified as the word alignment pattern. the word aligner aligns to the 16'hf628 pattern received in cycle n after de-assertion of rx_digitalreset . the rx_patterndetect[1] signal is driven high for one parallel clock cycle. the rx_syncstatus[1] signal is driven high constantly until cycle n + 2, after which it is driven low because of the rising edge on the rx_enapatternalign signal that re-triggers the word aligner operation. the word aligner receives the word alignment pattern again in cycle n + 4, causing the rx_patterndetect[1] signal to be driven high for one parallel clock cycle and the rx_syncstatus[1] signal to be driven high constantly.
1?82 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation bit-slip mode word aligner with 16-bit pma-pcs interface modes in some basic double-width configurations with a 16-bit pma-pcs interface, you can configure the word aligner in bit-slip mode by selecting the use manual bit slipping mode option in the altgx megawizard plug-in manager. the word aligner operation for basic double-width with a 16-bit pma-pcs interface is similar to the word aligner operation in basic single-width mode with an 8-bit pma-pcs interface. for word aligner operation in bit-slip mode, refer to ?word aligner in single-width mode with 8-bit pma-pcs interface modes? on page 1?74 . the only difference is that the bit-slip word aligner in 16-bit pma-pcs interface modes allows 8-bit and 16-bit word alignment patterns, whereas the bit-slip word aligner in 8-bit pma-pcs interface modes allows only a 16-bit word alignment pattern. word aligner in double-width mode with 20-bit pma-pcs interface modes a 20-bit pma-pcs interface is supported only in basic double-width mode. table 1?23 shows the word aligner configurations allowed in functional modes with a 20-bit pma-pcs interface. manual alignment mode word aligner with 20-bit pma-pcs interface modes the word aligner operation in basic double-width mode with a 20-bit pma-pcs interface is similar to the word aligner operation in basic double-width mode with a 16-bit pma-pcs interface. for word aligner operation in manual alignment mode, refer to ?word aligner in double-width mode with 16-bit pma-pcs interface modes? on page 1?80 . the only difference is that the manual alignment mode word aligner in 20-bit pma-pcs interface modes allows 7-, 10-, and 20-bit word alignment patterns, whereas the manual alignment mode word aligner in 16-bit pma-pcs interface modes allows only 8-, 16-, and 32-bit word alignment patterns. figure 1?63. manual alignment mode word aligner with 16-bit pma-pcs interface modes xxxx f628 xxxx xxxx xxxx f628 xxxx xxxx 00 10 00 11 10 11 00 10 10 00 00 n n + 1 n + 2 n + 3 n + 4 rx_dataout rx_digitalreset rx_enapatternalign rx_syncstatus[1:0] rx_patterndetect[1:0] table 1?23. word aligner in 20-bit pma-pcs interface modes functional mode allowed word aligner configurations allowed word alignment pattern length basic double-width manual alignment, bit-slip 7 bits, 10 bits, 20 bits
chapter 1: hardcopy iv gx transceiver architecture 1?83 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 bit-slip mode word aligner with 20-bit pma-pcs interface modes in some basic single-width configurations with 20-bit pma-pcs interfaces, you can configure the word aligner in bit-slip mode by selecting the use manual bit slipping mode option in the altgx megawizard plug-in manager. the word aligner operation for basic double-width with a 20-bit pma-pcs interface is similar to the word aligner operation in basic single-width mode with an 8-bit pma-pcs interface. for word aligner operation in bit-slip mode, refer to ?word aligner in single-width mode with 8-bit pma-pcs interface modes? on page 1?74 . the only difference is that the bit-slip word aligner in 20-bit pma-pcs interface modes allows only 7-, 10-, and 20-bit word alignment patterns, whereas the bit-slip word aligner in 8-bit pma-pcs interface modes allows only a 16-bit word alignment pattern.
1?84 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation table 1?24 summarizes the word aligner options available in basic single-width and double-width modes. table 1?24. word aligner options available in basic single-width and double-width modes (note 1) (part 1 of 2) functional mode pma-pcs interface width word alignment mode word alignment pattern length rx_enapatternalign sensitivity rx_syncstatus behavior rx_patterndetect behavior basic single-width 8 bit manual alignment 16 bit rising edge sensitive asserted high for one parallel clock cycle when the word aligner aligns to a new word boundary. asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary. bit-slip 16 bit ? ? asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary. 10 bit manual alignment 7 and 10-bit level sensitive asserted high for one parallel clock cycle when the word aligner aligns to a new word boundary. asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary. bit slip 7 and 10-bit ? ? asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary. automatic synchronization state machine 7 and 10-bit ? stays high as long as the synchronization conditions are satisfied. asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary.
chapter 1: hardcopy iv gx transceiver architecture 1?85 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 programmable run length violation detection the programmable run length violation circuit resides in the word aligner block and detects consecutive 1s or 0s in the data. if the data stream exceeds the preset maximum number of consecutive 1s or 0s, the violation is signified by the assertion of the rx_rlv signal. basic double-width 16 bit manual alignment 8, 16, and 32-bit rising edge sensitive stays high after the word aligner aligns to the word alignment pattern. goes low on receiving a rising edge on rx_enapatte rnalign until a new word alignment pattern is received. asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary. bit slip 8, 16, and 32-bit ?? asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary. 20 bit manual alignment 7, 10, and 20-bit rising edge sensitive stays high after the word aligner aligns to the word alignment pattern. goes low on receiving a rising edge on rx_enapatte rnalign until a new word alignment pattern is received. asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary. bit slip 7, 10, and 20-bit ?? asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary. note to tab l e 1 ?2 4 : (1) for more information about word aligner operation, refer to ?word aligner in single-width mode? on page 1?74 and ?word aligner in double-width mode? on page 1?80 . table 1?24. word aligner options available in basic single-width and double-width modes (note 1) (part 2 of 2) functional mode pma-pcs interface width word alignment mode word alignment pattern length rx_enapatternalign sensitivity rx_syncstatus behavior rx_patterndetect behavior
1?86 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation the run length violation status signal on the rx_rlv port has lower latency when compared with the parallel data on the rx_dataout port. the rx_rlv signal in each channel is clocked by its parallel recovered clock. the core fabric clock might have a phase difference and/or ppm difference (in asynchronous systems) with respect to the recovered clock. to ensure that the core fabric clock can latch the rx_rlv signal reliably, the run length violation circuitry asserts the rx_rlv signal for a minimum of two recovered clock cycles in single-width modes and a minimum of three recovered clock cycles in double-width modes. the rx_rlv signal can be asserted longer, depending on the run length of the received data. in single-width mode, the run length violation circuit detects up to a run length of 128 (for an 8-bit deserialization factor) or 160 (for a 10-bit deserialization factor). the settings are in increments of four or five for the 8-bit or 10-bit deserialization factors, respectively. in double-width mode, the run length violation circuit maximum run length detection is 512 (with a run length increment of eight) and 640 (with a run length increment of 10) for the 16-bit and 20-bit deserialization factors, respectively. table 1?25 summarizes the detection capabilities of the run length violation circuit. receiver polarity inversion the positive and negative signals of a serial differential link are often erroneously swapped during board layout. solutions like board re-spin or major updates to the pld logic can be expensive. the receiver polarity inversion feature is provided to correct this situation. an optional rx_invpolarity port is available in all single-width and double-width modes except (oif) cei phy and pci express (pipe modes) to dynamically enable the receiver polarity inversion feature. in single-width modes, a high value on the rx_invpolarity port inverts the polarity of every bit of the 8-bit or 10-bit input data word to the word aligner in the receiver datapath. in double-width modes, a high value on the rx_invpolarity port inverts the polarity of every bit of the 16-bit or 20-bit input data word to the word aligner in the receiver datapath. because inverting the polarity of each bit has the same effect as swapping the positive and negative signals of the differential link, correct data is seen by the receiver. rx_invpolarity is a dynamic signal and can cause initial disparity errors in an 8b/10b encoded link. the downstream system must be able to tolerate these disparity errors. table 1?25. detection capabilities of the run length violation circuit mode pma-pcs interface width run length violation detector range minimum maximum single-width mode 8-bit 4 128 10-bit 5 160 double-width mode 16-bit 8 512 20-bit 10 640
chapter 1: hardcopy iv gx transceiver architecture 1?87 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 the generic receiver polarity inversion feature is different from the pci express (pipe) 8b/10b polarity inversion feature. the generic receiver polarity inversion feature inverts the polarity of the data bits at the input of the word aligner and is not available in pipe mode. the pipe 8b/10b polarity inversion feature inverts the polarity of the data bits at the input of the 8b/10b decoder and is available only in pipe mode. figure 1?64 shows the receiver polarity inversion feature in single-width 10 bit wide datapath configurations. figure 1?64. receiver polarity inversion in single-width mode 0 1 0 1 1 1 1 1 0 0 1 0 1 0 0 0 0 0 1 1 output from deserializer input to word aligner to word aligner rx _ invpolarity = high
1?88 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation figure 1?65 shows the receiver polarity inversion feature in double-width 20 bit wide datapath configurations. receiver bit reversal by default, the hardcopy iv gx receiver assumes a lsbit-to-msbit transmission. if the transmission order is msbit-to-lsbit, the receiver forwards the bit-flipped version of the parallel data to the core fabric on the rx_dataout port. the receiver bit reversal feature is available to correct this situation. the receiver bit reversal feature is available through the rx_revbitordwa port only in basic single-width and double-width modes with the word aligner configured in bit-slip mode. when the rx_revbitordwa signal is driven high in basic single-width mode, the 8-bit or 10-bit data d[7:0] or d[9:0] at the output of the word aligner gets rewired to d[0:7] or d[0:9] , respectively. figure 1?65. receiver polarity inversion in double-width mode 1 0 1 0 0 0 0 0 1 1 output from deserializer input to word aligner 0 1 0 1 1 1 1 1 0 0 1 0 1 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 0 rx_invpolarity = high to word aligner
chapter 1: hardcopy iv gx transceiver architecture 1?89 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 when the rx_revbitordwa signal is driven high in basic double-width mode, the 16-bit or 20-bit data d[15:0] or d[19:0] at the output of the word aligner gets rewired to d[0:15] or d[0:19] , respectively. flipping the parallel data using this feature allows the receiver to forward the correct bit-ordered data to the core fabric on the rx_dataout port in the case of msbit-to-lsbit transmission. figure 1?66 shows the receiver bit reversal feature in basic single-width 10 bit wide datapath configurations. figure 1?66. receiver bit reversal in single-width mode d [ 9 ] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] d[0] d[1] d[2] d[3] d[4] d[5] d[6] d[7] d[8] d[9] output of word aligner before rx bit reversal output of word aligner after rx bit reversal rx_revbitordwa = high
1?90 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation figure 1?67 shows the receiver bit reversal feature in basic double-width 20-bit wide datapath configurations. receiver byte reversal in basic double-width modes the msbyte and lsbyte of the input data to the transmitter may be erroneously swapped. the receiver byte reversal feature is available to correct this situation. an optional port, rx_revbyteordwa , is available only in basic double-width mode to enable receiver byte reversal. in 8b/10b enabled mode, a high value on rx_revbyteordwa exchanges the 10-bit msbyte for the lsbyte of the 20-bit word at the output of the word aligner in the receiver datapath. in non-8b/10b enabled mode, a high value on rx_revbyteordwa exchanges the 8-bit msbyte for the lsbyte of the 16-bit word at the output of the word aligner in the receiver datapath. this compensates for the erroneous exchanging at the transmitter and corrects the data received by the downstream systems. rx_revbyteorderwa is a dynamic signal and can cause an initial disparity error at the receiver of an 8b/10b encoded link. the downstream system must be able to tolerate this disparity error. figure 1?67. receiver bit reversal in double-width mode to serializer d[0] d[2] d[1] d[4] d[3] d[6] d[5] d[8] d[7] d[10] d[9] d[12] d[11] d[15] d[13] d[14] d[17] d[16] d[19] d[18] d[18] d[19] d[16] d[17] d[15] d[13] d[14] d[11] d[12] d[9] d[10] d[7] d[8] d[5] d[6] d[3] d[4] d[1] d[2] d[0] output of word aligner before rx bit reversal output of word aligner after rx bit reversal rx_revbitordwa = high
chapter 1: hardcopy iv gx transceiver architecture 1?91 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?68 shows the receiver byte reversal feature. deskew fifo code groups received across four lanes in a xaui link can be misaligned with respect to one another because of skew in the physical medium or differences between the independent clock recoveries per lane. the xaui protocol allows a maximum skew of 40 ui (12.8 ns) as seen at the receiver of the four lanes. xaui protocol requires the physical layer device to implement a deskew circuitry to align all four channels. to enable the deskew circuitry at the receiver to align the four channels, the transmitter sends a /a/ (/k28.3/) code group simultaneously on all four channels during inter-packet gap (ipg). the skew introduced in the physical medium and the receiver channels can cause the /a/ code groups to be received misaligned. deskew circuitry performs the deskew operation in xaui functional mode. deskew circuitry consists of: cmu0 channel of the transceiver block that controls the deskew fifo write and read operations in each channel 1 deskew circuitry is only available in xaui mode. figure 1?68. receiver byte reversal feature 01 00 03 02 05 04 07 06 09 08 0b 0a msbyte lsbyte xx xx xx xx 07 06 09 08 0b 0a msbyte lsbyte 00 01 02 03 04 05 06 07 08 09 0a 0b msbyte lsbyte data to be transmitted input data to transmitter rx_revbyteordwa word aligner output with rx_revbyteordwa asserted
1?92 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation the deskew fifo in each channel receives data from its word aligner. the deskew operation begins only after link synchronization is achieved on all four channels as indicated by a high level on the rx_syncstatus signal from the word aligner in each channel. until the first /a/ code group is received, the deskew fifo read and write pointers in each channel are not incremented. after the first /a/ code group is received, the write pointer starts incrementing for each word received but the read pointer is frozen. if the /a/ code group is received on each of the four channels within 10 recovered clock cycles of each other, the read pointer for all four deskew fifos is released simultaneously, aligning all four channels. figure 1?69 shows lane skew at the receiver input and how the deskew fifo uses the /a/ code group to align the channels. after alignment of the first ||a|| column, if three additional aligned ||a|| columns are observed at the output of the deskew fifos of the four channels, the rx_channelaligned signal is asserted high, indicating channel alignment is acquired. after acquiring channel alignment, if four misaligned ||a|| columns are seen at the output of the deskew fifos in all four channels with no aligned ||a|| columns in between, the rx_channelaligned signal is de-asserted low, indicating loss of channel alignment. figure 1?69. deskew fifo?lane skew at the receiver input lanes are deskewed by lining up the "align"/a/, code groups lane skew at receiver input a lane 0 k k r a k r r k k k rr lane 1 k k r a k r r k k k rr lane 0 k k r k r r k k k rr lane 1 k k r a k r r k k k rr lane 2 k k r a k r r k k k rr lane 3 k k r a k r r k k k rr lane 2 k k r a k r r k k k rr lane 3 k k r a k r r k k k rr
chapter 1: hardcopy iv gx transceiver architecture 1?93 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 the deskew operation in xaui functional mode is compliant to the pcs deskew state machine diagram specified in clause 48 of ieee p802.3ae, as shown in figure 1?70 . rate match (clock rate compensation) fifo in asynchronous systems, the upstream transmitter and local receiver can be clocked with independent reference clocks. frequency differences in the order of a few hundred ppm can corrupt the data when latching from the recovered clock domain (the same clock domain as the upstream transmitter reference clock) to the local receiver reference clock domain. the rate match fifo compensates for small clock frequency differences between the upstream transmitter and the local receiver clocks by inserting or removing skp symbols or ordered sets from the ipg or idle streams. it deletes skp symbols or ordered sets when the upstream transmitter reference clock frequency is higher than the local receiver reference clock frequency. it inserts skp symbols or ordered-sets when the local receiver reference clock frequency is higher than the upstream transmitter reference clock frequency. figure 1?70. deskew fifo operation in xaui functional mode (note 1) note to figure 1?70 : (1) this figure is from ieee p802.3ae. reset + (sync_status=fail * sudi) sync_status ok * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) sudi(![/||a||/]) sudi(![/||a||/]) sudi(![/||a||/]) deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi sudi(![/||a||/]) loss_of_alignment align_status ? ? ? 2 ? 2 2 4 2
1?94 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation the rate match fifo consists of a 20-word deep fifo and necessary logic that controls insertion and deletion of a skip character or ordered set, depending on the ppm difference. the rate match fifo is mandatory and cannot be bypassed in the following functional modes: rx_rmfifodatainserted ?indicates insertion of a skip character or ordered set rx_rmfifodatadeleted ?indicates deletion of a skip character or ordered set rx_rmfifofull ?indicates rate match fifo full condition rx_rmfifoempty ?indicates rate match fifo empty condition 1 the rate match fifo status signals are not available in pipe mode. these signals are encoded on the pipestatus[2:0] signal in pipe mode as specified in the pipe specification. rate match fifo in pci express (pipe) mode in pipe mode, the rate match fifo is capable of compensating up to 300 ppm (total 600 ppm) difference between the upstream transmitter and the local receiver. the pipe protocol requires the transmitter to send skp ordered sets during ipgs, adhering to rules listed in the base specification. the skp ordered set is defined as a /k28.5/ com symbol followed by three consecutive /k28.0/ skp symbols groups. the pipe protocol requires the receiver to recognize a skp ordered set as a /k28.5/ com symbol followed by one to five consecutive /k28.0/ skp symbols. the rate match fifo operation is compliant to pipe base specification 2.0. the rate match operation begins after the synchronization state machine in the word aligner indicates synchronization is acquired by driving the rx_syncstatus signal high. the rate match fifo looks for the skp ordered set and deletes or inserts skp symbols as necessary to prevent the rate match fifo from overflowing or under-running. the rate match fifo inserts or deletes only one skp symbol per skp ordered set received. the rate match fifo insertion and deletion events are communicated to the core fabric on the pipestatus[2:0] port from each channel. the pipestatus[2:0] signal is driven to 3'b001 for one clock cycle synchronous to the /k28.5/ com symbol of the skp ordered set in which the /k28.0/ skp symbol is inserted. the pipestatus[2:0] signal is driven to 3'b010 for one clock cycle synchronous to the /k28.5/ com symbol of the skp ordered set from which the /k28.0/ skp symbol is deleted.
chapter 1: hardcopy iv gx transceiver architecture 1?95 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?71 shows an example of rate match deletion in the case where two /k28.0/ skp symbols are required to be deleted. only one /k28.0/ skp symbol is deleted per skp ordered set received. figure 1?72 shows an example of rate match insertion in the case where two skp symbols are required to be inserted. only one /k28.0/ skp symbol is inserted per skp ordered set received. the rate match fifo full and empty conditions are communicated to the core fabric on the pipestatus[2:0] port from each channel. the rate match fifo in pipe mode automatically deletes the data byte that causes the fifo to go full and drives pipestatus[2:0] = 3'b101 synchronous to the subsequent data byte. figure 1?73 shows the rate match fifo full condition in pipe mode. the rate match fifo becomes full after receiving data byte d4. the rate match fifo automatically inserts /k30.7/ (9'h1fe) after the data byte that causes the fifo to go empty and drives pci express (pipe)status[2:0] = 3?b110 flag synchronous to the inserted /k30.7/ (9'h1fe). figure 1?71. rate match deletion in pci express (pipe) mode datain dataout pipestatus[2:0] first skip ordered set k28.5 k28.0 k28.0 dx.y k28.5 k28.0 dx.y k28.5 k28.5 k28.0 k28.0 k28.0 k28.0 second skip ordered set skip symbol deleted 3'b010 xxx xxx xxx 3'b010 xxx figure 1?72. rate match insertion in pci express (pipe) mode datain dataout pipestatus[2:0] first skip ordered set k28.0 k28.0 dx.y k28.5 k28.5 k28.0 k28.0 k28.0 second skip ordered set skip symbol inserted k28.5 k28.0 dx.y k28.5 k28.0 k28.0 k28.0 k28.0 k28.0 k28.0 xxx xxx 3'b001 xxx xxx 3'b001 xxx xxx xxx xxx figure 1?73. rate match fifo full condition in pci express (pipe) mode d1 d2 d1 d2 d7 datain dataout d4 d4 d5 d6 d7 d8 d3 d3 d6 xx d8 xx xx xxx xxx xxx 3'b101 xxx xxx xxx xxx pipestatus[2:0]
1?96 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation figure 1?74 shows rate match fifo empty condition in pci express (pipe) mode. the rate match fifo becomes empty after reading out data byte d3. 1 c cfr r c w c r ff enable rate match fifo option in the altgx megawizard plug-in manager. rate match fifo in xaui mode in xaui mode, the rate match fifo is capable of compensating for up to 100 ppm (200 ppm total) difference between the upstream transmitter and the local receiver reference clock. the xaui protocol requires the transmitter to send /r/ (/k28.0/) code groups simultaneously on all four lanes (denoted as ||r|| column) during inter-packet gaps, adhering to rules listed in the ieee p802.3ae specification. the rate match fifo operation in xaui mode is compliant to the ieee p 802.3ae specification. the rate match operation begins after:  the synchronization state machine in the word aligner of all four channels indicates synchronization was acquired by driving its rx_syncstatus signal high  the deskew fifo block indicates alignment was acquired by driving the rx_channelaligned signal high the rate match fifo looks for the ||r|| column (simultaneous /r/ code group on all four channels) and deletes or inserts the ||r|| column to prevent the rate match fifo from overflowing or under-running. it can insert or delete as many ||r|| columns as necessary to perform the rate match operation. two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted , that indicate rate match fifo deletion and insertion events, respectively, are forwarded to the core fabric. if an ||r|| column is deleted, the rx_rmfifodeleted flag from each of the four channels goes high for one clock cycle per deleted ||r|| column. if an ||r|| column is inserted, the rx_rmfifoinserted flag from each of the four channels goes high for one clock cycle per inserted ||r|| column. figure 1?74. rate match fifo empty condition in pci express (pipe) mode d1 d2 d1 d2 d5 datain dataout /k30.7/ d4 d5 d6 d3 d3 d4 pipestatus[2:0] 3'b110 xxx xxx xxx xxx xxx
chapter 1: hardcopy iv gx transceiver architecture 1?97 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?75 shows an example of rate match deletion in the case where three ||r|| columns must be deleted. figure 1?76 shows an example of rate match insertion in the case where two ||r|| columns are required to be inserted. two flags, rx_rmfifofull and rx_rmfifoempty , are forwarded to the core fabric to indicate rate match fifo full and empty conditions. figure 1?75. rate match deletion in xaui mode datain[3] rx_rmfifodatadeleted k28.0 k28.3 k28.5 k28.5 k28.0 k28.0 k28.0 k28.5 first ||r|| column second ||r|| column third ||r|| column fourth ||r|| column k28.5 datain[2] k28.0 k28.3 k28.5 k28.5 k28.0 k28.0 k28.0 k28.5 k28.5 datain[1] k28.0 k28.3 k28.5 k28.5 k28.0 k28.0 k28.0 k28.5 k28.5 datain[0] k28.0 k28.3 k28.5 k28.5 k28.0 k28.0 k28.0 k28.5 k28.5 dataout[3] k28.5 k28.3 k28.5 k28.0 k28.5 k28.5 dataout[2] k28.5 k28.3 k28.5 k28.0 k28.5 k28.5 dataout[1] k28.5 k28.3 k28.5 k28.0 k28.5 k28.5 dataout[0] k28.5 k28.3 k28.5 k28.0 k28.5 k28.5 figure 1?76. rate match insertion in xaui mode dataout[3] rx_rmfifodatainserted k28.0 k28.3 k28.5 k28.0 k28.0 k28.5 k28.0 first ||r|| column second ||r|| column k28.5 dataout[2] k28.0 k28.3 k28.5 k28.0 k28.0 k28.5 k28.0 k28.5 dataout[1] k28.0 k28.3 k28.5 k28.0 k28.0 k28.5 k28.0 k28.5 dataout[0] k28.0 k28.3 k28.5 k28.0 k28.0 k28.5 k28.0 k28.5 datain[3] k28.0 k28.3 k28.5 k28.5 k28.0 k28.5 datain[2] k28.0 k28.3 k28.5 k28.5 k28.0 k28.5 datain[1] k28.0 k28.3 k28.5 k28.5 k28.0 k28.5 datain[0] k28.0 k28.3 k28.5 k28.5 k28.0 k28.5
1?98 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation in xaui mode, the rate match fifo does not automatically insert or delete code groups to overcome fifo empty and full conditions, respectively. it asserts the rx_rmfifofull and rx_rmfifoempty flags for at least three recovered clock cycles to indicate rate match fifo full and empty conditions, respectively. 1 c f r c f c r rx_digitalreset signal to reset the receiver pcs blocks. rate match fifo in gige mode in gige mode, the rate match fifo is capable of compensating for up to 100 ppm (200 ppm total) difference between the upstream transmitter and the local receiver reference clock. the gige protocol requires the transmitter to send idle ordered sets /i1/ (/k28.5/d5.6/) and /i2/ (/k28.5/d16.2/) during inter-packet gaps, adhering to rules listed in the ieee 802.3 specification. the rate match operation begins after the synchronization state machine in the word aligner indicates synchronization is acquired by driving the rx_syncstatus signal high. the rate match fifo is capable of deleting or inserting the /i2/ (/k28.5/d16.2/) ordered set to prevent the rate match fifo from overflowing or under-running during normal packet transmission. the rate match fifo is also capable of deleting or inserting the first two bytes of the /c2/ ordered set (/k28.5/d2.2/dx.y/dx.y/) to prevent the rate match fifo from overflowing or under-running during the auto negotiation phase. the rate match fifo can insert or delete as many /i2/ or /c2/ (first two bytes) as necessary to perform the rate match operation. two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted , that indicate rate match fifo deletion and insertion events, respectively, are forwarded to the core fabric. both the rx_rmfifodatadeleted and rx_rmfifodatainserted flags are asserted for two clock cycles for each deleted and inserted /i2/ ordered set, respectively. figure 1?77 shows an example of rate match fifo deletion in the case where three symbols are required to be deleted. because the rate match fifo can only delete /i2/ ordered set, it deletes two /i2/ ordered sets (four symbols deleted). figure 1?78 shows an example of rate match fifo insertion in the case where one symbol is required to be inserted. because the rate match fifo can only delete /i2/ ordered set, it inserts one /i2/ ordered sets (two symbols inserted). figure 1?77. rate match deletion in gige mode datain dataout rx_rmfifodatadeleted first /i2/ ordered set dx.y k28.5 k28.5 second /i2/ ordered set /i2/ ordered set deleted d16.2 d16.2 k28.5 d16.2 dx.y third /i2/ ordered set dx.y k28.5 d16.2 dx.y
chapter 1: hardcopy iv gx transceiver architecture 1?99 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 two flags, rx_rmfifofull and rx_rmfifoempty , are forwarded to the core fabric to indicate rate match fifo full and empty conditions. in gige mode, the rate match fifo does not insert or delete code groups automatically to overcome fifo empty and full conditions, respectively. it asserts the rx_rmfifofull and rx_rmfifoempty flags for at least two recovered clock cycles to indicate rate match fifo full and empty conditions, respectively. 1 c f r c f c r rx_digitalreset signal to reset the receiver pcs blocks. rate match fifo in basic single-width mode in basic single-width mode, the rate match fifo is capable of compensating for up to 300 ppm (600 ppm total) difference between the upstream transmitter and the local receiver reference clock. 1 r c c w rcvr c v rr rcvr c c cvr rr r f r r 1 crcr c w w r c r rrr rc c c w r c r r r r r c r1 r c r f c f w rr r c r c f 1 r 1 cr r c 1 c r v r r r r c r fr wr r cr rx_syncstatus goes high. when the rate matcher receives either of the two 10-bit control patterns followed by the respective 10-bit skip pattern, it inserts or deletes the 10-bit skip pattern as necessary to avoid the rate match fifo from overflowing or under-running. the rate match fifo can delete a maximum of four skip patterns from a cluster, if there is one skip pattern left in the cluster after deletion. the rate match fifo can insert a maximum of four skip patterns in a cluster, if there are no more than five skip patterns in the cluster after insertion. two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted , indicating rate match fifo deletion and insertion events, respectively, are forwarded to the core fabric. figure 1?78. rate match insertion in gige mode datain dataout rx_rmfifodatainserted first /i2/ ordered set dx.y k28.5 k28.5 second /i2/ ordered set d16.2 d16.2 dx.y k28.5 d16.2 d16.2 dx.y k28.5 d16.2 k28.5
1?100 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation figure 1?79 shows an example of rate match fifo deletion in the case where three skip patterns are required to be deleted. in this example, /k28.5/ is the control pattern and neutral disparity /k28.0/ is the skip pattern. the first skip cluster has a /k28.5/ control pattern followed by two /k28.0/ skip patterns. the second skip cluster has a /k28.5/ control pattern followed by four /k28.0/ skip patterns. the rate match fifo deletes only one /k28.0/ skip pattern from the first skip cluster to maintain at least one skip pattern in the cluster after deletion. two /k28.0/ skip patterns are deleted from the second cluster for a total of three skip patterns deletion requirement. figure 1?80 shows an example of rate match fifo insertion in the case where three skip patterns are required to be inserted. in this example, /k28.5/ is the control pattern and neutral disparity /k28.0/ is the skip pattern. the first skip cluster has a /k28.5/ control pattern followed by three /k28.0/ skip patterns. the second skip cluster has a /k28.5/ control pattern followed by one /k28.0/ skip pattern. the rate match fifo inserts only two /k28.0/ skip patterns into the first skip cluster to maintain a maximum of five skip patterns in the cluster after insertion. one /k28.0/ skip pattern is inserted into the second cluster for a total of three skip patterns to meet the insertion requirement. two flags, rx_rmfifofull and rx_rmfifoempty , are forwarded to the core fabric to indicate rate match fifo full and empty conditions. the rate match fifo in basic single-width mode automatically deletes the data byte that causes the fifo to go full and asserts the rx_rmfifofull flag synchronous to the subsequent data byte. figure 1?79. rate match deletion in basic single-width mode datain dataout rx_rmfifodatadeleted first skip cluster k28.5 k28.5 second skip cluster three skip patterns deleted k28.0 k28.0 k28.0 k28.0 k28.0 k28.0 k28.5 k28.0 k28.5 k28.0 k28.0 k28.0 figure 1?80. rate match insertion in basic single-width mode datain dataout rx_rmfifoinserted first skip cluster k28.0 k28.5 second skip cluster three skip patterns inserted k28.0 k28.0 k28.5 k28.0 dx.y k28.5 k28.0 k28.0 k28.0 k28.0 k28.0 k28.0 k28.5 k28.0 dx.y k28.0 k28.0
chapter 1: hardcopy iv gx transceiver architecture 1?101 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?81 shows the rate match fifo full condition in basic single-width mode. the rate match fifo becomes full after receiving data byte d4. the rate match fifo automatically inserts /k30.7/ (9'h1fe) after the data byte that causes the fifo to go empty and asserts the rx_fifoempty flag synchronous to the inserted /k30.7/ (9'h1fe). figure 1?82 shows the rate match fifo empty condition in basic single-width mode. the rate match fifo becomes empty after reading out data byte d3. rate match fifo in basic double-width mode in basic double-width mode, the rate match fifo is capable of compensating up to 300 ppm (total 600 ppm total) difference between the upstream transmitter and the local receiver reference clock. 1 r c c w rcvr c v rr rcvr c c cvr rr r f r r 1 crcr c w w r c r rrr rc c c w r c r r r r r c r1 r c r f c f w rr r c r c f 1 r 1 cr r c 1 c r v r r r r c r fr wr r cr rx_syncstatus goes high. when the rate matcher receives either of the two 10-bit control patterns followed by the respective 10-bit skip pattern, it inserts or deletes a pair of 10-bit skip patterns as necessary to avoid the rate match fifo from overflowing or under-running. figure 1?81. rate match fifo full condition in basic single-width mode d1 d2 d1 d2 d7 datain dataout d4 d4 d5 d6 d7 d8 d3 d3 d6 rx_rmfifofull xx d8 xx xx figure 1?82. rate match fifo empty condition in basic single-width mode d1 d2 d1 d2 d5 datain dataout /k30.7/ d4 d5 d6 d3 d3 d4 rx_rmfifoempty
1?102 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation the rate match fifo can delete as many pairs of skip patterns from a cluster necessary to avoid the rate match fifo from overflowing. the rate match fifo can delete a pair of skip patterns only if the two 10-bit skip patterns appear in the same clock cycle on the lsbyte and msbyte of the 20-bit word. if the two skip patterns appear straddled on the msbyte of a clock cycle and the lsbyte of the next clock cycle, the rate match fifo cannot delete the pair of skip patterns. the rate match fifo can insert as many pairs of skip patterns into a cluster necessary to avoid the rate match fifo from under-running. the 10-bit skip pattern can appear on msbyte or lsbyte, or both, of the 20-bit word. two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted , indicating rate match fifo deletion and insertion events, respectively, are forwarded to the core fabric. figure 1?83 shows an example of rate match fifo deletion in the case where three skip patterns are required to be deleted. in this example, /k28.5/ is the control pattern and neutral disparity /k28.0/ is the skip pattern. the first skip cluster has a /k28.5/ control pattern in the lsbyte and /k28.0/ skip pattern in the msbyte of a clock cycle followed by one /k28.0/ skip pattern in the lsbyte of the next clock cycle. the rate match fifo cannot delete the two skip patterns in this skip cluster because they do not appear in the same clock cycle. the second skip cluster has a /k28.5/ control pattern in the msbyte of a clock cycle followed by two pairs of /k28.0/ skip patterns in the next two cycles. the rate match fifo deletes both pairs of /k28.0/ skip patterns (for a total of four skip patterns deleted) from the second skip cluster to meet the three skip pattern deletion requirement. figure 1?84 shows an example of rate match fifo insertion in the case where three skip patterns are required to be inserted. in this example, /k28.5/ is the control pattern and neutral disparity /k28.0/ is the skip pattern. the first skip cluster has a /k28.5/ control pattern in the lsbyte and /k28.0/ skip pattern in the msbyte of a clock cycle followed by one /k28.0/ skip pattern in the lsbyte of the next clock cycle. the rate match fifo inserts pairs of skip patterns in this skip cluster to meet the three skip pattern insertion requirement. figure 1?83. rate match deletion in basic double-width mode datain[19:10] rx_rmfifodatadeleted k28.5 k28.0 dx.y k28.0 k28.0 dx.y first skip cluster second skip cluster dx.y datain[9:0] dx.y k28.5 k28.0 k28.0 k28.0 dx.y dataout[19:0] k28.5 k28.0 dx.y dx.y dataout[9:0] dx.y k28.5 k28.0 dx.y dx.y dx.y dx.y two pairs of skip patterns deleted
chapter 1: hardcopy iv gx transceiver architecture 1?103 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 two flags, rx_rmfifofull and rx_rmfifoempty , are forwarded to the core fabric to indicate rate match fifo full and empty conditions. the rate match fifo in basic double-width mode automatically deletes the pair of data byte that causes the fifo to go full and asserts the rx_rmfifofull flag synchronous to the subsequent pair of data bytes. figure 1?85 shows the rate match fifo full condition in basic double-width mode. the rate match fifo becomes full after receiving the 20-bit word d5d6. the rate match fifo automatically inserts a pair of /k30.7/ ({9'h1fe,9'h1fe}) after the data byte that causes the fifo to go empty and asserts the rx_fifoempty flag synchronous to the inserted pair of /k30.7/ ({9'h1fe,9'h1fe}). figure 1?84. rate match insertion in basic double-width mode datain[19:10] rx_rmfifodatainserted k28.0 k28.0 k28.0 dx.y k28.5 k28.0 first skip cluster second skip cluster dx.y datain[9:0] k28.0 k28.5 k28.0 dx.y dx.y k28.0 dx.y dataout[19:0] k28.5 k28.0 dx.y k28.0 dataout[9:0] dx.y k28.5 dx.y k28.0 dx.y dx.y k28.0 k28.0 k28.0 k28.0 figure 1?85. rate match fifo full condition in basic double-width mode datain[19:10] datain[9:0] dataout[19:0] dataout[9:0] rx_rmfifofull d2 d4 d6 d8 d10 d12 d1 d3 d5 d7 d9 d11 d2 d4 d6 d10 d12 xx d1 d3 d5 d9 d11 xx
1?104 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation figure 1?86 shows the rate match fifo empty condition in basic double-width mode. the rate match fifo becomes empty after reading out the 20-bit word d5d6. 8b/10b decoder protocols such as pci express (pipe), xaui, gige, and serial rapidio require the serial data sent over the link to be 8b/10b encoded to maintain the dc balance in the serial data transmitted. these protocols require the receiver pcs logic to implement an 8b/10b decoder to decode the data before forwarding it to the upper layers for packet processing. the hardcopy iv gx receiver channel pcs datapath implements the 8b/10b decoder after the rate matcher. in functional modes with rate matcher enabled, the 8b/10b decoder receives data from the rate matcher. in functional modes with rate matcher disabled, the 8b/10b decoder receives data from the word aligner. the 8b/10b decoder operates in two modes: figure 1?86. rate match fifo empty condition in basic double-width mode datain[19:10] datain[9:0] dataout[19:0] dataout[9:0] rx_rmfifoempty d2 d4 d6 d8 d10 d12 d2 d4 d6 d8 d10 /k30.7/ /k30.7/ d1 d3 d5 d7 d9 d11 d1 d3 d5 d7 d9
chapter 1: hardcopy iv gx transceiver architecture 1?105 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 8b/10b decoder in single-width mode figure 1?87 shows the 8b/10b decoder in single-width mode. in single-width mode, the 8b/10b decoder receives 10-bit data from the rate matcher or word aligner (when rate matcher is disabled) and decodes it into an 8-bit data + 1-bit control identifier. the decoded data is fed to the byte deserializer or the receiver phase compensation fifo (if byte deserializer is disabled). 1 1 cr c cfc 1 cr r w fw fc figure 1?87. 8b/10b decoder in single-width mode 8b/10b decoder (lsbyte) 8b/10b decoder (msbyte) datain [19:10] recovered clock or tx_clkout[0] current running disparity rx_dataout [15:8] rx_ctrldetect[1] rx_errdetect[1] rx_disperr[1] datain[9:0] rx_dataout[7:0] rx_ctrldetect rx_errdetect rx_disperr recovered clock or tx_clkout[0]
1?106 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation control code group detection the 8b/10b decoder indicates whether the decoded 8-bit code group is a data or control code group on the rx_ctrldetect port. if the received 10-bit code group is one of the 12 control code groups (/kx.y/) specified in the ieee802.3 specification, the rx_ctrldetect signal is driven high. if the received 10-bit code group is a data code group (/dx.y/), the rx_ctrldetect signal is driven low. figure 1?89 shows the 8b/10b decoder decoding the received 10-bit /k28.5/ control code group into an 8-bit data code group (8'hbc) driven on the rx_dataout port. the rx_ctrldetect signal is asserted high synchronous with 8'hbc on the rx_dataout port, indicating that it is a control code group. the rest of the codes received are data code groups /dx.y/. figure 1?88. 8b/10b decoder in single-width mode 9876543210 8b/10b conversion jhgfiedcba msb received last lsb received first 76543210 hgfed cb a ctrl parallel data figure 1?89. 8b/10b decoder in control code group detection d3.4 d24.3 d28.5 k28.5 d15.0 d0.0 d31.5 clock rx_ctrldetect datain[9..0 ] rx_dataout[7..0] 83 78 bc bc 0f 00 bf
chapter 1: hardcopy iv gx transceiver architecture 1?107 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 8b/10b decoder in double-width mode figure 1?90 shows the 8b/10b decoder in double-width mode. in double-width mode, two 8b/10b decoders are cascaded for decoding the 20-bit encoded data, as shown in figure 1?91 . the 10-bit lsbyte of the received 20-bit encoded data is decoded first and the ending running disparity is forwarded to the 8b/10b decoder responsible for decoding the 10-bit msbyte. the cascaded 8b/10b decoder decodes the 20-bit encoded data into 16-bit data + 2-bit control identifier. the msb and lsb of the 2-bit control identifier corresponds to the msbyte and lsbyte of the 16-bit decoded data code group. the decoded data is fed to the byte deserializer or the receiver phase compensation fifo (if byte deserializer is disabled). 1 c f w cc 1 cr c cfc 1 cr r w c w fc c r 1 cr r rrr rc figure 1?90. 8b/10b decoder in double-width mode 8b/10b decoder (lsbyte) 8b/10b decoder (lsbyte) current running disparity datain[19:10] rx_dataout[15:8] rx_ctrldetect[1] rx_errdetect[1] rx_disperr[1] recovered clock or tx_clkout[0] datain[9:0] rx_dataout[7:0] rx_ctrldetect rx_errdetect rx_disperr recovered clock or tx_clkout[0]
1?108 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation figure 1?91 shows a 20-bit code group decoded into 16-bit data and 2-bit control identifier by the 8b/10b decoder in double-width mode. control code group detection the cascaded 8b/10b decoder indicates whether the decoded 16-bit code group is a data or control code group on the 2-bit rx_ctrldetect[1:0] port. the rx_ctrldetect[0] signal is driven high or low depending on whether decoded data on the rx_dataout[7:0] port (lsbyte) is a control or data code group, respectively. the rx_ctrldetect[1] signals are driven high or low depending on whether decoded data on the rx_dataout[15:8] port (msbyte) is a control or data code group, respectively. figure 1?92 shows the 8b/10b decoding of the received 10-bit /k28.5/ control code group into 8-bit data code group (8'hbc) driven on the rx_dataout port. the rx_ctrldetect signal is asserted high synchronous with 8'hbc on the rx_dataout port, indicating that it is a control code group. the rest of the codes received are data code groups /dx.y/. byte deserializer the core fabric-transceiver interface frequency has an upper limit of 250 mhz. in functional modes that have a receiver pcs frequency greater than 250 mhz, the parallel received data and status signals cannot be forwarded directly to the core fabric because it violates the upper limit of the 250 mhz core fabric-transceiver interface frequency. in such configurations, the byte deserializer is required to reduce the core fabric-transceiver interface frequency to half while doubling the parallel data figure 1?91. 8b/10 decoder in 20-bit double-width mode 19 18 17 16 15 14 13 12 11 10 cascaded 8b/10b conversion j 1 h 1 g 1 f 1 i 1 e 1 d 1 c 1 b 1 a 1 msb lsb 15 14 13 13 11 10 9 8 h 1 g 1 f 1 e 1 d 1 c 1 b 1 a 1 ctrl[1..0] 9876543210 jhgfiedcba 7 6543 21 0 hgfed cb a parallel data figure 1?92. 8b/10b decoder 10-bit control code group 00 01 00 clock datain[19:10] datain[9:0] rx_ctrldetect[1:0] rx_dataout[15:0] d3.4 d28.5 d15.0 d3.4 d28.5 d15.0 d3.4 d24.3 16'h8378 16'hbcbc 16'h0f0f 16'h8383
chapter 1: hardcopy iv gx transceiver architecture 1?109 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 width. for example, at 3.2 gbps data rate with a deserialization factor of 10, the receiver pcs datapath runs at 320 mhz. the 10-bit parallel received data and status signals at 320 mhz cannot be forwarded to the core fabric because it violates the upper limit of 250 mhz. the byte serializer converts the 10-bit parallel received data at 320 mhz into 20-bit parallel data at 160 mhz before forwarding to the core fabric. 1 rr rr cfr c cr frcrcvr rfc cc r frc cfr c cr frcrcvr rfc cc r frc rr r w byte deserializer in single-width mode in single-width mode, the byte deserializer receives 8 bit wide data from the 8b/10b decoder or 10 bit wide data from the word aligner (if the 8b/10b decoder is disabled) and deserializes it into 16 bit or 20 bit wide data at half the speed. figure 1?93 shows the byte deserializer in single-width mode. byte deserializer in double-width mode in double-width mode, the byte deserializer receives 16 bit wide data from the 8b/10b decoder or 20 bit wide data from the word aligner (if the 8b/10b decoder is disabled) and deserializes it into 32 bit or 40 bit wide data at half the speed. figure 1?93. byte deserializer in single-width mode or /2 byte deserializer receiver pcs clock dataout[15:0] dataout[19:0] d1 d2 d3 d4 d1 d2 d3 d4 or datain[7:0] datain[9:0]
1?110 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation figure 1?94 shows the byte deserializer in double-width mode. byte ordering block in single-width modes with the 16 bit or 20 bit core fabric-transceiver interface, the byte deserializer receives one data byte (8 or 10 bit) and deserializes it into two data bytes (16 or 20 bit). depending on when the receiver pcs logic comes out of reset, the byte ordering at the output of the byte deserializer may or may not match the original byte ordering of the transmitted data. the byte misalignment resulting from byte deserialization is unpredictable because it depends on which byte is being received by the byte deserializer when it comes out of reset. figure 1?95 shows a scenario in which the msbyte and lsbyte of the two-byte transmitter data appears straddled across two word boundaries after getting byte deserialized at the receiver. in double-width modes with the 32 bit or 40 bit core fabric-transceiver interface, the byte deserializer receives two data bytes (16 or 20 bit) and deserializes it into four data bytes (32 or 40 bit). figure 1?96 shows a scenario in which the two msbytes and lsbytes of the four-byte transmitter data appears straddled across two word boundaries after getting byte deserialized at the receiver. figure 1?94. byte deserializer in double-width mode or /2 receiver pcs clock byte deserializer dataout[31:0] dataout[39:0] d3d4 d7d8 d1d2 d5d6 d3d4 d1d2 d5d6 d7d8 or dataout[15:0] dataout[19:0] figure 1?95. msbyte and lsbyte of the two-bit transmitter data straddled across two word boundaries transmitter receiver tx_datain[15:8] (msbyte) tx_datain[7:0] (lsbyte) d2 d4 d6 d5 d3 d1 byte serializer xx d1 d2 d3 d4 d5 d6 xx byte deserializer d1 d3 d5 xx xx d2 d4 d6 rx_dataout[15:8] (msbyte) rx_dataout[7:0] (lsbyte)
chapter 1: hardcopy iv gx transceiver architecture 1?111 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 hardcopy iv gx transceivers have an optional byte ordering block in the receiver datapath that you can use to restore proper byte ordering before forwarding the data to the core fabric. the byte ordering block looks for the user-programmed byte ordering pattern in the byte-deserialized data. you must select a byte ordering pattern that you know appears at the lsbyte(s) position of the parallel transmitter data. if the byte ordering block finds the programmed byte ordering pattern in the msbyte(s) position of the byte-deserialized data, it inserts the appropriate number of user-programmed pad bytes to push the byte ordering pattern to the lsbyte(s) position, thereby restoring proper byte ordering. byte ordering block in single-width modes the byte ordering block is available in the following single-width functional modes: 1 r r fr cfr w rr c rcvr rfr c fr 11 r fwr c cfr rr r rr r fr fc r r fr rfr rr 11 c w c rr c rr r rr r r r 1 w rr r w c w figure 1?96. msbyte and lsbyte of the four-bit transmitter data straddled across two word boundaries transmitter receiver tx_datain[31:16] (msbytes) tx_datain[15:0] (lsbytes) d3d4 d1d2 d7d8 d5d6 byte serializer xx d1d2 d2d4 d5d6 d7d8 xx byte deserializer rx_dataout[31:16] (msbytes) rx_dataout[15:0] (lsbytes) d1d2 d5d6 xx xx d3d4 d7d8
1?112 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation byte ordering block in double-width modes the byte ordering block is available in the following double-width functional modes: 1 r r fr cfr w rr c rcvr rfr c fr 11 c w c rr c rr r rr r r r 1 w rr r w c w table 1?26. byte ordering pattern length in basic single-width mode functional mode byte ordering pattern length byte ordering pad pattern length basic single-width mode with: 16-bit core fabric-transceiver interface no 8b/10b decoder word aligner in manual alignment mode 8 bit 8 bit basic single-width mode with: 16-bit core fabric-transceiver interface 8b/10b decoder word aligner in automatic synchronization state machine mode 9 bit (1) 9 bit note to tab l e 1 ?2 6 : (1) if a /kx.y/ control code group is selected as the byte ordering pattern, the msb of the 9-bit byte ordering pattern must be 1'b1. if a /dx.y/ data code group is selected as the byte ordering pattern, the msb of the 9-bit byte ordering pattern must be 1'b0. the least significant 8 bits must be the 8b/10b decoded version of the code group used for byte ordering.
chapter 1: hardcopy iv gx transceiver architecture 1?113 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 the byte ordering block modes of operation in both single-width and double-width modes are: word-alignment-based byte ordering in word-alignment-based byte ordering, the byte ordering block starts looking for the byte ordering pattern in the byte-deserialized data every time it sees a rising edge on the rx_syncstatus signal. after a rising edge on the rx_syncstatus signal, if the byte ordering block finds the first data byte that matches the programmed byte ordering pattern in the msbyte position of the byte-deserialized data, it inserts one programmed pad pattern to push the byte ordering pattern in the lsbyte position. if the byte ordering block finds the first data byte that matches the programmed byte ordering pattern in the lsbyte position of the byte-deserialized data, it considers the data to be byte ordered and does not insert any pad pattern. in either case, the byte ordering block asserts the rx_byteorderalignstatus signal. 1 you can choose word-alignment-based byte ordering by selecting the sync status signal from the word aligner tab in the what do you want the byte ordering to be based on? field in the altgx megawizard plug-in manager. table 1?27. byte ordering pattern length in basic double-width mode functional mode byte ordering pattern length byte ordering pad pattern length basic double-width mode with: 32-bit core fabric-transceiver interface no 8b/10b decoder (16-bit pma-pcs interface) word aligner in manual alignment mode 16 bit, 8 bit 8 bit basic double-width mode with: 32-bit core fabric-transceiver interface 8b/10b decoder (20-bit pma-pcs interface) word aligner in manual alignment mode 18 bit, 9 bit (1) 9 bit basic double-width mode with: 40-bit core fabric-transceiver interface no 8b/10b decoder (20-bit pma-pcs interface) word aligner in manual alignment mode 20 bit, 10 bit 10 bit note to tab l e 1 ?2 7 : (1) the 18-bit byte ordering pattern d[17:0] consists of msbyte d[17:9] and lsbyte d[8:0] , d[17] corresponds to rx_ctrldetect[1] and d[16:9] corresponds to rx_dataout[15:8] . similarly, d[9] corresponds to rx_ctrldetect[0] and d[7:0] corresponds to rx_dataout[7:0] .
1?114 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation figure 1?97 shows an example of the byte ordering operation in single-width modes. in this example, a is the programmed byte ordering pattern and pad is the programmed pad pattern. the byte deserialized data places the byte ordering pattern a in the msbyte position, resulting in incorrect byte ordering. assuming that a rising edge on the rx_syncstatus signal had occurred before the byte ordering block sees the byte ordering pattern a in the msbyte position, the byte ordering block inserts a pad byte and pushes the byte ordering pattern a in the lsbyte position. the data at the output of the byte ordering block has correct byte ordering as reflected on the rx_byteorderalignstatus signal. if the byte ordering block sees another rising edge on the rx_syncstatus signal from the word aligner, it de-asserts the rx_byteorderalignstatus signal and repeats the byte ordering operation as previously described. user-controlled byte ordering unlike word-alignment-based byte ordering, user-controlled byte ordering provides control to the user logic to restore correct byte ordering at the receiver. when enabled, an rx_enabyteord port is available that you can use to trigger the byte ordering operation. a rising edge on the rx_enabyteord port triggers the byte ordering block. after a rising edge on the rx_enabyteord signal, if the byte ordering block finds the first data byte that matches the programmed byte ordering pattern in the msbyte position of the byte-deserialized data, it inserts one programmed pad pattern to push the byte ordering pattern in the lsbyte position. if the byte ordering blocks finds the first data byte that matches the programmed byte ordering pattern in the lsbyte position of the byte-deserialized data, it considers the data to be byte ordered and does not insert any pad byte. in either case, the byte ordering block asserts the rx_byteorderalignstatus signal. figure 1?97. byte ordering in single-width modes a transmitter receiver xx a xx pad a channel tx_datain[15:8] tx_datain[7:0] d2 d3 d5 d4 d1 byte serializer byte deserializer d1 d4 d3 d2 byte ordering rx_byteorderalignstatus d1 d3 d5 d4 d2 rx_dataout[15:8] rx_dataout[7:0]
chapter 1: hardcopy iv gx transceiver architecture 1?115 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?98 shows user-controlled byte ordering in basic double-width mode. receiver phase compensation fifo the receiver phase compensation fifo in each channel ensures reliable transfer of data and status signals between the receiver channel and the core fabric. the receiver phase compensation fifo compensates for the phase difference between the parallel receiver pcs clock (fifo write clock) and the core fabric clock (fifo read clock). the receiver phase compensation fifo operates in one of the following two modes: figure 1?98. user-controlled byte ordering in basic double-width mode transmitter receiver channel byte serializer byte deserializer byte ordering rx_enabyteord rx_byteorderalignstatus xxxx tx_datain[31:16] (msbyte) tx_datain[15:0] (lsbyte) d2d3 d4d5 d8d9 d0d1 b1b2 d6d7 b1b2 d8d9 d0d1 d2d3 d4d5 xxxx b1b2 d6d7 b1b2 d8d9 d0d1 p1p2 d4d5 xxxx d2d3 b1b2 d6d7 xxxx b1b2 rx_dataout [31:16] (msbyte) rx_dataout[15:0] (lsbyte) table 1?28. receiver phase compensation fifo write clock source (part 1 of 2) configuration receiver phase compensation fifo write clock without byte serializer with byte serializer non-bonded channel configuration with rate matcher parallel transmitter pcs clock from the local clock divider in the associated channel ( tx_clkout ) divide-by-two version of the parallel transmitter pcs clock from the local clock divider in the associated channel ( tx_clkout ) non-bonded channel configuration without rate matcher parallel recovered clock from the receiver pma in the associated channel ( rx_clkout ) divide-by-two version of the parallel recovered clock from the receiver pma in the associated channel ( rx_clkout )
1?116 chapter 1: hardcopy iv gx transceiver architecture receiver channel datapath hardcopy iv device handbook volume 3 ? june 2009 altera corporation the receiver phase compensation fifo read clock source varies depending on whether or not you instantiate the rx_coreclk port in the altgx megawizard plug-in manager. table 1?29 shows the receiver phase compensation fifo read clock source in different configurations. receiver phase compensation fifo error flag an optional rx_phase_comp_fifo_error port is available in all functional modes to indicate a receiver phase compensation fifo underrun or overflow condition. the rx_phase_comp_fifo_error signal is asserted high when the phase compensation fifo gets either full or empty. this feature is useful to verify a phase compensation fifo underrun or overflow condition as a probable cause of link errors. offset cancellation in the receiver buffer and receiver cdr as silicon progresses towards smaller process nodes, the performance of circuits at these smaller nodes depends more on process variations. these process variations result in analog voltages that can be offset from the required ranges. offset cancellation logic corrects these offsets. the receiver buffer and receiver cdr require offset cancellation. 4 bonded channel configuration parallel transmitter pcs clock from the central clock divider in the cmu0 of the associated transceiver block ( coreclkout ) divide-by-two version of the parallel transmitter pcs clock from the central clock divider in cmu0 of the associated transceiver block ( coreclkout ) 8 bonded channel configuration parallel transmitter pcs clock from the central clock divider in cmu0 of the master transceiver block ( coreclkout from master transceiver block) divide-by-two version of the parallel transmitter pcs clock from the central clock divider in cmu0 of the master transceiver block ( coreclkout from master transceiver block) table 1?28. receiver phase compensation fifo write clock source (part 2 of 2) configuration receiver phase compensation fifo write clock without byte serializer with byte serializer table 1?29. receiver phase compensation fifo read clock source configuration receiver phase compensation fifo read clock rx_coreclk port not instantiated rx_coreclk port instantiated (1) non-bonded channel configuration with rate matcher core fabric clock driven by the clock signal on the tx_clkout port core fabric clock driven by the clock signal on the rx_coreclk port non-bonded channel configuration without rate matcher core fabric clock driven by the clock signal on the rx_clkout port core fabric clock driven by the clock signal on the rx_coreclk port 4 bonded channel configuration core fabric clock driven by the clock signal on the coreclkout port core fabric clock driven by the clock signal on the rx_coreclk port 8 bonded channel configuration core fabric clock driven by the clock signal on the coreclkout port core fabric clock driven by the clock signal on the rx_coreclk port note to tab l e 1 ?2 9 : (1) the clock signal driven on the rx_coreclk port must have 0 ppm frequency difference with respect to the receiver phase compensation fifo write clock.
chapter 1: hardcopy iv gx transceiver architecture 1?117 receiver channel datapath ? june 2009 altera corporation hardcopy iv device handbook volume 3 offset cancellation is executed automatically once each time a hardcopy iv gx device is powered on. the control logic for offset cancellation is integrated into the altgx_reconfig megafunction. to use this logic, you need to enable the offset cancellation option in the altgx_reconfig megawizard plug-in manager. additionally, the reconfig_fromgxb and reconfig_togxb buses and the necessary clocks need to be connected between the altgx instance and the altgx_reconfig instance. f r r fr ff cc cr c ccv rfr r c cfr cr v f r vc 1 r ff cc f busy signal, the rx_analogreset is not relevant until the busy signal goes low. offset cancellation logic requires a separate clock. in pipe mode, you must connect the clock input to the fixedclk port provided by the altgx megawizard plug-in manager. the frequency of this clock input must be 125 mhz. for all other functional modes, connect the clock input to the reconfig_clk port provided by the altgx megawizard plug-in manager. the frequency of the clock connected to the reconfig_clk port must be within the range of 37.5 to 50 mhz. figure 1?99 shows the interface of the offset cancellation control logic (altgx_reconfig instance) and the altgx instance. the offset cancellation process begins by disconnecting the path from the receiver input buffer to the receiver cdr. it then sets the receiver cdr into a fixed set of dividers to guarantee a v co clock rate that is within the range necessary to provide proper offset cancellation. subsequently, the offset cancellation process goes through various states and culminates in the offset cancellation of the receiver buffer and the receiver cdr. figure 1?99. interface of offset cancellation control logic to the altgx instance altgx_reconfig instance offset cancellation logic transceiver block reconfig_togxb reconfig_fromgxb rx tx buffer cdr rx tx buffer cdr rx tx buffer cdr rx tx buffer cdr dynamic re-config logic busy altgx instance with 4 channels reconfig_clk reconfig_clk
1?118 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation after offset cancellation is complete, your divider settings are restored. then the reconfiguration block sends and receives data to the altgx using the reconfig_togxb and reconfig_fromgxb buses. connect the buses between the altgx_reconfig and altgx instances. the de-assertion of the busy signal from the offset cancellation control logic indicates the offset cancellation process is complete. functional modes you can configure hardcopy iv gx transceivers in one of the following functional modes using the altgx megawizard plug-in manager: basic functional mode the hardcopy iv gx transceiver datapath is extremely flexible in basic functional mode. to configure the transceiver in basic functional mode, you must select basic in the which protocol will you be using? option of the altgx megawizard plug-in manager. basic functional mode can be further sub-divided into the following two functional modes:
chapter 1: hardcopy iv gx transceiver architecture 1?119 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 table 1?30 shows the pcs-pma interface widths and data rates supported in basic single-width and double-width modes. low latency pcs datapath the altgx megawizard plug-in manager provides an enable low latency pcs mode option when configured in basic single-width or basic double-width mode. if you select this option, the following transmitter and receiver channel pcs blocks are bypassed to yield a low latency pcs datapath: table 1?30. pcs-pma interface widths and data rates in basic single-width and double-width modes basic functional mode supported data rate range (1) pma-pcs interface width basic single-width mode 600 mbps to 3.75 gbps 8 bit 10 bit basic double-width mode 1 gbps to 6.5 gbps 16 bit 20 bit note to tab l e 1 ?3 0 : (1) the data rate range supported in basic single-width and double-width modes varies depending on whether or not you use the byte serializer/deserializer. for more information, refer to ?basic single-width mode configurations? on page 1?120 and ?basic double-width mode configurations? on page 1?122 .
1?120 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation basic single-width mode configurations figure 1?100 shows hardcopy iv gx transceiver configurations allowed in basic single-width functional mode with an 8-bit pma-pcs interface. figure 1?100. transceiver configurations in basic single-width mode with an 8-bit pma-pcs interface disabled disabled disabled rate match fifo byte serdes byte ordering hardcopy iv gx configurations basic single width double width protocol pipe xaui gige srio sonet /sdh (oif) cei sdi 8-bit 10-bit 16-bit 20-bit 10-bit 10-bit 10-bit 10-bit 8-bit 16-bit 10-bit enabled disabled disabled disabled enabled disabled enabled disabled disabled disabled disabled disabled enabled disabled enabled disabled disabled fpga fabric - transceiver interface frequency disabled disabled functional modes pma-pcs interface width pma-pcs interface width data rate (gbps) channel bonding low-latency pcs word aligner (pattern length) 8b/10b encoder/decoder data rate (gbps) core fabric-transceiver interface width core fabric-transceiver interface frequency (mhz) 75 - 250 37.5 - 195.3125 37.5 - 195.3125 75 - 250 37.5 - 195.3125 8-bit 8-bit 16-bit 16-bit 16-bit 0.6 - 2.0 0.6 - 3.125 0.6 - 2.0 0.6 - 3.125 manual alignment (16-bit) bit-slip (16-bit) basic single-width 8-bit pma-pcs interface width 0.6 - 3.2 x1, x4, x8 0.6 - 2.0 0.6 - 3.2 8-bit 16-bit 75 - 250 37.5 - 200
chapter 1: hardcopy iv gx transceiver architecture 1?121 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?101 shows hardcopy iv gx transceiver configurations allowed in basic single-width functional mode with a 10-bit pma-pcs interface. figure 1?101. transceiver configurations in basic single-width mode with a 10-bit pma-pcs interface disabled disabled disabled rate match fifo byte serdes byte ordering hardcopy iv gx configurations basic single width double width protocol pipe xaui gige srio sonet /sdh (oif) cei sdi 8-bit 10-bit 16-bit 20-bit 10-bit 10-bit 10-bit 10-bit 8-bit 16-bit 10-bit enabled disabled disabled disabled disabled disabled channel bonding fpga fabric - transceiver interface frequency enabled disabled enabled disabled enabled disabled disabled disabled disabled disabled enabled enabled disabled enabled disabled enabled disabled enabled disabled disabled disabled disabled disabled disabled disabled disabled enabled disabled enabled disabled enabled disabled disabled disabled disabled enabled disabled disabled disabled enabled disabled disabled functional modes pma-pcs interface width pma-pcs interface width data rate (gbps) low-latency pcs word aligner (pattern length) 8b/10b encoder/decoder data rate (gbps) core fabric-transceiver interface width core fabric-transceiver interface frequency (mhz) 30 - 187.5 30 - 187.5 30 - 187.5 30 - 187.5 30 - 187.5 30 - 187.5 30 - 187.5 30 - 187.5 60 - 250 60 - 250 60 - 250 60 - 250 60 - 250 60 - 250 60 - 250 10-bit 10-bit 10-bit 16-bit 16-bit 16-bit 16-bit 16-bit 8-bit 8-bit 8-bit 8-bit 20-bit 20-bit 20-bit 0.6 - 2.5 0.6 - 2.5 0.6 - 2.5 0.6 - 2.5 0.6 - 2.5 0.6 - 2.5 0.6 - 2.5 0.6 - 3.75 0.6 - 3.75 0.6 - 3.75 0.6 - 3.75 0.6 - 3.75 0.6 - 3.75 0.6 - 3.75 automatic synchronization state machine (7-bit, 10-bit) bit-slip (7-bit, 10-bit) manual alignment (7-bit, 10-bit) x1, x4, x8 0.6 - 3.75 basic single-width 10-bit pma-pcs interface width 0.6 - 2.5 0.6 - 3.75 10-bit 20-bit 60 - 250 30 - 187.5
1?122 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation basic double-width mode configurations figure 1?102 shows hardcopy iv gx transceiver configurations allowed in basic double-width functional mode with a 16-bit pma-pcs interface. figure 1?102. transceiver configurations in basic double-width mode with a 16-bit pma-pcs interface note to figure 1?102 : (1) the byte ordering block is available only if you select the word alignment pattern length of 16 or 32 bits. disabled disabled disabled rate match fifo byte serdes byte ordering hardcopy iv gx configurations basic single- width double- width protocol pipe xaui gige srio sonet /sdh (oif) cei sdi 8-bit 10-bit 16-bit 20-bit 10-bit 10-bit 10-bit 10-bit 8-bit 16-bit 10-bit enabled disabled disabled disabled enabled disabled enabled disabled disabled disabled disabled disabled enabled channel bonding disabled enabled disabled disabled fpga fabric - transceiver interface frequency disabled disabled functional modes pma-pcs interface width pma-pcs interface width data rate (gbps) low-latency pcs word aligner (pattern length) 8b/10b encoder/decoder data rate (gbps) core fabric-transceiver interface width core fabric-transceiver interface frequency (mhz) 62.5 - 250 62.5 - 250 31.25 - 203.125 31.25 - 203.125 31.25 - 203.125 16-bit 16-bit 32-bit 32-bit 32-bit 1.0 - 4.0 1.0 - 4.0 1.0 - 6.5 1.0 - 6.5 manual alignment (8-, 16-, 32-bit) bit-slip (8-, 16-, 32-bit) x1, x4, x8 1.0 - 6.5 basic double-width 16-bit pma-pcs interface width 1.0 - 4.0 1.0 - 6.5 32-bit 16-bit 31.25 - 203.125 62.5 - 250 (1)
chapter 1: hardcopy iv gx transceiver architecture 1?123 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?103 shows hardcopy iv gx transceiver configurations allowed in basic double-width functional mode with a 20-bit pma-pcs interface. deterministic latency options the hardcopy iv gx device has a deterministic latency option available for use in high-speed serial interfaces such as cpri (common public radio interface). this option is available in single-width mode with 8/10-bit channel width and double-width mode with 16/20-bit channel width options only. figure 1?103. transceiver configurations in basic double-width mode with a 20-bit pma-pcs interface note to figure 1?103 : (1) the byte ordering block is available only if you select the word alignment pattern length of 20 bits. word aligner (pattern length ) basic double width 20-bit pma-pcs interface width disabled manual alignment (7-, 10-, 20-bit) disabled disabled 8b/10b encoder /decoder rate match fifo byte serdes byte ordering hardcopy iv gx configurations basic single width double width functional modes protocol pipe xaui gige srio sonet /sdh (oif) cei sdi 8-bit 10-bit 16-bit 20-bit 10-bit 10-bit 10-bit 10-bit 8-bit 16-bit 10-bit pma-pcs interface width pma-pcs interface width low-latency pcs enabled bit-slip (7-, 10-, 20-bit) disabled disabled disabled disabled disabled data rate (gbps) 1.0 ? 6.5 channel bonding x1, x4, x8 core fabric - transceiver interface width 20-bit data rate (gbps) 1.0 ? 5.0 fpga fabric - transceiver interface frequency core fabric - transceiver interface frequency ( mhz ) 1.0 ? 5.0 enabled disabled enabled disabled disabled disabled enabled disabled enabled disabled enabled disabled enabled 1.0 ? 6.5 1.0 ? 5.0 1.0 ? 6.5 1.0 ? 5.0 1.0 ? 6.5 1.0 ? 5.0 1.0 ? 6.5 disabled disabled disabled disabled disabled disabled disabled 40-bit 16-bit 32-bit 20-bit 40-bit 16-bit 32-bit disabled enabled 1.0 ? 6.5 disabled disabled 20-bit 40-bit enabled disabled enabled 1.0 ? 5.0 1.0 ? 6.5 enabled (1) enabled (1) 40-bit 32-bit disabled disabled 16-bit 32-bit 50 - 250 50 - 250 50 - 250 50 - 250 50 - 250 50 - 250 25 - 162.5 25 - 162.5 25 - 162.5 25 - 162.5 25 - 162.5 25 - 162.5 25 - 162.5 25 - 162.5
1?124 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation to implement deterministic latency mode under the basic functional mode, the transmitter must be placed in bit-slip mode, the receiver?s phase compensation fifo must be placed in register mode and a port on the receiver, rx_bitslipboundaryselectout[4:0] should be used. for example, for a full duplex (with both receiver and transmitter channels) link, you must select enable the rx phase comp fifo in register mode in the altgx megawizard plug-in manager. when this option is selected, the transmitter is placed in bit-slipping mode and the tx_bitslipboundaryselect[4:0] port is automatically available. similarly, the rx_bitslipboundaryselectout[4:0] output port is automatically available. rx bit slipping the number of bits slipped in the receiver?s word aligner is given out on the rx_bitslipboundaryselectout[4:0] output port. the information on this output depends on your deserializer block width. in single-width mode with 8/10-bit channel width, the number of bits slipped in the receiver path is given out sequentially on this output. for example, if zero bits are slipped, the output on rx_bitslipboundaryselectout[4:0] shows a value of 0(00000); if two bits are slipped, the output on rx_bitslipboundaryselectout[4:0] shows a value of 2 (00010). in double-width mode with 16/20-bit channel width, the output is 19 minus the number of bits slipped. for example, if 0 bits are slipped, the output on rx_bitslipboundaryselectout[4:0] shows a value of 19 (10011); if two bits are slipped, the output on rx_bitslipboundaryselectout[4:0] shows a value of 17 (10001). the information on the rx_bitslipboundaryselectout[4:0] output port helps in calculating the latency through the receiver datapath. you can use the information on rx_bitslipboundaryselectout[4:0] to set up the tx_bitslipboundaryselect[4:0] appropriately to cancel out the latency uncertainty. figure 1?104. transceiver datapath when in deterministic latency mode transmitter channel pcs transmitter channel pma receiver channel pcs receiver channel pma pci express hardip pci express hardip pipe interface pipe interface core fa b ric bit slip tx phase compensation fifo byte serializer 8b/10b encoder serializer cdr de- serialzier w ord aligner rate match fifo 8b/10b decoder byte de- serializer rx phase compensation fifo
chapter 1: hardcopy iv gx transceiver architecture 1?125 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 receiver phase comp fifo in register mode to remove the latency uncertainty through the receiver?s phase compensation fifo, select the enable the rx phase comp fifo in register mode option in the altgx megawizard plug-in manager. in register mode, the phase compensation fifo acts as a register and thereby removes the uncertainty in latency. the latency through the phase compensation fifo in register mode is one clock cycle. this mode is available in: transmitter bit slipping the transmitter is bit slipped to achieve deterministic latency. to use this feature, select the create the ?tx_bitslipboundaryselect[4:0] port to control the number of bits slipped in the tx bitslipper option in the altgx megawizard plug-in manager. the tx_bitslipboundaryselect[4:0] input port is used to set the number of bits that the transmitter block needs to slip. pci express (pipe) mode intel corporation has developed a phy interface for the pipe architecture specification to enable implementation of a pipe-compliant physical layer device. the pipe specification also defines a standard interface between the physical layer device and the media access control layer (mac). version 2.0 of the pipe specification provides implementation details for a pipe-compliant physical layer device at both gen1 (2.5 gt/s) and gen2 (5 gt/s) signaling rates. to implement a version 2.0 pipe-compliant phy, you must configure the hardcopy iv gx transceivers in pipe functional mode. hardcopy iv gx devices have built-in pipe hard ip blocks that you can use to implement the phy-mac layer, data link layer, and transaction layer of the pipe protocol stack. you can also bypass the pipe hard ip blocks and implement the phy-mac layer, data link layer, and transaction layer in the fgpa fabric using a soft ip. if you enable the pipe hard ip blocks, the hardcopy iv gx transceivers interface with these hard ip blocks. otherwise, the hardcopy iv gx transceivers interface with the core fabric. you can configure the hardcopy iv gx transceivers in pipe functional mode using one of the following two methods:
1?126 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation 1 description of pci express (pipe) hard ip architecture and pipe mode configurations allowed when using the pipe hard ip block are beyond the scope of this chapter. for more information about the pipe hard ip block, refer to the pci express compiler user guide. pci express (pipe) mode configurations hardcopy iv gx transceivers support both gen1 (2.5 gbps) and gen2 (5 gbps) data rates in pipe functional mode. when configured for a gen2 (5 gbps) data rate, the hardcopy iv gx transceivers allow dynamic switching between gen2 (5 gbps) and gen1 (2.5 gbps) signaling rates. dynamic switch capability between the two pipe signaling rates is critical for speed negotiation during link training. hardcopy iv gx transceivers support 1, 4, and 8 lane configurations in pipe functional mode at both 2.5 gbps and 5 gbps data rates. in pipe 1 configuration, the pcs and pma blocks of each channel are clocked and reset independently. pipe 4 and 8 configurations support channel bonding for four-lane and eight-lane pipe links. in these bonded channel configurations, the pcs and pma blocks of all bonded channels share common clock and reset signals.
chapter 1: hardcopy iv gx transceiver architecture 1?127 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?105 shows the hardcopy iv gx transceiver configurations allowed in pci express (pipe) functional mode. figure 1?105. hardcopy iv gx transceivers in pci express (pipe) functional mode channel bonding rate match fifo functional mode data rate disabled byte serdes disabled disabled enabled enabled enabled disabled disabled enabled pipe 2.5 gbps (gen1) x1, x4, x8 10-bit automatic synchronization state machine (/k28.5+/,/k28.5-/) enabled enabled enabled 8-bit 8-bit 16-bit 250 mhz 250 mhz 125 mhz pma-pcs interface width word aligner (pattern) 8b/10b encoder/ decoder pci express hardip pcs-hardip or pcs-core fabric interface width pcs-hardip or pcs-core fabric interface frequency 500 mhz 250 mhz 8-bit 16-bit enabled automatic synchronization state machine (/k28.5+/,/k28.5-/) 10-bit x1, x4, x8 5 gbps (gen2) hardcopy iv gx configurations basic single width double width functional modes protocol pipe xaui gige srio sonet /sdh (oif) cei sdi 8-bit 10-bit 16-bit 10-bit 20-bit 10-bit 10-bit 10-bit 8-bit 16-bit 10-bit pma-pcs interface width
1?128 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation pci express (pipe) mode datapath figure 1?106 shows the hardcopy iv gx transceiver datapath when configured in pci express (pipe) functional mode. table 1?31 shows the transceiver datapath clock frequencies in pipe functional mode configured using the altgx megawizard plug-in manager. transceiver datapath clocking varies between non-bonded (1) and bonded (4 and 8) configurations in pipe mode. the transmitter datapath in pci express (pipe) mode consists of: figure 1?106. hardcopy iv gx transceiver datapath in pci express (pipe) 1 mode tx phase compensation fifo byte serializer 8b/10b encoder serializer transmitter channel pcs transmitter channel pma /2 wrclk wrclk rdclk rdclk low-speed parallel clock high-speed serial clock tx_coreclk[0] rx phase compensation fifo byte de- serializer 8b/10b decoder rate match fifo word aligner de- serializer cdr /2 tx_clkout[0] parallel recovered clock low-speed parallel clock rx_coreclk[0] receiver channel pcs receiver channel pma core fabric-transceiver interface clock pci express hardip pci express hardip pipe interface pipe interface core fabric table 1?31. hardcopy iv gx transceiver datapath clock frequencies in pci express (pipe) mode functional mode data rate high-speed serial clock frequency parallel recovered clock and low-speed parallel clock frequency core fabric-transceiver interface clock frequency without byte serializer/ deserializer (8-bit wide) with byte serializer/ deserializer (16-bit wide) pci express (pipe) 1, 4, 8 (gen1) 2.5 gbps 1.25 ghz 250 mhz 250 mhz 125 mhz pci express (pipe) 1, 4, 8 (gen2) 5 gbps 2.5 ghz 500 mhz n/a (1) 250 mhz note to tab l e 1 ?3 1 : (1) in pci express (pipe) functional mode at gen2 (5 gbps) data rate, the byte serializer/deserializer cannot be bypassed.
chapter 1: hardcopy iv gx transceiver architecture 1?129 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3  optional byte serializer (enabled for 16-bit and disabled for 8-bit core fabric-transceiver interface)  8b/10b encoder  10:1 serializer  transmitter buffer with receiver detect circuitry the receiver datapath in pci express (pipe) mode consists of:  receiver buffer with signal detect circuitry  1:10 deserializer  word aligner that implements pipe-compliant synchronization state machine  optional rate match fifo (clock rate compensation) that can tolerate up to 600 ppm frequency difference  8b/10b decoder  optional byte deserializer (enabled for 16-bit and disabled for 8-bit core fabric-transceiver interface)  receiver phase compensation fifo  pipe interface table 1?32 shows features supported in pipe functional mode for 2.5 gbps and 5 gbps data rate configurations. table 1?32. supported features in pci express (pipe) mode feature 2.5 gbps (gen1) 5gbps (gen2) 1, 4, 8 link configurations vv pipe-compliant synchronization state machine vv 300 ppm (total 600 ppm) clock rate compensation vv 8-bit core fabric-transceiver interface v ? 16-bit core fabric-transceiver interface vv transmitter buffer electrical idle vv receiver detection vv 8b/10b encoder disparity control when transmitting compliance pattern vv power state management vv receiver status encoding vv dynamic switch between 2.5 gbps and 5 gbps signaling rate ? v dynamically selectable transmitter margining for differential output voltage control ? v dynamically selectable transmitter buffer de-emphasis of -3.5 db and -6 db ? v dynamically selectable full-swing and half-swing transmitter output voltage levels ? v
1?130 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation pci express (pipe) interface in pipe mode, each channel has a pipe interface block that transfers data, control, and status signals between the phy-mac layer and the transceiver channel pcs and pma blocks. the pipe interface block is compliant to version 2.0 of the pipe specification. if you use the pipe hard ip block, the phy-mac layer is implemented in the hard ip block. otherwise, the phy-mac layer can be implemented using soft ip in the core fabric. 1 rfc c c rfrr cr w r rcvr rfc c fw fc rr c c r vc transmitter buffer electrical idle when the input signal tx_forceelecidle is asserted high, the pipe interface block puts the transmitter buffer in that channel in the electrical idle state. during electrical idle, the transmitter buffer differential and common mode output voltage levels are compliant to the pipe base specification 2.0 for both pipe gen1 and gen2 data rates. figure 1?107 shows the relationship between the assertion of the tx_forceelecidle signal and the transmitter buffer output on the tx_dataout port. time t1 taken from the assertion of the tx_forceelecidle signal to the transmitter buffer reaching electrical idle voltage levels is pending characterization. once in the electrical idle state, the pipe protocol requires the transmitter buffer to stay in electrical idle for a minimum of 20 ns for both gen1 and gen2 data rates. 1 r f fr wc frcc r c rr ffr crc fr crcr
chapter 1: hardcopy iv gx transceiver architecture 1?131 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 the pci express (pipe) specification requires the transmitter buffer to be in electrical idle in certain power states. for more information about the tx_forceelecidle signal levels required in different pipe power states, refer to table 1?31 on page 1?128 . receiver detection during the detect substate of the link training and status state machine (ltssm), the pipe protocol requires the transmitter channel to perform a receiver detect sequence to detect if a receiver is present at the far end of each lane. the pipe specification requires the receiver detect operation to be performed during the p1 power state. the pipe interface block in hardcopy iv gx transceivers provides an input signal tx_detectrxloopback for the receiver detect operation. when the input signal tx_detectrxloopback is asserted high in the p1 power state, the pipe interface block sends a command signal to the transmitter buffer in that channel to initiate a receiver detect sequence. in the p1 power state, the transmitter buffer must always be in the electrical idle state. after receiving this command signal, the receiver detect circuitry creates a step voltage at the output of the transmitter buffer. if an active receiver (that complies to the pipe input impedance requirements) is present at the far end, the time constant of the step voltage on the trace is higher than when the receiver is not present. receiver detect circuitry monitors the time constant of the step signal seen on the trace to determine if a receiver was detected. the receiver detect circuitry monitor needs a 125-mhz clock for operation that you must drive on the fixedclk port. 1 for the receiver detect circuitry to function reliably, the ac-coupling capacitor on the serial link and the receiver termination values used in your system must be compliant to the pci express (pipe) base specification 2.0. receiver detect circuitry communicates the status of the receiver detect operation to the pipe interface block. if a far-end receiver is successfully detected, the pipe interface block asserts pipephydonestatus for one clock cycle and synchronously drives the pipestatus[2:0] signal to 3'b011. if a far-end receiver is not detected, the pipe interface block asserts pipephydonestatus for one clock cycle and synchronously drives the pipestatus[2:0] signal to 3'b000. figure 1?108 and figure 1?109 show the receiver detect operation where a receiver was successfully detected and where a receiver was not detected, respectively. figure 1?107. transmitter buffer electrical idle state tx_forcelecidle tx_dataout t1 >20 ns
1?132 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation compliance pattern transmission support the ltssm state machine can enter the polling.compliance substate where the transmitter is required to transmit a compliance pattern as specified in the pci express (pipe) base specification 2.0. the po lling.compliance substate is intended to assess if the transmitter is electrically compliant with the pipe voltage and timing specifications. the compliance pattern is a repeating sequence of the following four code groups: /k28.5/ /d21.5/ /k28.5/ /d10.2/ the pci express (pipe) protocol requires the first /k28.5/ code group of the compliance pattern to be encoded with negative current disparity. to satisfy this requirement, the pipe interface block provides the input signal tx_forcedispcompliance. a high level on tx_forcedispcompliance forces the associated parallel transmitter data on the tx_datain port to transmit with negative current running disparity. figure 1?108. receiver detect, successfully detected figure 1?109. receiver detect, unsuccessfully detected powerdown[1:0] tx_detectrxloopback pipephydonestatus pipestatus[2:0] 3'b000 2'b10(p1) 3'b011 powerdown[1:0] tx_detectrxloopback pipephydonestatus pipestatus[2:0] 3'b000 2'b10 (p1)
chapter 1: hardcopy iv gx transceiver architecture 1?133 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3  for 8-bit transceiver channel width configurations, you must drive tx_forcedispcompliance high in the same parallel clock cycle as the first /k28.5/ of the compliance pattern on the tx_datain port.  for 16-bit transceiver channel width configurations, you must drive only the lsb of tx_forcedispcompliance[1:0] high in the same parallel clock cycle as /k28.5/d21.5/ of the compliance pattern on the tx_datain port. figure 1?110 and figure 1?111 show the required level on the tx_forcedispcompliance signal while transmitting the compliance pattern in 8-bit and 16-bit channel width configurations, respectively. power state management the pci express (pipe) specification defines four power states?p0, p0s, p1, and p2? that the physical layer device must support to minimize power consumption.  p0 is the normal operating state during which packet data is transferred on the pipe link.  p0s, p1, and p2 are low-power states into which the physical layer must transition as directed by the phy-mac layer to minimize power consumption. the pipe specification provides the mapping of these power states to the ltssm states specified in the pipe base specification 2.0. the phy-mac layer is responsible for implementing the mapping logic between the ltssm states and the four power states in the pipe-compliant phy. figure 1?110. compliance pattern transmission support, 8-bit channel width configurations figure 1?111. compliance pattern transmission support, 16-bit channel width configurations bc bc bc bc tx_datain[7:0] tx_ctrldetect tx_forcedispcompliance b5 4a b5 4a k28.5 d21.5 k28.5 d10.2 k28.5 d21.5 k28.5 d10.2 01 00 01 tx_datain[15:0] tx_ctrldetect[1:0] tx_forcedispcompliance[1:0] b5bc /k28.5/d21.5/ /k28.5/d10.2/ bc4a b5bc /k28.5/d21.5/ bc4a /k28.5/d10.2/
1?134 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation the pci express (pipe) interface in hardcopy iv gx transceivers provides an input port, powerdn[1:0] , for each transceiver channel configured in pipe mode. table 1?33 shows mapping between the logic levels driven on the powerdn[1:0] port and the resulting power state that the pipe interface block puts the transceiver channel into. 1 r fr wr wr wr 1 cfc rr c r vc wr v r r rcvr wr v r c rr ffr crc wr wr rfc c c ccf wr r r pipephydonestatus signal for one parallel clock cycle as specified in the pipe specification. the phy-mac layer must not request any further power state transition until the pipephydonestatus signal has indicated the completion of the current power state transition request. figure 1?112 shows an example waveform for a transition from the p0 to p2 power state. the pipe specification allows the pipe interface to perform protocol functions; for example, receiver detect, loopback, and beacon transmission, in specified power states only. this requires the phy-mac layer to drive the tx_detectrxloopback and tx_forceelecidle signals appropriately in each power state to perform these functions. table 1?34 summarizes the logic levels that the phy-mac layer must drive on the tx_detectrxloopback and tx_forceelecidle signals in each power state. table 1?33. power state functions and descriptions power state powerdn function description p0 2?b00 transmits normal data, transmits electrical idle, or enters into loopback mode normal operation mode p0s 2?b01 only transmits electrical idle low recovery time saving state p1 2?b10 transmitter buffer is powered down and can do a receiver detect while in this state high recovery time power saving state p2 2?b11 transmits electrical idle or a beacon to wake up the downstream receiver lowest power saving state figure 1?112. power state transition from p0 to p2 parallel clock powerdn[1:0] pipephydonestatus 2'b00 (p0) 2'b11 (p2)
chapter 1: hardcopy iv gx transceiver architecture 1?135 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 receiver status the pci express (pipe) specification requires the phy to encode the receiver status on a 3-bit rxstatus[2:0] signal. this status signal is used by the phy-mac layer for its operation. the pipe interface block receives status signals from the transceiver channel pcs and pma blocks and encodes the status on the 3-bit output signal pipestatus[2:0] to the core fabric. the encoding of the status signals on pipestatus[2:0] is compliant with the pipe specification and is listed in table 1?35 . two or more of the error conditions (for example, 8b/10b decode error [code group violation], rate match fifo overflow or underflow, and receiver disparity error), can occur simultaneously. the pipe interface follows the priority listed in table 1?35 while encoding the receiver status on the pipestatus[2:0] port. for example, if the pipe interface receives an 8b/10b decode error and disparity error for the same symbol, it drives 3'b100 on the pipestatus[2:0] signal. fast recovery mode the pipe base specification fast training sequences (fts) are used for bit and byte synchronization to transition from l0s to l0 (pipe p0s to p0) power states. when transitioning from l0s to l0 power state, the pipe base specification requires the physical layer device to acquire bit and byte synchronization after receiving a maximum of 255 fts (~4 us at gen1 data rate and ~2 us at gen2 data rate). table 1?34. logic levels for the phy-mac layer power state tx_detectrxloopback tx_forceelecidle p0 0: normal mode 1: datapath in loopback mode 0: must be de-asserted 1: illegal mode p0s don?t care 0: illegal mode 1: must be asserted in this state p1 0: electrical idle 1: receiver detect 0: illegal mode 1: must be asserted in this state p2 don?t care de-asserted in this state for sending beacon. otherwise asserted. table 1?35. encoding of the status signals on pipestatus[2:0] pipestatus[2:0] description error condition priority 3'b000 received data ok ? 3'b001 one skp symbol added 5 3'b010 one skp symbol deleted 6 3'b011 receiver detected ? 3'b100 8b/10b decode error 1 3'b101 elastic buffer (rate match fifo) overflow 2 3'b110 elastic buffer (rate match fifo) underflow 3 3'b111 received disparity error 4
1?136 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation if the hardcopy iv gx receiver cdr is configured in automatic lock mode, the receiver cannot meet the pci express (pipe) specification of acquiring bit and byte synchronization within 4 2 2 . , . 1 cvr crcr c f rcvr r r f cvr cvr crcr cr rcvr rx_locktorefclk and rx_locktodata signals to force the receiver cdr in ltr or ltd mode. it relies on the electrical idle ordered sets (eios), n_fts sequences received in the l0 power state, and the signal detect signal from the receiver input buffer to control the receiver cdr lock mode. 1 cvr crcr fr rr cr fr rx_locktorefclk and rx_locktodata ports are not available in the altgx megawizard plug-in manager. electrical idle inference the pipe protocol allows inferring the electrical idle condition at the receiver instead of detecting the electrical idle condition using analog circuitry. clause 4.2.4.3 in the pipe base specification 2.0 specifies conditions to infer electrical idle at the receiver in various substates of the ltssm state machine. in all pipe modes (1, 4, and 8), each receiver channel pcs has an optional electrical idle inference module designed to implement the electrical idle inference conditions specified in the pipe base specification 2.0. you can enable the electrical idle inference module by selecting the enable electrical idle inference functionality option in the altgx megawizard plug-in manager. if enabled, this module infers electrical idle depending on the logic level driven on the rx_elecidleinfersel[2:0] input signal. the electrical idle inference module in each receiver channel indicates whether the electrical idle condition is inferred or not on the pipeelecidle signal of that channel. the electrical idle interface module drives the pipeelecidle signal high if it infers an electrical idle condition; otherwise, it drives it low. table 1?36 shows electrical idle inference conditions specified in the pipe base specification 2.0 and implemented in the electrical idle inference module to infer electrical idle in various substates of the ltssm state machine. for the electrical idle inference module to correctly infer an electrical idle condition in each ltssm substate, you must drive the rx_elecidleinfersel[2:0] signal appropriately, as shown in table 1?36 . table 1?36. electrical idle inference conditions (part 1 of 2) ltssm state gen1 (2.5 gbps) gen2 (5 gbps) rx_elecidleinfersel[2:0] l0 absence of skip ordered set in 128 s window absence of skip ordered set in 128 s window 3'b100 recovery.rcvrcfg absence of ts1 or ts2 ordered set in 1280 ui interval absence of ts1 or ts2 ordered set in 1280 ui interval 3'b101
chapter 1: hardcopy iv gx transceiver architecture 1?137 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 in the recovery.speed substate of the ltssm state machine with unsuccessful speed negotiation ( rx_elecidleinfersel[2:0] = 3'b110 ), the pci express (pipe) base specification requires the receiver to infer an electrical idle condition ( pipeelecidle = high) if absence of an exit from electrical idle is detected in a 2000 ui interval for gen1 data rate and 16000 ui interval for gen2 data rate. the electrical idle inference module detects an absence of exit from electrical idle if four /k28.5/ com code groups are not received in the specified interval. in other words, when configured for gen1 data rate and rx_elecidleinfersel[2:0] = 3'b110, the electrical idle inference module asserts pipeelecidle high if it does not receive four /k28.5/ com code groups in a 2000 ui interval. when configured for gen1 data rate and rx_elecidleinfersel[2:0] = 3'b111 in the loopback active substate of the ltssm state machine, the electrical idle inference module asserts pipeelecidle high if it does not receive four /k28.5/ com code groups in a 128 s interval. when configured for gen2 data rate and rx_elecidleinfersel[2:0] = 3'b110, the electrical idle inference module asserts pipeelecidle high if it does not receive four /k28.5/ com code groups in a 16000 ui interval. 1 crc frc v c c crc c rc f crc rr cf r cfc f c enable electrical idle inference functionality option in the altgx megawizard plug-in manager and drive rx_elecidleinfersel[2:0] = 3'b0xx , the electrical idle inference block uses the eios detection from the fast recovery circuitry to drive the pipeelecidle signal. if you do not select the enable electrical idle inference functionality option in the altgx megawizard plug-in manager, the electrical idle inference module is disabled. in this case, the rx_signaldetect signal from the signal detect circuitry in the receiver buffer is inverted and driven as the pipeelecidle signal. pci express (pipe) gen2 (5 gbps) support the pci express (pipe) functional mode supports the following additional features when configured for 5 gbps data rate:  dynamic switch between 2.5 gbps and 5 gbps signaling rate recovery.speed when successful speed negotiation = 1'b1 absence of ts1 or ts2 ordered set in 1280 ui interval absence of ts1 or ts2 ordered set in 1280 ui window 3'b101 recovery.speed when successful speed negotiation = 1'b0 absence of an exit from electrical idle in 2000 ui interval absence of an exit from electrical idle in 16000 ui interval 3'b110 loopback.active (as slave) absence of an exit from electrical idle in 128 s window ? 3'b111 table 1?36. electrical idle inference conditions (part 2 of 2) ltssm state gen1 (2.5 gbps) gen2 (5 gbps) rx_elecidleinfersel[2:0]
1?138 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation  dynamically selectable transmitter margining for differential output voltage control  dynamically selectable transmitter buffer de-emphasis of -3.5 db and -6 db  dynamically selectable full-swing and half-swing transmitter output voltage levels dynamic switch between gen1 (2.5 gbps) and gen2 (5 gbps) signaling rate during link training, the upstream and downstream pci express (pipe) ports negotiate the speed (2.5 gbps or 5 gbps) at which the link operates. because the upstream and downstream pipe ports do not know the speed capabilities of their link partner, the pipe protocol requires each port to start with a gen1 (2.5 gbps) signaling rate. one of the ports capable of supporting the gen2 (5 gbps) signaling rate might initiate a speed change request by entering the recovery state of the ltssm. in the recovery state, each port advertises its speed capabilities by transmitting training sequences as specified in the pipe base specification 2.0. if both ports are capable of operating at the gen2 (5 gbps) signaling rate, the phy-mac layer instructs the physical layer device to operate at the gen2 (5 gbps) signaling rate. to support speed negotiation during link training, the pipe specification requires a pipe-compliant physical layer device to provide an input signal ( rate) to the phy-mac layer. when this input signal is driven low, the physical layer device must operate at the gen1 (2.5 gbps) signaling rate; when driven high, this input signal must operate at the gen2 (5 gbps) signaling rate. the pipe specification allows the phy-mac layer to initiate a signaling rateswitch only in power states p0 and p1 with the transmitter buffer in electrical idle state. the pipe specification allows the physical layer device to implement the signaling rateswitch using either of the following approaches:  change the transceiver datapath clock frequency, keeping the transceiver interface width constant  change the transceiver interface width between 8 bit and 16 bit, keeping the transceiver clock frequency constant when configured in pipe functional mode at gen2 (5 gbps) data rate, the altgx megawizard plug-in manager provides the input signal rateswitch . the rateswitch signal is functionally equivalent to the rate signal specified in the pipe specification. the phy-mac layer can use the rateswitch signal to instruct the hardcopy iv gx device to operate at either gen1 (2.5 gbps) or gen2 (5 gbps) data rate, depending on the negotiated speed between the upstream and downstream ports. a low-to-high transition on the rateswitch signal initiates a data rateswitch from gen1 (2.5 gbps) to gen2 (5 gbps). a high-to-low transition on the rateswitch signal initiates a data rateswitch from gen2 (5 gbps) to gen1 (2.5 gbps). the signaling rateswitch between gen1 (2.5 gbps) and gen2 (5 gbps) is achieved by changing the transceiver datapath clock frequency between 250 mhz and 500 mhz, while maintaining a constant transceiver interface width of 16-bit. the dedicated pipe rateswitch circuitry performs the dynamic switch between the gen1 (2.5 gbps) and gen2 (5 gbps) signaling rate. the pipe rateswitch circuitry consists of:  pci express (pipe) rateswitch controller  pci express (pipe) clock switch circuitry
chapter 1: hardcopy iv gx transceiver architecture 1?139 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 pci express (pipe) rateswitch controller the rateswitch signal serves as the input signal to the pci express (pipe) rateswitch controller. after seeing a transition on the rateswitch signal from the phy-mac layer, the pci express (pipe) rateswitch controller performs the following operations:  controls the pipe clock switch circuitry to switch between gen1 (2.5 gbps) and gen2 (5 gbps) signaling rate, depending on the rateswitch signal level  disables and resets the transmitter and receiver phase compensation fifo pointers until the pipe clock switchover circuitry indicates successful rateswitch completion  communicates completion of rateswitch to the pipe interface module, which in turn communicates completion of the rateswitch to the phy-mac layer on the pipephydonestatus signal pci express (pipe) rateswitch controller location:  in pipe 1 mode, the pipe rateswitch controller is located in the transceiver pcs of each channel.  in pipe 4 mode, the pipe rateswitch controller is located in cmu0 channel within the transceiver block.  in pipe 8 mode, the pipe rateswitch controller is located in cmu0_channel within the master transceiver block. 1 when operating at the gen 2 data rate, asserting the rx_digitalreset signal causes the pipe rateswitch circuitry to switch the transceiver to gen 1 data rate. 1 when switching from gen1 to gen2 using the dynamic reconfiguration controller, you must set the two ports of the dynamic reconfiguration controller, tx_preemp_0t and tx_preemp_2t , to zero to meet the gen2 de-emphasis specifications. when switching from gen2 to gen1, if your system requires specific settings on tx_preemp_01 and tx_preemp_2t , those values must to be set at the respective two ports of the dynamic reconfiguration controller to meet your system requirements. pci express (pipe) clock switch circuitry when the phy-mac layer instructs a rateswitch between the gen1 (2.5 gbps) and gen2 (5 gbps) signaling rates, both the transmitter high-speed serial and low-speed parallel clock and the cdr recovered clock must switch to support the instructed data rate. hardcopy iv gx transceivers have dedicated pipe clock switch circuitry located in the following blocks:  local clock divider in transmitter pma of each transceiver channel  cmu0 clock divider in cmu0_channel of each transceiver block  receiver cdr in receiver pma of each transceiver channel
1?140 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation pci express (pipe) transmitter high-speed serial and low-speed parallel clock switch occurs: cmu_pll clock switch occurs in the local clock divider in each transceiver channel. cmu_pll clock switch occurs in the cmu0 clock divider in the cmu0_channel within the transceiver block. cmu_pll clock switch occurs in the cmu0 clock divider in the cmu0_channel within the master transceiver block. in pipe 1, 4, and 8 modes, the recovered clock switch happens in the receiver cdr of each transceiver channel. table 1?37 lists the locations of the pipe rateswitch controller and the pipe clock switch circuitry in pipe 1, 2, 4, and 8 modes. dynamic switch between gen1 (2.5 gbps) and gen2 (5 gbps) signaling rates in pci express (pipe) x1 mode figure 1?113 shows the pci express (pipe) rateswitch circuitry in pci express (pipe) 1 mode configured at gen2 (5 gbps) data rate. table 1?37. pci express (pipe) rateswitch controller and clock switch circuitry channel bonding option location of pci express (pipe) rateswitch controller module location of pci express (pipe) clock switch circuitry transmitter high-speed serial and low-speed parallel clock switch circuitry recovered clock switch circuitry 1 individual channel pcs block local clock divider in transmitter pma of each channel cdr block in receiver pma of each channel 4 cmu0 channel cmu0 clock divider in cmu0_channel cdr block in receiver pma of each channel 8 cmu0 channel of the master transceiver block cmu0 clock divider in cmu0_channel of the master transceiver block cdr block in receiver pma of each channel
chapter 1: hardcopy iv gx transceiver architecture 1?141 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 in pipe 1 mode configured at gen2 (5 gbps) data rate, when the pipe rateswitch controller sees a transition on the rateswitch signal, it sends control signal pcie_gen2switch to the pipe clock switch circuitry in the local clock divider block and the receiver cdr to switch to the instructed signaling rate. a low-to-high transition on the rateswitch signal initiates a gen1 (2.5 gbps) to gen2 (5 gbps) signaling rateswitch. a high-to-low transition on the rateswitch signal initiates a gen2 (5 gbps) to gen1 (2.5 gbps) signaling rateswitch. table 1?38 shows transceiver clock frequencies when switching between 2.5 gbps and 5 gbps signaling rates. figure 1?113. dynamic switch signaling in pipe 1 mode vco /2 rx_datain rx_cruclk rx_locktorefclk rx_lockt odata signal detect rx_freqlocked clock and data recovery (cdr) unit serial recovered clock parallel recovered clock 0 1 high-speed serial clock low-speed parallel clock cmu0_pll output clock cmu1_pll output clock local clock divider transceiver pcs core fabric rateswitch pipephydonestatus reset_int reset_int transceiver channel pci express clock switch circuitry phase detector (pd) phase frequency detector (pfd) charge pump + loop filter /l /m ltr/ltd controller pipe interface receiver phase comp fifo transmitter phase comp fifo /1, /2, /4 /1, /2, /4 /2 4, /5, /8, /10 pci express rate switch controller pci express clock switch circuitry pcie_gen2switch pcie_gen2switch pcie_gen2switch pcie_gen2switch_done table 1?38. transceiver clock frequencies signaling rates in pci express (pipe) 1 mode transceiver clocks gen1 (2.5 gbps) to gen2 (5 gbps) switch (low-to-high transition on the rateswitch signal) gen2 (5 gbps) to gen1 (2.5 gbps) switch (high-to-low transition on the rateswitch signal) high-speed serial clock 1.25 ghz to 2.5 ghz 2.5 ghz to 1.25 ghz low-speed parallel clock 250 mhz to 500 mhz 500 mhz to 250 mhz serial recovered clock 1.25 ghz to 2.5 ghz 2.5 ghz to 1.25 ghz parallel recovered clock 250 mhz to 500 mhz 500 mhz to 250 mhz core fabric-transceiver interface clock 125 mhz to 250 mhz 250 mhz to 125 mhz
1?142 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation the pci express (pipe) clock switch circuitry in the local clock divider block performs the clock switch between 250 mhz and 500 mhz on the low-speed parallel clock when switching between gen1 (2.5 gbps) and gen2 (5 gbps) signaling rates. it indicates successful completion of clock switch on the pcie_gen2switchdone signal to the pipe rateswitch controller. the pipe rateswitch controller forwards the clock switch completion status to the pipe interface block. the pipe interface block communicates the clock switch completion status to the phy-mac layer by asserting the pipephydonestatus signal for one parallel clock cycle. figure 1?114 shows low-speed parallel clock switch between gen1 (250 mhz) and gen2 (500 mhz) in response to the change in the logic level on the rateswitch signal. the rateswitch completion is shown marked with a one clock cycle assertion of the pipephydonestatus signal. 1 1 fr r rateswitch signal to the assertion of pipephydonestatus is pending characterization. as a result of the signaling rateswitch between gen1 (2.5 gbps) and gen2 (5 gbps), the core fabric-transceiver interface clock switches between 125 mhz and 250 mhz. the core fabric-transceiver interface clock clocks the read side and write side of the transmitter phase compensation fifo and the receiver phase compensation fifo, respectively. it is also routed to the core fabric on a global or regional clock resource and looped back to clock the write port and read port of the transmitter phase compensation fifo and the receiver phase compensation fifo, respectively. due to the routing delay between the write and read clock of the transmitter and receiver phase compensation fifos, the write pointers and read pointers might collide during a rateswitch between 125 mhz and 250 mhz. to avoid collision of the phase compensation fifo pointers, the pipe rateswitch controller automatically disables and resets the pointers during clock switch. when the pipe clock switch circuitry in the local clock divider indicates successful clock switch completion, the pipe rateswitch controller releases the phase compensation fifo pointer resets. figure 1?114. low-speed parallel clock switching in pci express (pipe) 1 mode pipephydonestatus low-speed parallel clock rateswitch 250 mhz (gen1) 500 mhz (gen2) 250 mhz (gen1) t1 t1
chapter 1: hardcopy iv gx transceiver architecture 1?143 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 dynamic switch between gen1 (2.5 gbps) and gen2 (5 gbps) signaling rates in pci express (pipe) 4 mode figure 1?115 shows the pipe rateswitch circuitry in pipe 4 mode configured at gen2 (5 gbps) data rate. in pipe 4 mode configured at gen2 (5 gbps) data rate, when the pipe rateswitch controller sees a transition on the rateswitch signal, it sends the pcie_gen2switch control signal to the pipe clock switch circuitry in the cmu0 clock divider block and the receiver cdr to switch to the instructed signaling rate. a low-to-high transition on the rateswitch signal initiates a gen1 (2.5 gbps) to gen2 (5 gbps) signaling rateswitch. a high-to-low transition on the rateswitch signal initiates a gen2 (5 gbps) to gen1 (2.5 gbps) signaling rateswitch. table 1?39 shows the transceiver clock frequencies when switching between 2.5 gbps and 5 gbps signaling rates. figure 1?115. dynamic switch signaling in pci express (pipe) 4 mode pipe interface pipe interface pipe interface vco clock and data recovery (cdr) unit serial recovered clock parallel recovered clock 0 1 transceiver pcs rateswitch pipephydonestatu s[3:0] transceiver block pcie _gen2switch pci express clock switch circuitry core fabric pipe interface receiver phase compen- sation fifo transmitter phase compen- sation fifo reset_int reset_int rx_locktorefclk rx_locktodata signal_detect rx_freqlocked rx_datain rx_cruclk /1. /2, /4 /2 ltr/ltd controller phase detector (pd) phase frequency detector (pfd) charge pump + loop filter /2 pcie_gen2switch /l /m cmu0_channel cmu0 clock divider high-speed serial clock to the four (pipe x4) bonded channels low-speed parallel clock to the four (pipe x4) bonded channels /4, /5, /8, /10 pci express clock switch circuitry /1, /2, /4 pcie_gen2switch pcie_gen2switch_done cmu0_ pll cmu1_ pll cmu1_channel cmu1 clock divider /4, /5, /8, 10 /1, /2, /4 pci express rate switch controller ccu table 1?39. transceiver clock frequencies signaling rates in pci express (pipe) 4 mode (part 1 of 2) transceiver clocks gen1 (2.5 gbps) to gen2 (5 gbps) switch (low-to-high transition on the rateswitch signal) gen2 (5 gbps) to gen1 (2.5 gbps) switch (high-to-low transition on the rateswitch signal) high-speed serial clock 1.25 ghz to 2.5 ghz 2.5 ghz to 1.25 ghz low-speed parallel clock 250 mhz to 500 mhz 500 mhz to 250 mhz serial recovered clock 1.25 ghz to 2.5 ghz 2.5 ghz to 1.25 ghz
1?144 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation the pci express (pipe) clock switch circuitry in the cmu0 clock divider block performs the clock switch between 250 mhz and 500 mhz on the low-speed parallel clock when switching between gen1 (2.5 gbps) and gen2 (5 gbps) signaling rates. it indicates successful completion of clock switch on the pcie_gen2switchdone signal to the pipe rateswitch controller. the pipe rateswitch controller forwards the clock switch completion status to the pipe interface block. the pipe interface block communicates the clock switch completion status to the phy-mac layer by asserting the pipephydonestatus signal of all bonded channels for one parallel clock cycle. figure 1?116 shows the low-speed parallel clock switch between gen1 (250 mhz) and gen2 (500 mhz) in response to the change in the logic level on the rateswitch signal. the rateswitch completion is shown marked with a one clock cycle assertion of the pipephydonestatus signal of all bonded channels. 1 1 fr r rateswitch signal to the assertion of pipephydonestatus is pending characterization. parallel recovered clock 250 mhz to 500 mhz 500 mhz to 250 mhz core fabric-transceiver interface clock 125 mhz to 250 mhz 250 mhz to 125 mhz table 1?39. transceiver clock frequencies signaling rates in pci express (pipe) 4 mode (part 2 of 2) transceiver clocks gen1 (2.5 gbps) to gen2 (5 gbps) switch (low-to-high transition on the rateswitch signal) gen2 (5 gbps) to gen1 (2.5 gbps) switch (high-to-low transition on the rateswitch signal) figure 1?116. low-speed parallel clock switching in pci express (pipe) 4 mode low-speed parallel clock rateswitch pipephydonestatus[3] pipephydonestatus[0] t1 t1 250 mhz (gen1) 500 mhz (gen2) 250 mhz (gen1)
chapter 1: hardcopy iv gx transceiver architecture 1?145 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 as a result of the signaling rateswitch between gen1 (2.5 gbps) and gen2 (5 gbps), the core fabric-transceiver interface clock switches between 125 mhz and 250 mhz. the core fabric-transceiver interface clock clocks the read side and write side of the transmitter phase compensation fifo and the receiver phase compensation fifo of all bonded channels, respectively. it is also routed to the core fabric on a global or regional clock resource and looped back to clock the write port and read port of the transmitter phase compensation fifo and the receiver phase compensation fifo, respectively. due to the routing delay between the write and read clock of the transmitter and receiver phase compensation fifos, the write pointers and read pointers might collide during a rateswitch between 125 mhz and 250 mhz. to avoid collision of the phase compensation fifo pointers, the pci express (pipe) rateswitch controller automatically disables and resets the phase compensation fifo pointers of all bonded channels during clock switch. when the pipe clock switch circuitry in the local clock divider indicates successful clock switch completion, the pipe rateswitch controller releases the phase compensation fifo pointer resets.
1?146 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation dynamic switch between gen1 (2.5 gbps) and gen2 (5 gbps) signaling rates in pci express (pipe) 8 mode figure 1?117 shows the pci express (pipe) rateswitch circuitry in pipe 8 mode configured at gen2 (5 gbps) data rate. figure 1?117. dynamic switch signaling in pci express (pipe) 8 mode /m /2 rx_datain rx_cruclk rx_locktorefclk rx_lockt odata signal detect rx_freqlocked clock and data recovery [cdr] unit serial recovered clock parallel recovered clock 0 1 high-speed serial clock to the eight bonded channels in the master and slave transceiver blocks transceiver pcs rateswitch cmu 0 clock divider /1, /2, /4 /1, /2, /4 4, /5, /8, /10 4, /5, /8, /10 cmu 1_pll cmu 1 clock divider cmu 1_channel core fabric low-speed parallel clock to the eight bonded channels in the master and slave transceiver blocks phase detector (pd) phase frequency detector (pfd) phase detector (pd) charge pump + loop filter charge pump + loop filter /2 /2 vco vco /l /l /m /2 rx_datain rx_cruclk ltr/ltd controller ltr/ltd controller rx_locktorefclk rx_lockt odata signal detect rx_freqlocked clock and data recovery [cdr] unit serial recovered clock parallel recovered clock 0 1 rateswitch_asn rateswitch_asn pipe interface pipe interface pipe interface transceiver pcs pipe interface pipe interface receiver phase comp fifo receiver phase comp fifo transceiver phase comp fifo transceiver phase comp fifo pipephydonestatus [7:4] pipephydonestatus [3:0] reset_int reset_int reset_int reset_int slave transceiver block master transceiver block cmu 0_channel pci express clock switch circuitry pcie_gen2switch pcie_gen2switch pcie_gen2switch pcie_gen2switch_done pci express clock switch circuitry /1, /2, /4 /1, /2, /4 phase frequency detector (pfd) pci express rate switch controller ccu cmu 0_pll
chapter 1: hardcopy iv gx transceiver architecture 1?147 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 in pci express (pipe) 8 mode configured at 5 gbps data rate, when the pipe rateswitch controller sees a transition on the rateswitch signal, it sends the pcie_gen2switch control signal to the pipe clock switch circuitry in the cmu0 clock divider of the master transceiver block and the receiver cdr in all eight bonded channels to switch to the instructed signaling rate. a low-to-high transition on the rateswitch signal initiates a gen1 (2.5 gbps) to gen2 (5 gbps) signaling rateswitch. a high-to-low transition on the rateswitch signal initiates a gen2 (5 gbps) to gen1 (2.5 gbps) signaling rateswitch. table 1?40 shows the transceiver clock frequencies when switching between 2.5 gbps and 5 gbps signaling rates. the pipe clock switch circuitry in the cmu0 clock divider of the master transceiver block performs the clock switch between 250 mhz and 500 mhz on the low-speed parallel clock when switching between gen1 (2.5 gbps) and gen2 (5 gbps) signaling rates. it indicates successful completion of clock switch on the pcie_gen2switchdone signal to the pipe rateswitch controller. the pipe rateswitch controller forwards the clock switch completion status to the pipe interface block. the pipe interface block communicates the clock switch completion status to the phy-mac layer by asserting the pipephydonestatus signal of all eight bonded channels for one parallel clock cycle. figure 1?118 shows the low-speed parallel clock switch between gen1 (250 mhz) and gen2 (500 mhz) in response to the change in the logic level on the rateswitch signal. the rateswitch completion is shown marked with a one clock cycle assertion of the pipephydonestatus signal of all eight bonded channels. table 1?40. transceiver clock frequencies signaling rates in pci express (pipe) 8 mode transceiver clocks gen1 (2.5 gbps) to gen 2 (5 gbps) switch (low-to-high transition on the rateswitch signal) gen2 (5 gbps) to gen1 (2.5 gbps) switch (high-to-low transition on the rateswitch signal) high-speed serial clock 1.25 ghz to 2.5 ghz 2.5 ghz to 1.25 ghz low-speed parallel clock 250 mhz to 500 mhz 500 mhz to 250 mhz serial recovered clock 1.25 ghz to 2.5 ghz 2.5 ghz to 1.25 ghz parallel recovered clock 250 mhz to 500 mhz 500 mhz to 250 mhz core fabric-transceiver interface clock 125 mhz to 250 mhz 250 mhz to 125 mhz
1?148 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation as a result of the signaling rateswitch between gen1 (2.5 gbps) and gen2 (5 gbps), the core fabric-transceiver interface clock switches between 125 mhz and 250 mhz. the core fabric-transceiver interface clock clocks the read side and write side of the transmitter phase compensation fifo and the receiver phase compensation fifo of all eight bonded channels, respectively. it is also routed to the core fabric on a global or regional clock resource and looped back to clock the write port and read port of the transmitter phase compensation fifo and the receiver phase compensation fifo, respectively. due to the routing delay between the write and read clock of the transmitter and receiver phase compensation fifos, the write pointers and read pointers might collide during a rateswitch between 125 mhz and 250 mhz. to avoid collision of the phase compensation fifo pointers, the pipe rateswitch controller automatically disables and resets the phase compensation fifo pointers of all eight bonded channels during clock switch. when the pipe clock switch circuitry in the local clock divider indicates successful clock switch completion, the pipe rateswitch controller releases the phase compensation fifo pointer resets. pci express (pipe) cold reset requirements the pipe base specification 2.0 defines the following three types of conventional resets to the pipe system components: perst# . the pipe base specification 2.0 specifies that perst# must be kept asserted for a minimum of 100 ms ( tpvperl ) after the system power becomes stable in a cold reset situation. additionally, all system components must enter the ltssm detect state within 20 ms and the link must become active within 100 ms after de-assertion of the perst# signal. this implies that each pipe system component must become active within 200 ms after the power becomes stable. figure 1?118. low-speed parallel clock switching in pci express (pipe) 8 mode (note 1) note to figure 1?118 : (1) time t1 from a transition on the rateswitch signal to the assertion of pipephydonestatus is pending characterization. t1 low-speed parallel clock rateswitch pipephydonestatus[7] pipephydonestatus[0] 250 mhz (gen1) 500 mhz (gen2) 250 mhz (gen1) t1
chapter 1: hardcopy iv gx transceiver architecture 1?149 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 1 the link being active is interpreted as the physical layer device coming out of electrical idle in the l0 state of the ltssm state machine. figure 1?119 shows the pci express (pipe) cold reset timing requirements. the time taken by a pci express (pipe) port implemented using the hardcopy iv gx device to go from power up to link active state is described below: power-on reset?begins after power rails become stable. typically takes 12 ms time taken from de-assertion of perst# to link active?typically takes 40 ms (pending characterization and verification of pipe soft ip and hard ip) xaui mode xaui is an optional, self-managed interface that you can insert between the reconciliation sublayer and the phy layer to transparently extend the physical reach of the xgmii. xaui addresses several physical limitations of the xgmii. xgmii signaling is based on the hstl class 1 single-ended i/o standard, which has an electrical distance limitation of approximately 7 cm. because xaui uses a low-voltage differential signaling method, the electrical limitation is increased to approximately 50 cm. another advantage of xaui is simplification of backplane and board trace routing. xgmii is composed of 32 transmit channels, 32 receive channels, 1 transmit clock, 1 receive clock, 4 transmitter control characters, and 4 receive control characters for a 74-pin wide interface. xaui, on the other hand, only consists of 4 differential transmitter channels and 4 differential receiver channels for a 16-pin wide interface. this reduction in pin count significantly simplifies the routing process in the layout design. figure 1?119. pci express (pipe) cold reset requirements 12 4 3 power rail perst# t pvperl 100 ms t 2-3 d" 20 ms t 2-4 d" 100 ms marker 1: power becomes stable marker 2: perst# gets de-asserted marker 3: maximum time for marker 2 fo r the ltssm to enter the detect state marker 4: maximum time for marker 2 fo r the link to become active
1?150 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation figure 1?120 shows the relationships between the xgmii and xaui layers. the xgmii interface consists of four lanes of 8 bits. at the transmit side of the xaui interface, the data and control characters are converted within the xgxs into an 8b/10b encoded data stream. each data stream is then transmitted across a single differential pair running at 3.125 gbps (3.75 gbps for higig). at the xaui receiver, the incoming data is decoded and mapped back to the 32-bit xgmii format. this provides a transparent extension of the physical reach of the xgmii and also reduces the interface pin count. in hardcopy iv gx xaui functional mode, the interface between the transceiver and core fabric is 64 bits wide (four channels of 16 bits each) at single data rate. xaui functions as a self-managed interface because code group synchronization, channel deskew, and clock domain decoupling is handled with no upper layer support requirements. this functionality is based on the pcs code groups that are used during the ipg time and idle periods. pcs code groups are mapped by the xgxs to xgmii characters, as specified in table 1?41 . figure 1?120. xaui and xgmii layers osi reference model layers application presentation session transport network data link physical pma pmd medium 10 gb/s optional xgmii extender physical layer device mac control (optional) logical link control (llc) lan carrier sense multiple access/collision detect (csma/cd) layers higher layers reconciliation media access control (mac) pcs 10 gigabit media independent interface xgmii extender sublayer xgmii extender sublayer 10 gigabit attachment unit interface 10 gigabit media independent interface medium dependent interface table 1?41. xgmii character to pcs code-group mapping (part 1 of 2) xgmii txc xgmii txd (1) pcd code group description 0 00 through ff dxx,y normal data transmission 1 07 k28.0 or k28.3 or k28.5 idle in ||i||
chapter 1: hardcopy iv gx transceiver architecture 1?151 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?121 shows an example of mapping between xgmii characters and the pcs code groups that are used in xaui. the idle characters are mapped to a pseudo-random sequence of /a/, /r/, and /k/ code groups. pcs code groups are sent via pcs ordered sets. pcs ordered sets consist of combinations of special and data code groups defined as a column of code groups. these ordered sets are composed of four code groups beginning in lane 0. table 1?42 lists the defined idle ordered sets (||i||) that are used for the self-managed properties of xaui. 1 07 k28.5 idle in ||t|| 1 9c k28.4 sequence 1f bk 2 7 . 7s t a r t 1f dk 2 9 . 7t e r m i n a t e 1 fe k30.7 error 1 any other value k30.7 invalid xgmii character note to tab l e 1 ?4 1 : (1) the values in the xgmii txd column are in hexadecimal. table 1?41. xgmii character to pcs code-group mapping (part 2 of 2) xgmii txc xgmii txd (1) pcd code group description figure 1?121. example of mapping xgmii characters to pcs code groups dp t/rxd<7..0> |s ddd - - - - - - - - - - - - d dp t/rxd<15..8> |dp ddd t dp t/rxd<23..16> |dp ddd | dp t/rxd<31..24> | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dp ddd ddd ddd ddd ddd | lane 0 k r s ak rr lane 1 k r dp ak rr lane 2 k r k a k rr lane 3 k r k a k k k k k r r r r rr dp ddd - - - - - - - - - - - - d dp ddd t dpdp dd dpdp d d dd ddd ddd ddd ddd xgmii pcs table 1?42. defined idle ordered set code ordered set number of code groups encoding ||i|| idle substitute for xgmii idle ||k|| synchronization column 4 /k28.5/k28.5/k28.5/k28.5/ ||r|| skip column 4 /k28.0/k28.0/k28.0/k28.0/ ||a|| align column 4 /k28.3/k28.3/k28.3/k28.3/
1?152 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation hardcopy iv gx transceivers configured in xaui mode provide the following protocol features:
chapter 1: hardcopy iv gx transceiver architecture 1?153 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?122 shows the xaui mode configuration supported in hardcopy iv gx devices. figure 1?122. hardcopy iv gx xaui mode configuration xaui disabled enabled rate match fifo byte serdes byte ordering hardcopy iv gx configurations basic single width double width functional modes protocol pipe xaui gige srio sonet /sdh (oif) cei sdi 8-bit 10-bit 16-bit 20-bit 10-bit 10-bit 10-bit 10-bit 8-bit 16-bit 10-bit enabled enabled channel bonding disabled deskew fifo enabled pma-pcs interface width functional mode data rate (gbps) low-latency pcs word aligner (pattern length) 8b/10b encoder/decoder core fabric-transceiver interface width core fabric-transceiver interface frequency (mhz) 156.25 - 187.5 16-bit automatic synchronization state machine (10-bit/k28.5/) x4 3.125 - 3.75
1?154 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation xaui m ode datapath figure 1?123 shows the altgx megafunction transceiver datapath when configured in xaui mode. figure 1?123. transceiver datapath in xaui mode rx phase compensation fifo byte de- serializer de- serializer cdr /2 ch0 parallel recovered clock low-speed parallel clock from cmu 0 clock divider receiver channel pma receiver channel pcs core fabric tx_coreclk[3:2] /2 ch0 parallel recovered clock ch2 parallel recovered clock low-speed parallel clock from cmu 0 clock divider rx_coreclk[3:2] rx_coreclk[1:0] /2 coreclkout cmu1_pll cmu0_pll cmu1_channel cmu0_channel cmu0 clock divider low-s peed parallel clock input reference clock core fabric-transceiver interface clock receiver channel pma cmu1 clock divider serializer transmitter channel pcs transmitter channel pma /2 wrclk wrclk rdclk rdclk low-s peed parallel clock from cmu 0 click divider receiver channel pcs tx_coreclk[1:0] tx phase compensation fifo byte serializer 8b/10b encoder serializer transmitter channel pcs transmitter channel pma /2 wrclk wrclk rdclk rdclk low-sp eed parallel clock from cmu 0 clock divider high-speed serial clock channel 0 channel 1 channel 2 channel 3 channel 2 channel 3 channel 0 channel 1 ch0 parallel recovered clock word aligner deskew fifo rate match fifo 8b/10b decoder input reference clock rx phase compensation fifo byte de- serializer 8b/10b decoder rate match fifo deskew fifo word aligner de- serializer cdr 8b/10b encoder byte serializer tx phase compensation fifo
chapter 1: hardcopy iv gx transceiver architecture 1?155 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 xgmii-to-pcs code conversion at the transmitter in xaui mode, the 8b/10b encoder in the hardcopy iv gx transmitter datapath is controlled by a transmitter state machine that maps various 8-bit xgmii codes to 10-bit pcs code groups. this state machine complies with the ieee p 802.3ae pcs transmit source state diagram shown in figure 1?124 . figure 1?124. xgmii-to-pcs code conversion in xaui mode (note 1) note to figure 1?124 : (1) this figure is from ieee p802.3ae. send_random_k tx_code_group<39:0> ? ||k|| send_random_r tx_code_group<39:0> ? ||r|| send_random_a tx_code_group<39:0> ? ||a|| a_cnt 0 * cod_sel=1 a_cnt 0 * cod_sel=1 a_cnt 0 * cod_sel=1 a_cnt=0 a_cnt=0 a_cnt 0 * cod_sel=1 !q_det * cod_sel=1 q_det q_det !q_det !q_det * cod_set=1 a b b b a a b a cod_set=1 cod_set=1 b a pudr send_k tx_code_group<39:0> ? ||k|| next_ifg ? a (next_ifg + a_cnt 0) next_ifg = a_cnt 0 pudr send_a tx_code_group<39:0> ? ||a|| next_ifg ? k send_q tx_code_group<39:0> ? tqmsg q_det ? k pudr pudr send_q if tx=||t|| then cvtx_terminate tx_code_group<39:0> ? encode(tx) !reset !(tx=||idle|| + tx=||q|| pudr pudr send_random_q tx_code_group<39:0> ? tqmsg q_det ? false pudr reset uct uct
1?156 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation table 1?43 lists the xgmii-to-pcs code group conversion in xaui functional mode. the xgmii txc control signal is equivalent to the tx_ctrlenable signal; the xgmii txd control signal is equivalent to the tx_datain[7:0] signal. pcs-to-xgmii code conversion at the receiver in xaui mode, the 8b/10b decoder in the hardcopy iv gx receiver datapath is controlled by a xaui receiver state machine that converts received pcs code groups into specific 8-bit xgmii codes. this state machine complies with the ieee p802.3ae specifications. table 1?44 lists the pcs-to-xgmii code group conversion in xaui functional mode. the xgmii rxc control signal is equivalent to the rx_ctrldetect signal; the xgmii rxd control signal is equivalent to the rx_dataout[7:0] signal. table 1?43. xgmii character to pcs code-group mapping xgmii txc xgmii txd (1) pcd code group description 0 00 through ff dxx,y normal data transmission 1 07 k28.0 or k28.3 or k28.5 idle in ||i|| 1 07 k28.5 idle in ||t|| 1 9c k28.4 sequence 1f bk 2 7 . 7s t a r t 1f dk 2 9 . 7t e r m i n a t e 1 fe k30.7 error 1 any other value k30.7 invalid xgmii character note to tab l e 1 ?4 1 : (1) the values in the xgmii txd column are in hexadecimal. table 1?44. pcs code group to xgmii character mapping xgmii rxc xgmii rxd (1) pcd code group description 0 00 through ff dxx,y normal data transmission 1 07 k28.0 or k28.3 or k28.5 idle in ||i|| 1 07 k28.5 idle in ||t|| 1 9c k28.4 sequence 1f bk 2 7 . 7s t a r t 1f dk 2 9 . 7t e r m i n a t e 1f ek 3 0 . 7e r r o r 1 fe invalid code group received code group note to tab l e 1 ?4 1 : (1) the values in the xgmii rxd column are in hexadecimal.
chapter 1: hardcopy iv gx transceiver architecture 1?157 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 word aligner the word aligner in xaui functional mode is configured in automatic synchronization state machine mode. the quartus ii software automatically configures the synchronization state machine to indicate synchronization when the receiver receives four /k28.5/ comma code groups without intermediate invalid code groups. the synchronization state machine implemented in xaui mode is compliant to the pcs synchronization state diagram specified in clause 48 of the ieee p802.3ae specification and is shown in figure 1?125 . figure 1?125. ieee 802.3ae pcs synchronization state diagram (note 1) note to figure 1?125 : (1) this figure is from ieee p802.3ae. power_on=true+mr_main_rest=true + (signal_detectchange=true + mr_loopback=false +pudi) (signal_detect=ok+mr_loopback=true)* * pudi([/comma/] pudi([/|dv|/] rx_even=false+pudi([/comma/] pudi(![/comma/] *? [/invalid/] pudi([/|dv|/] cggood *good_cgs = 3 cggood *good_cgs = 3 cggood *good_cgs = 3 cggood *good_cgs = 3 cggood cggood pudi(![/|dv|/] pudi(![/|dv|/] [pudi * signal_detect=fail + mr_loopback=false] + pudi(![/comma/]) loss_of_sync sync_status ? fail rx_even ? ! rx_even sudi comma_detect_1 rx_even ? true sudi sync_acquired_2 rx_even ? ! rx_even sudi good_cgs ? 0 sync_acquired_3 sync_acquired_4 cgbad cgbad cggood cgbad cgbad cggood cgbad cgbad cgbad sync_acquired_2a sync_acquired_3a sync_acquired_4a acquire_sync_1 sudi comma_detect_2 sudi 2 cggood *good_cgs = 3 cggood *good_cgs = 3 3 3 2 pudi(![/comma/] *? [/invalid/] rx_even ? true rx_even=false+pudi([/comma/] cgbad cgbad acquire_sync_2 sudi rx_even ? ! rx_even pudi(![/|dv|/] comma_detect_3 sudi rx_even ? true pudi([/|dv|/] sync_acquired_1 sudi sync_status ? ok rx_even ? ! rx_even rx_even ? ! rx_even rx_even ? ! rx_even sudi good_cgs ? good_cgs + 1 rx_even ? ! rx_even sudi good_cgs ? 0 rx_even ? ! rx_even sudi good_cgs ? good_cgs + 1 rx_even ? ! rx_even sudi good_cgs ? 0 rx_even ? ! rx_even sudi good_cgs ? good_cgs + 1
1?158 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation receiver synchronization is indicated on the rx_syncstatus port of each channel. a high on the rx_syncstatus port indicates that the lane is synchronized; a low on the rx_syncstatus port indicates that it has fallen out of synchronization. the receiver loses synchronization when it detects four invalid code groups separated by less than four valid code groups or when it is reset. deskew fifo code groups received across four lanes in a xaui link can be misaligned with respect to one another because of skew in the physical medium or differences between the independent clock recoveries per lane. the xaui protocol allows a maximum skew of 40 ui (12.8 ns) as seen at the receiver of the four lanes. the xaui protocol requires the physical layer device to implement a deskew circuitry to align all four channels. to enable the deskew circuitry at the receiver to align the four channels, the transmitter sends a /a/ (/k28.3/) code group simultaneously on all four channels during inter-packet gap. the skew introduced in the physical medium and the receiver channels can be /a/ code groups to be received misaligned with respect to each other. the deskew operation is performed by the deskew fifo in xaui functional mode. the deskew fifo in each channel receives data from its word aligner. the deskew operation begins only after link synchronization is achieved on all four channels as indicated by a high on the rx_syncstatus signal from the word aligner in each channel. until the first /a/ code group is received, the deskew fifo read and write pointers in each channel are not incremented. after the first /a/ code group is received, the write pointer starts incrementing for each word received but the read pointer is frozen. if the /a/ code group is received on each of the four channels within 10 recovered clock cycles of each other, the read pointer of all four deskew fifos is released simultaneously, aligning all four channels. figure 1?126 shows lane skew at the receiver input and how the deskew fifo uses the /a/ code group to align the channels. figure 1?126. receiver input lane skew in xaui mode lanes are deskewed by lining up the "align"/a/, code groups lane skew at receiver input a lane 0 k k r a k r r k k k rr lane 1 k k r a k r r k k k rr lane 0 k k r k r r k k k rr lane 1 k k r a k r r k k k rr lane 2 k k r a k r r k k k rr lane 3 k k r a k r r k k k rr lane 2 k k r a k r r k k k rr lane 3 k k r a k r r k k k rr
chapter 1: hardcopy iv gx transceiver architecture 1?159 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 after alignment of the first ||a|| column, if three additional aligned ||a|| columns are observed at the output of the deskew fifos of the four channels, the rx_channelaligned signal is asserted high, indicating channel alignment is acquired. after acquiring channel alignment, if four misaligned ||a|| columns are seen at the output of the deskew fifos in all four channels with no aligned ||a|| columns in between, the rx_channelaligned signal is de-asserted low, indicating loss-of-channel alignment. the deskew fifo operation in xaui functional mode is compliant with the pcs deskew state machine diagram specified in clause 48 of the ieee p 802.3ae, as shown in figure 1?127 . figure 1?127. deskew fifo in xaui mode (note 1) note to figure 1?127 : (1) this figure is from ieee p802.3ae. reset + (sync_status=fail * sudi) sync_status ok * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) sudi(![/||a||/]) sudi(![/||a||/]) sudi(![/||a||/]) deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi deskew_error * sudi sudi(![/||a||/]) loss_of_alignment align_status ? fail enable_deskew ? true audi align_detect_1 enable_deskew ? false audi align_detect_2 audi align_detect_3 audi c !deskew_error * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) !deskew_error * sudi(![/||a||/]) sudi(![/||a||/]) align_acquired_1 enable_deskew ? false audi align_acquired_2 audi align_acquired_3 audi a b c !deskew_error * sudi(![/||a||/]) sudi(![/||a||/]) align_acquired_4 audi b sudi(![/||a||/]) a sudi(![/||a||/])
1?160 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation rate match fifo in xaui mode, the rate match fifo is capable of compensating for up to 100 ppm (200 ppm total) difference between the upstream transmitter and the local receiver reference clock. the xaui protocol requires the transmitter to send /r/ (/k28.0/) code groups simultaneously on all four lanes (denoted as ||r|| column) during inter-packet gaps, adhering to rules listed in the ieee p802.3ae specification. the rate match fifo operation in xaui mode is compliant to the ieee p 802.3ae specification. the rate match operation begins after: rx_syncstatus signal high rx_channelaligned signal high the rate match fifo looks for the ||r|| column (simultaneous /r/ code group on all four channels) and deletes or inserts ||r|| column to prevent the rate match fifo from overflowing or under-running. the rate match fifo can insert or delete as many ||r|| columns as necessary to perform the rate match operation. two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted , indicating rate match fifo deletion and insertion events, respectively, are forwarded to the core fabric. if an ||r|| column is deleted, the rx_rmfifodeleted flag from each of the four channels goes high for one clock cycle per deleted ||r|| column. if an ||r|| column is inserted, the rx_rmfifoinserted flag from each of the four channels goes high for one clock cycle per inserted ||r|| column. figure 1?128 shows an example of rate match deletion in the case where three ||r|| columns are required to be deleted. figure 1?128. rate match deletion in xaui mode datain[3] rx_rmfifodatadeleted k28.0 k28.3 k28.5 k28.5 k28.0 k28.0 k28.0 k28.5 first ||r|| column second ||r|| column third ||r|| column fourth ||r|| column k28.5 datain[2] k28.0 k28.3 k28.5 k28.5 k28.0 k28.0 k28.0 k28.5 k28.5 datain[1] k28.0 k28.3 k28.5 k28.5 k28.0 k28.0 k28.0 k28.5 k28.5 datain[0] k28.0 k28.3 k28.5 k28.5 k28.0 k28.0 k28.0 k28.5 k28.5 dataout[3] k28.5 k28.3 k28.5 k28.0 k28.5 k28.5 dataout[2] k28.5 k28.3 k28.5 k28.0 k28.5 k28.5 dataout[1] k28.5 k28.3 k28.5 k28.0 k28.5 k28.5 dataout[0] k28.5 k28.3 k28.5 k28.0 k28.5 k28.5
chapter 1: hardcopy iv gx transceiver architecture 1?161 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?129 shows an example of rate match insertion in the case where two ||r|| columns are required to be inserted. gige mode ieee 802.3 defines the 1000 base-x phy as an intermediate, or transition, layer that interfaces various physical media with the media access control (mac) in a gigabit ethernet system. it shields the mac layer from the specific nature of the underlying medium. the 1000 base-x phy is divided into three sub-layers: figure 1?129. rate match insertion in xaui mode datain[3] rx_rmfifodatadeleted k28.0 k28.3 k28.5 k28.0 k28.0 k28.5 k28.0 first ||r|| column second ||r|| column k28.5 datain[2] k28.0 k28.3 k28.5 k28.0 k28.0 k28.5 k28.0 k28.5 datain[1] k28.0 k28.3 k28.5 k28.0 k28.0 k28.5 k28.0 k28.5 datain[0] k28.0 k28.3 k28.5 k28.0 k28.0 k28.5 k28.0 k28.5 dataout[3] k28.0 k28.3 k28.5 k28.5 k28.0 k28.5 dataout[2] k28.0 k28.3 k28.5 k28.5 k28.0 k28.5 dataout[1] k28.0 k28.3 k28.5 k28.5 k28.0 k28.5 dataout[0] k28.0 k28.3 k28.5 k28.5 k28.0 k28.5
1?162 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation figure 1?130 shows the 1000 base-x phy position in a gigabit ethernet osi reference model. hardcopy iv gx transceivers, when configured in gige functional mode, have built-in circuitry to support the following pcs and pma functions defined in the ieee 802.3 specification: 1 r rcvr v r fr r fc fr c cc crrr f rr fc c rr r r crc figure 1?130. 1000 base-x phy in a gigabit ethernet osi reference model osi reference model layers application presentation session transport network data link physical medium gmii 1000 base-x phy mac (optional) llc lan csma/cd layers higher layers reconciliation mac pcs pma pmd
chapter 1: hardcopy iv gx transceiver architecture 1?163 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?131 shows the gige mode configuration supported in hardcopy iv gx devices. figure 1?131. gige mode gige disabled enabled rate match fifo byte serdes byte ordering hardcopy iv gx configurations basic single width double width functional modes protocol pipe xaui gige srio sonet /sdh (oif) cei sdi 8-bit 10-bit 16-bit 20-bit 10-bit 10-bit 10-bit 10-bit 8-bit 16-bit 10-bit functional mode enabled disabled channel bonding disabled 125 pma-pcs interface width data rate (gbps) low-latency pcs word aligner (pattern length) 8b/10b encoder/decoder core fabric-transceiver interface width core fabric-transceiver interface frequency (mhz) 8-bit 1.25 x1 automatic synchronization state machine (7-bit comma, 10-bit /k28.5/)
1?164 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation gige mode datapath figure 1?132 shows the transceiver datapath when configured in gige functional mode. table 1?45 shows the transceiver datapath clock frequencies in gige functional mode. 8b/10b encoder in gige mode, the 8b/10b encoder clocks in 8-bit data and 1-bit control identifiers from the transmitter phase compensation fifo and generates 10-bit encoded data. the 10-bit encoded data is fed to the serializer. for more information about 8b/10b encoder functionality, refer to ?8b/10b encoder? on page 1?40 . gige protocol?ordered sets and special code groups table 1?46 lists ordered sets and special code groups specified in the ieee 802.3 specification. figure 1?132. gige mode datapath tx phase compensation fifo 8b/10b encoder 8b/10b decoder serializer de- serializer transmitter channel pcs transmitter channel pma wrclk rdclk low-speed parallel clock high-sp eed serial cloc k tx_coreclk[0] rx phase compensation fifo rate match fifo word aligner cdr tx_clkout[0] parallel recovered clock low-speed parallel clock rx_coreclk[0] receiver channel pcs receiver channel pma core fabric-transceiver interface clock core fabric local clock divider table 1?45. transceiver datapath clock frequencies in gige mode functional mode data rate high-speed serial clock frequency parallel recovered clock and low-speed parallel clock frequency core fabric-transceiver interface clock frequency gige 1.25 gbps 625 mhz 125 mhz 125 mhz table 1?46. gige ordered sets (part 1 of 2) code ordered set number of code groups encoding /c/ configuration ? alternating /c1/ and /c2/ /c1/ configuration 1 4 /k28.5/d21.5/ config_reg (1) /c2/ configuration 2 4 /k28.5/d2.2/ config_reg (1) /i/ idle ? correcting /i1/, preserving /i2/
chapter 1: hardcopy iv gx transceiver architecture 1?165 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 idle ordered-set generation the ieee 802.3 specification requires the gige phy to transmit idle ordered sets (/i/) continuously and repetitively whenever the gmii is idle. this ensures that the receiver maintains bit and word synchronization whenever there is no active data to be transmitted. in gige functional mode, any /dx.y/ following a /k28.5/ comma is replaced by the transmitter with either a /d5.6/ (/i1/ ordered set) or a /d16.2/ (/i2/ ordered set), depending on the current running disparity. the exception is when the data following the /k28.5/ is /d21.5/ (/c1/ ordered set) or /d2.2/ (/c2/) ordered set. if the running disparity before the /k28.5/ is positive, an /i1/ ordered set is generated. if the running disparity is negative, a /i2/ ordered set is generated. the disparity at the end of a /i1/ is the opposite of that at the beginning of the /i1/. the disparity at the end of a /i2/ is the same as the beginning running disparity (right before the idle code). this ensures a negative running disparity at the end of an idle ordered set. a /kx.y/ following a /k28.5/ is not replaced. 1 note that /d14.3/, /d24.0/, and /d15.8/ are replaced by /d5.6/ or /d16.2/ (for /i1/, /i2/ ordered sets). /d21.5/ (part of the /c1/ order set) is not replaced. figure 1?133 shows the automatic idle ordered set generation. reset condition after de-assertion of tx_digitalreset , the gige transmitter automatically transmits three /k28.5/ comma code groups before transmitting user data on the tx_datain port. this could affect the synchronization state machine behavior at the receiver. /i1/ idle 1 2 /k28.5/d5.6 /i2/ idle 2 2 /k28.5/d16.2 encapsulation ? ? /r/ carrier_extend 1 /k23.7/ /s/ start_of_packet 1 /k27.7/ /t/ end_of_packet 1 /k29.7/ /v/ error_propagation 1 /k30.7/ note to tab l e 1 ?4 6 : (1) two data code groups representing the config_reg value. table 1?46. gige ordered sets (part 2 of 2) code ordered set number of code groups encoding figure 1?133. automatic ordered set generation k28.5 d14.3 k28.5 d24.0 k28.5 d15.8 k28.5 d21.5 tx_datain [ ] clock dx.y dx.y k28.5 d5.6 k28.5 d16.2 k28.5 d16.2 k28.5 tx_dataout ordered set d21.5 /i1/ /i2/ /i2/ /c2/
1?166 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation depending on when you start transmitting the synchronization sequence, there could be an even or odd number of /dx.y/ code groups transmitted between the last of the three automatically sent /k28.5/ code groups and the first /k28.5/ code group of the synchronization sequence. if there is an even number of /dx.y/ code groups received between these two /k28.5/ code groups, the first /k28.5/ code group of the synchronization sequence begins at an odd code group boundary ( rx_even = false). an ieee802.3-compliant gige synchronization state machine treats this as an error condition and goes into the loss of sync state. figure 1?134 shows an example of even numbers of /dx.y/ between the last automatically sent /k28.5/ and the first user-sent /k28.5/. the first user-sent /k28.5/ code group received at an odd code group boundary in cycle n + 3 takes the receiver synchronization state machine in the loss of sync state. the first synchronization ordered set /k28.5/dx.y/ in cycles n + 3 and n + 4 is discounted and three additional ordered sets are required for successful synchronization. word aligner the word aligner in gige functional mode is configured in automatic synchronization state machine mode. the quartus ii software automatically configures the synchronization state machine to indicate synchronization when the receiver receives three consecutive synchronization ordered sets. a synchronization ordered set is a /k28.5/ code group followed by an odd number of valid /dx.y/ code groups. the fastest way for the receiver to achieve synchronization is to receive three continuous {/k28.5/, /dx.y/} ordered sets. receiver synchronization is indicated on the rx_syncstatus port of each channel. a high on the rx_syncstatus port indicates that the lane is synchronized; a low on the rx_syncstatus port indicates that the lane has fallen out of synchronization. the receiver loses synchronization when it detects four invalid code groups separated by less than three valid code groups or when it is reset. table 1?47 lists the synchronization state machine parameters when configured in gige mode. figure 1?134. reset condition in gige mode clock tx_dataout tx_digitalreset k28.5 k28.5 k28.5 k28.5 xxx dx.y dx.y k28.5 k28.5 k28.5 dx.y dx.y dx.y n n + 1 n + 2 n + 3 n + 4 table 1?47. synchronization state machine parameters in gige functional mode synchronization state machine parameters setting number of valid {/k28.5/, /dx,y/} ordered sets received to achieve synchronization 3 number of errors received to lose synchronization 4 number of continuous good code groups received to reduce the error count by 1 4
chapter 1: hardcopy iv gx transceiver architecture 1?167 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?135 shows the synchronization state machine implemented in gige mode. rate match fifo in gige mode, the rate match fifo is capable of compensating for up to 100 ppm (200 ppm total) difference between the upstream transmitter and the local receiver reference clock. the gige protocol requires the transmitter to send idle ordered sets /i1/ (/k28.5/d5.6/) and /i2/ (/k28.5/d16.2/) during inter-packet gaps adhering to the rules listed in the ieee 802.3 specification. the rate match operation begins after the synchronization state machine in the word aligner indicates synchronization is acquired by driving the rx_syncstatus signal high. the rate matcher deletes or inserts both symbols (/k28.5/ and /d16.2/) of the /i2/ ordered sets, even if it requires deleting only one symbol to prevent the rate match fifo from overflowing or under-running. it can insert or delete as many /i2/ ordered sets as necessary to perform the rate match operation. figure 1?135. synchronization state machine in gige mode (note 1) note to figure 1?135 : (1) this figure is from ieee p802.3ae. power_on=true+mr_main_rest=true + (signal_detectchange=true + mr_loopback=false +pudi) (signal_detect=ok+mr_loopback=true)* * pudi([/comma/] pudi([/|dv|/] rx_even=false+pudi([/comma/] pudi(![/comma/] *? [/invalid/] pudi([/|dv|/] cggood *good_cgs = 3 cggood *good_cgs = 3 cggood *good_cgs = 3 cggood *good_cgs = 3 cggood cggood pudi(![/|dv|/] pudi(![/|dv|/] [pudi * signal_detect=fail + mr_loopback=false] + pudi(![/comma/]) loss_of_sync sync_status ? fail rx_even ? ! rx_even sudi comma_detect_1 rx_even ? true sudi sync_acquired_2 rx_even ? ! rx_even sudi good_cgs ? 0 sync_acquired_3 sync_acquired_4 cgbad cgbad cggood cgbad cgbad cggood cgbad cgbad cgbad sync_acquired_2a sync_acquired_3a sync_acquired_4a acquire_sync_1 sudi comma_detect_2 sudi 2 cggood *good_cgs = 3 cggood *good_cgs = 3 3 3 2 pudi(![/comma/] *? [/invalid/] rx_even ? true rx_even=false+pudi([/comma/] cgbad cgbad acquire_sync_2 sudi rx_even ? ! rx_even pudi(![/|dv|/] comma_detect_3 sudi rx_even ? true pudi([/|dv|/] sync_acquired_1 sudi sync_status ? ok rx_even ? ! rx_even rx_even ? ! rx_even rx_even ? ! rx_even sudi good_cgs ? good_cgs + 1 rx_even ? ! rx_even sudi good_cgs ? 0 rx_even ? ! rx_even sudi good_cgs ? good_cgs + 1 rx_even ? ! rx_even sudi good_cgs ? 0 rx_even ? ! rx_even sudi good_cgs ? good_cgs + 1
1?168 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted , indicating rate match fifo deletion and insertion events, respectively, are forwarded to the core fabric. both the rx_rmfifodatadeleted and rx_rmfifodatainserted flags are asserted for two clock cycles for each deleted and inserted /i2/ ordered set, respectively. figure 1?136 shows an example of rate match fifo deletion in the case where three symbols are required to be deleted. because the rate match fifo can only delete /i2/ ordered set, it deletes two /i2/ ordered sets (four symbols deleted). figure 1?137 shows an example of rate match fifo insertion in the case where one symbol is required to be inserted. because the rate match fifo can only delete /i2/ ordered set, it inserts one /i2/ ordered set (two symbols inserted). sonet/sdh mode sonet/sdh is one of the most common serial-interconnect protocols used in backplanes deployed in communications and telecom applications. sonet/sdh defines various optical carrier (oc) sub-pr otocols for carrying signals of different capacities through a synchronous optical hierarchy. sonet/sdh frame structure base oc-1 frames are byte-interleaved to form sonet/sdh frames. for example, 12 oc-1 frames are byte-interleaved to form one oc-12 frame; 48 oc-1 frames are byte-interleaved to form one oc-48 frame, and so on. sonet/sdh frame sizes are constant, with a frame transfer rate of 125 . figure 1?136. rate match deletion in gige mode datain dataout rx_rmfifodatadeleted first /i2/ skip ordered set dx.y k28.5 k28.5 second /i2/ skip ordered set /i2/ skip symbol deleted d16.2 d16.2 k28.5 d16.2 dx.y third /i2/ skip ordered set dx.y k28.5 d16.2 dx.y figure 1?137. rate match insertion in gige mode datain dataout rx_rmfifodatainserted first /i2/ ordered set dx.y k28.5 k28.5 second /i2/ ordered set d16.2 d16.2 dx.y k28.5 d16.2 d16.2 dx.y k28.5 d16.2 k28.5
chapter 1: hardcopy iv gx transceiver architecture 1?169 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?138 shows the sonet/sdh frame structure. transport overhead bytes a1 and a2 are used for restoring frame boundary from the serial data stream. frame sizes are fixed, so the a1 and a2 bytes appear within the serial data stream every 125 . 2 , 2 2 2 . , 4 , 4 4 2 . , 2 figure 1?138. sonet/sdh mode nxa1 nxa2 nxj0/z0 9 rows nx3 bytes transport overhead nx3 bytes payload
1?170 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation figure 1?139 shows sonet/sdh mode configurations supported in hardcopy iv gx devices. figure 1?139. sonet/sdh mode configurations in hardcopy iv devices disabled disabled rate match fifo byte serdes byte ordering hardcopy iv gx configurations basic single width double width functional modes protocol pipe xaui gige srio sonet /sdh (oif) cei sdi 8-bit 10-bit 16-bit 20-bit 10-bit 10-bit 10-bit 10-bit 8-bit 16-bit 10-bit functional mode disabled disabled disabled disabled disabled enabled disabled enabled pma-pcs interface width data rate (gbps) channel bonding low-latency pcs word aligner (pattern length) 8b/10b encoder/decoder core fabric-transceiver interface width core fabric-transceiver interface frequency (mhz) 8-bit 16-bit 77.75 155.5 manual alignment (16-bit a1a2, 32-bit a1a1a2a2) manual alignment (16-bit a1a2, 32-bit a1a1a2a2) x1 x1 0.622 (oc-12) 2.488 (oc-48) sonet/ sdh disabled disabled disabled enabled disabled 32-bit 155.5 manual alignment (32-bit a1a1a2a2) x1 4.976 (oc-96)
chapter 1: hardcopy iv gx transceiver architecture 1?171 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 sonet/sdh oc-12 datapath figure 1?140 shows the transceiver datapath when configured in sonet/sdh oc-12 mode. sonet/sdh oc-48 datapath figure 1?141 shows the transceiver datapath when configured in sonet/sdh oc-48 mode. figure 1?140. sonet/sdh oc-12 datapath tx phase compensation fifo serializer transmitter channel pcs transmitter channel pma wrclk rdclk low-speed parallel clock high-speed serial clock tx_coreclk rx phase compensation fifo word aligner de- serializer cdr tx_clkout parallel recovered clock rx_coreclk receiver channel pcs receiver channel pma core fabric-transmitter interface clock core fabric local clock divider core fabric-receiver interface clock rx_clkout figure 1?141. sonet/sdh oc-48 datapath tx phase compensation fifo byte serializer serializer transmitter channel pcs transmitter channel pma /2 wrclk rdclk low-speed parallel clock high-speed serial clock tx_coreclk rx phase compensation fifo byte de- serializer word aligner de- serializer cdr wrclk rdclk /2 tx_clkout parallel recovered clock rx_coreclk byte ordering receiver channel pcs receiver channel pma core fabric-transmitter interface clock core fabric core fabric-receiver interface clock rx_clkout local clock divider
1?172 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation sonet/sdh oc-96 datapath figure 1?142 shows the transceiver datapath when configured in sonet/sdh oc-96 mode. sonet/sdh transmission bit order unlike ethernet, where the lsb of the parallel data byte is transferred first, sonet/sdh requires the msb to be transferred first and the lsb to be transferred last. to facilitate the msb-to-lsb transfer, you must enable the following options in the altgx megawizard plug-in manager: flip transmitter input data bits flip receiver output data bits depending on whether data bytes are transferred msb-to-lsb or lsb-to-msb, you must select the appropriate word aligner settings in the altgx megawizard plug-in manager. table 1?48 on page 1?173 lists the correct word aligner settings for each bit transmission order. word alignment the word aligner in sonet/sdh oc-12, oc-48, and oc-96 modes is configured in manual alignment mode, as described in ?word aligner in single-width mode with 8-bit pma-pcs interface modes? on page 1?74 . in oc-12 and oc-48 configurations, you can configure the word aligner to either align to a 16-bit a1a2 pattern or a 32-bit a1a1a2a2 pattern. this is controlled by the rx_a1a2size input port to the transceiver. a low level on the rx_a1a2size port configures the word aligner to align to a 16-bit a1a2 pattern; a high level on the rx_a1a2size port configures the word aligner to align to a 32-bit a1a1a2a2 pattern. in oc-96 configuration, the word aligner is only allowed to align to a a1a1a2a2 pattern, so input port rx_ala2size is unavailable. barring this difference, the oc-96 word alignment operation is similar to that of the oc-12 and oc-48 configurations. figure 1?142. sonet/sdh oc-96 datapath tx phase compensation fifo byte serializer serializer transmitter channel pcs transmitter channel pma /2 wrclk rdclk low-speed parallel clock high-speed serial clock tx_coreclk rx phase compensation fifo byte de- serializer word aligner de- serializer cdr wrclk rdclk /2 tx_clkout parallel recovered clock rx_coreclk receiver channel pcs receiver channel pma core fabric-transmitter interface clock core fabric core fabric-receiver interface clock rx_clkout local clock divider
chapter 1: hardcopy iv gx transceiver architecture 1?173 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 you can configure the word aligner to flip the alignment pattern bits programmed in the megawizard and compare them with the incoming data for alignment. this feature offers flexibility to the sonet backplane system for either a msbit-to-lsbit or lsbit-to-msbit data transfer. table 1?48 lists word alignment patterns that you must program in the altgx megawizard plug-in manager based on the bit-transmission order and the word aligner bit-flip option. the behavior of the sonet/sdh word aligner control and status signals, along with an operational timing diagram, are explained in ?word aligner in single-width mode with 8-bit pma-pcs interface modes? on page 1?74 . oc-48 and oc-96 byte serializer and deserializer the oc-48 and oc-96 transceiver datapath includes the byte serializer and deserializer to allow the pld interface to run at a lower speed. the oc-12 configuration does not use the byte serializer and deserializer blocks. the byte serializer and deserializer blocks are explained in ?byte serializer? on page 1?38 and ?byte deserializer? on page 1?108 , respectively. the oc-48 byte serializer converts 16-bit data words from the core fabric and translates the 16-bit data words into two 8-bit data bytes at twice the rate. the oc-48 byte deserializer takes in two consecutive 8-bit data bytes and translates them into a 16-bit data word to the core fabric at half the rate. the oc-96 byte serializer converts 32-bit data words from the core fabric and translates them into two 16-bit data words at twice the rate. the oc-96 byte deserializer takes in two consecutive 16-bit data words and translates them into a 32-bit data word to the core fabric at half the rate. oc-48 byte ordering because of byte deserialization, the msbyte of a word might appear at the rx_dataout port along with the lsbyte of the next word. in an oc-48 configuration, the byte ordering block is built into the datapath and can be leveraged to perform byte ordering. byte ordering in an oc-48 configuration is automatic, as explained in ?word-alignment-based byte ordering? on page 1?113 . in automatic mode, the byte ordering block is triggered by the rising edge of the rx_syncstatus signal. as soon as the byte ordering block sees the rising edge of the rx_syncstatus signal, it compares the lsbyte coming out of the byte deserializer with the a2 byte of the a1a2 alignment pattern. if the lsbyte coming out of the byte deserializer does not match the a2 byte set in the altgx megawizard plug-in manager, the byte ordering block inserts a pad character, as seen in figure 1?143 . insertion of this pad character enables the byte ordering block to restore the correct byte order. table 1?48. word aligner settings serial bit transmission order word alignment bit flip word alignment pattern msbit-to-lsbit on 1111011000101000 (16'hf628) msbit-to-lsbit off 0001010001101111 (16'h146f) lsbit-to-msbit off 0010100011110110 (16'h28f6)
1?174 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation 1 the pad character is defaulted to the a1 byte of the a1a2 alignment pattern. sdi mode the society of motion picture and television engineers (smpte) defines various sdi standards for transmission of uncompressed video. the following three smpte standards are popular in video broadcasting applications: smpte 259m standard?more popularly known as the standard-definition (sd) sdi, is defined to carry video data at 270 mbps smpte 292m standard?more popularly known as the high-definition (hd) sdi, is defined to carry video data at either 1485 mbps or 1483.5 mbps smpte 424m standard?more popularly known as the third-generation (3g) sdi, is defined to carry video data at either 2970 mbps or 2967 mbps you can configure hardcopy iv gx transceivers in hd-sdi or 3g-sdi configuration using the altgx megawizard plug-in manager. table 1?49 shows altgx configurations supported by hardcopy iv gx transceivers in sdi mode. figure 1?143. oc-48 byte ordering in automatic mode x x pad from byte deserializer rx_dataout (msb) rx_dataout (lsb) rx_clkout rx_syncstatus a1 a1 a1 a1 a2 a2 a2 a2 d0 d2 d1 byte ordering block rx_syncstatus rx_byteorderalignstatus to pld core a1 a1 a1 a2 a1 a2 d1 d2 d0 d3 table 1?49. altgx configurations in sdi mode configuration data rate (mbps) refclk frequencies (mhz) core fabric-transceiver interface width hd 1485 74.25, 148.5 10 bit and 20-bit 1483.5 74.175, 148.35 10 bit and 20-bit 3g 2970 148.5, 297 only 20-bit interface allowed in 3g 2967 148.35, 296.7 only 20-bit interface allowed in 3g
chapter 1: hardcopy iv gx transceiver architecture 1?175 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?144 shows sdi mode configurations supported in hardcopy iv gx devices. figure 1?144. sdi mode sdi disabled disabled rate match fifo byte serdes byte ordering hardcopy iv gx configurations basic single width double width functional modes protocol pipe xaui gige srio sonet /sdh (oif) cei sdi 8-bit 10-bit 16-bit 20-bit 10-bit 10-bit 10-bit 10-bit 8-bit 16-bit 10-bit functional mode disabled disabled disabled disabled disabled enabled channel bonding disabled disabled enabled disabled pma-pcs interface width data rate (gbps) low-latency pcs word aligner (pattern length) 8b/10b encoder/decoder core fabric-transceiver interface width core fabric-transceiver interface frequency (mhz) 148.5/ 148.35 74.25/ 74.175 10-bit 20-bit bit-slip x1 hd-sdi (1.485/1.4835) x1 3g-sdi (2.97/2.967) bit-slip 20-bit 148.5/ 148.35
1?176 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation sdi mode datapath figure 1?145 shows the transceiver datapath when configured in sdi mode. transmitter datapath the transmitter datapath, in hd-sdi configuration with 10 bit wide core fabric-transceiver interface, consists of the transmitter phase compensation fifo and the 10:1 serializer. the transmitter datapath, in hd-sdi and 3g-sdi configurations with 20 bit wide core fabric-transceiver interface, also includes the byte serializer. 1 rr r rr cvrr rr fc c cr ccc rc cc c r cr c rr receiver datapath in the 10-bit channel width sdi configuration, the receiver datapath is comprised of the clock recovery unit (cru), 1:10 deserializer, word aligner in bit-slip mode, and receiver phase compensation fifo. in the 20-bit channel width sdi configuration, the receiver datapath also includes the byte deserializer. 1 rcvr fc c cr fr ccr cr c rr receiver word alignment and framing in sdi systems, the word aligner in the receiver datapath is not useful because word alignment and framing happens after de-scrambling. altera recommends driving the altgx megafunction rx_bitslip signal low to avoid having the word aligner insert bits in the received data stream. figure 1?145. sdi mode datapath tx phase compensation fifo byte serializer serializer transmitter channel pcs transmitter channel pma low-speed parallel clock high-speed serial clock tx_coreclk rx phase compensation fifo byte de- serializer word aligner de- serializer cdr tx_clkout wrclk rdclk wrclk rdclk parallel recovered clock rx_coreclk receiver channel pcs receiver channel pma core fabric-transmitter interface clock core fabric core fabric-receiver interface clock rx_clkout local clock divider /2 /2
chapter 1: hardcopy iv gx transceiver architecture 1?177 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 (oif) cei phy interface mode optical internetworking forum (oif) cei phy interface mode is intended to support two main protocols: figure 1?146. (oif) cei phy interface mode rate match fifo byte serdes byte ordering hardcopy iv gx configurations basic single width double width functional modes protocol pipe xaui gige srio sonet /sdh (oif) cei sdi 8-bit 10-bit 16-bit 20-bit 10-bit 10-bit 10-bit 10-bit 8-bit 16-bit 10-bit functional mode disabled disabled disabled enabled channel bonding disabled disabled pma-pcs interface width data rate (gbps) low-latency pcs word aligner (pattern length) 8b/10b encoder/decoder core fabric-transceiver interface width core fabric-transceiver interface frequency (mhz) 97.65625 - 199.21875 32-bit x1, x4 (transmitter pma-only bonding) 3.125-6.375 (oif) cei phy interface mode
1?178 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation (oif) cei phy interf ace mode datapath figure 1?147 shows the altgx megafunction transceiver datapath when configured in (oif) cei phy interface mode. (oif) cei phy interf ace mode clocking for improved transmitter jitter performance, the altgx megawizard plug-in manager provides the use central clock divider to improve transmitter jitter option. if you select this option, the high-speed serial clock generated by the cmu0 clock divider block clocks all four transceiver channels within the same transceiver block. otherwise, the high-speed serial clock generated by the local clock divider in each channel clocks the respective channel. 1 r r c rr rfc w wr c figure 1?147. (oif) cei phy interface mode datapath tx phase compensation fifo byte serializer transmitter channel pcs transmitter channel pma wrclk wrclk rdclk rdclk low-speed parallel clock high-speed serial clock tx_coreclk rx phase compensation fifo cdr /2 /2 tx_clkout parallel recovered clock rx_coreclk receiver channel pcs receiver channel pma core fabric-transmitter interface clock core fabric core fabric-receiver interface clock rx_clkout local clock divider serializer de- serializer byte de- serializer
chapter 1: hardcopy iv gx transceiver architecture 1?179 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?148 shows transceiver clocking in (oif) cei phy interface mode with and without the improved transmitter jitter option enabled. transceiver placement limitations with the use central clock divider to improve transmitter jitter option enabled if one or more channels in a transceiver block are configured to (oif) cei phy interface mode with the improved jitter clocking option enabled, the remaining channels in that transceiver block must either be configured in (oif) cei phy interface mode with this option enabled or must be unused. all used channels within a transceiver block configured in (oif) cei phy interface mode with the improved jitter clocking option enabled must also run at the same data rate. figure 1?149 and figure 1?150 show two examples each of legal and illegal transceiver placements with respect to the improved jitter clocking option in (oif) cei phy interface mode. figure 1?148. transceiver clocking in (oif) cei phy interface mode cmu pll transceiver block clocking with the use central clock divider to improve transmitter jitter option enabled cmu0 clock divider block channel 3 channel 2 channel 1 channel 0 transceiver block clocking with the use central clock divider to improve transmitter jitter option disabled cmu pll ch 3 local clock divider block ch 2 local clock divider block ch 1 local clock divider block ch 0 local clock divider block channel 3 channel 2 channel 1 channel 0 figure 1?149. examples of legal transceiver placement in (oif) cei phy interface mode ch 3 ch 2 ch 1 ch 0 (oif) cei phy interface mode with the low-jitter option enabled (data rate = 5 gbps) (oif) cei phy interface mode with the low-jitter option enabled (data rate = 5 gbps) (oif) cei phy interface mode with the low-jitter option disabled (oif) cei phy interface mode with the low-jitter option disabled unused channel unused channel serial rapidio serial rapidio ch 3 ch 2 ch 1 ch 0
1?180 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation serial rapidio mode the rapidio trade association defines a high-performance, packet-switched interconnect standard to pass data and control information between microprocessors, digital signal, communications, and network processors, system memories, and peripheral devices. serial rapidio physical layer specification defines three line rates: figure 1?150. examples of illegal transceiver placement in (oif) cei phy interface mode ch 3 ch 2 ch 1 ch 0 (oif) cei phy interface mode with the low-jitter option enabled (oif) cei phy interface mode with the low-jitter option enabled serial rapidio serial rapidio ch 3 ch 2 ch 1 ch 0 (oif) cei phy interface mode with the low-jitter option enabled (data rate = 5 gbps ) (oif) cei phy interface mode with the low-jitter option enabled (data rate = 5 gbps ) (oif) cei phy interface mode with the low-jitter option enabled (data rate = 6 gbps ) (oif) cei phy interface mode with the low-jitter option enabled (data rate = 6 gbps )
chapter 1: hardcopy iv gx transceiver architecture 1?181 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?151 shows the altgx transceiver datapath when configured in serial rapidio mode. hardcopy iv gx transceivers, when configured in serial rapidio functional mode, provide the following pcs and pma functions: 1 r rcvr v r fr r fc fr r c r r rr fc c rr r r crc synchronization state machine in serial rapidio mode, the altgx megawizard plug-in manager defaults the word alignment pattern to k28.5. the word aligner has a synchronization state machine that handles the receiver lane synchronization. the altgx megawizard plug-in manager automatically defaults the synchronization state machine to indicate synchronization when the receiver receives 127 k28.5 (10'b010 1111 100 or 10'b1010000011) synchronization code groups without receiving an intermediate invalid code group. once synchronized, the state machine indicates loss of synchronization when it detects three invalid code groups separated by less than 255 valid code groups or when it is reset. receiver synchronization is indicated on the rx_syncstatus port of each channel. a high on the rx_syncstatus port indicates that the lane is synchronized and a low indicates that it has fallen out of synchronization. figure 1?151. serial rapidio mode datapath tx phase compensation fifo 8b/10b encoder 8b/10b decoder serializer de- serializer transmitter channel pcs transmitter channel pma wrclk rdclk low-speed parallel clock high-sp eed serial cloc k tx_coreclk[0] rx phase compensation fifo rate match fifo word aligner cdr tx_clkout[0] parallel recovered clock low-speed parallel clock rx_coreclk[0] receiver channel pcs receiver channel pma core fabric-transceiver interface clock core fabric local clock divider byte serializer /2 /2 byte de- serializer /2
1?182 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation table 1?50 lists the altgx megafunction synchronization state machine parameters when configured in serial rapidio mode. figure 1?152 shows a conceptual view of the synchronization state machine implemented in serial rapidio functional mode. table 1?50. synchronization state machine parameters in serial rapidio mode parameters number number of valid k28.5 code groups received to achieve synchronization. 127 number of errors received to lose synchronization. 3 number of continuous good code groups received to reduce the error count by one. 255 figure 1?152. synchronization state machine in serial rapidio mode loss of sync data = comma comma detect if data == comma kcntr++ else kcntr=kcntr synchronized data = valid; kcntr < 127 kcntr = 127 synchronized error detect if data == !valid ecntr++ gcntr=0 else if gcntr==255 ecntr-- gcntr=0 else gcntr++ data = !valid data=valid ecntr = 0 ecntr = 3 data = !valid
chapter 1: hardcopy iv gx transceiver architecture 1?183 functional modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 basic (pma-direct) functional mode in basic (pma-direct) functional mode, the hardcopy iv gx transceiver datapath contains only pma blocks. parallel data is transferred directly between the core fabric and the serializer/deserializer inside the transmitter/receiver pma. because all pcs blocks are bypassed in basic (pma direct) mode, you must implement the required pcs logic in the core fabric. you can configure four regular transceiver channels inside each transceiver block in basic (pma-direct) functional mode. two cmu channels inside each transceiver block can be configured only in basic (pma-direct) functional mode, as they do not support pcs circuitry. in pma-direct mode, you must create your own logic to support pcs functionality. there are specific reset sequences to be followed in this mode. use dynamic reconfiguration to dynamically reconfigure the various pma controls to tailor the transceivers in pma direct drive mode for a particular application. f r r fr rfr hardcopy iv gx dynamic reconfiguration chapter in volume 3 of the hardcopy iv device handbook . the term ?pma-direct? is used to describe various configurations in this mode. 1 c rc c r rfr fr c c rr 1 crcr wr r w r c rr rr cr frc c rc cr r w c r fc r 11 w r rcvr cfr c rc fc r c c r r cv figure 1?153. hardcopy iv gx transceiver configured in basic (pma-direct) mode note to figure 1?153 : (1) the grayed out blocks shown in figure 1?153 are not available in the cmu channels. therefore, the cmu channels can be configured to operate as transceiver channels in pma direct mode only. transmitter channel pcs transmitter channel pma receiver channel pcs receiver channel pma core fa b ric pci express hard ip pipe interface tx phase compensation fifo byte serializer 8b/10b encoder serializer cdr de- serializer w ord aligner rate match fifo 8b/10b decoder byte de- serializer rx phase compensation fifo
1?184 chapter 1: hardcopy iv gx transceiver architecture functional modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation 1 the grayed out blocks shown in figure 1?153 are not available in the cmu channels. therefore, the cmu channels can be configured to operate as transceiver channels in pma-direct mode only. in basic (pma-direct) mode, you can configure the transceiver channel in two main configurations: basic pma-direct 1 configuration and basic pma-direct n configuration. you can configure the transceiver in basic pma-direct 1/ n mode by setting the appropriate sub-protocol in the which sub protocol will you be using ? field. you can select single-width or double-width by selecting single/double in the what is the deserializer block width? field in the altgx megawizard plug-in manager. in single-width mode, the pma-pld interface is 8 bit/10 bit wide; whereas in double-width mode, the pma-pld interface is 16 bit/20 bit wide. table 1?51 shows the pld-pma interface widths and data rates supported in basic pma-direct 1/n single-width and double-width modes. basic pma-direct x1 configuration you can configure a transceiver channel in this mode by setting the which protocol will you be using? field to basic (pma-direct) and the which sub protocol will you be using? field to none . in this configuration, the quartus ii software requires one of the two cmu plls within the same transceiver block to provide high-speed clocks to the transmitter side of the channel. basic pma-direct xn configuration you can configure a transceiver channel in this mode by setting the which protocol will you be using field to basic (pma-direct) and the which sub protocol will you be using field to n . in this mode, all the transmitter channels can receive their high-speed clock from the cmu pll0 from the transceiver blocks or the atx pll present on the same side of the device. these clocks are provided through the n_top or n_bottom clock line. each receiver in a receiver channel has a dedicated cdr that provides a high-speed clock. table 1?51. basic deterministic latency mode basic pma direct 1/n functional mode supported data rate range at speed grade -3 core fabric frequency (max) core fabric-pma interface width basic pma direct 1/ n single-width mode 600 mbps to 1.28 gbps 318.75 mhz 8 bit 600 mbps to 1.6 gbps 318.75 mhz 10 bit basic pma direct 1/ n double-width mode 1 gbps to 2.56 gbps 318.75 mhz 16 bit 1 gbps to 3.2 gbps 318.75 mhz 20 bit
chapter 1: hardcopy iv gx transceiver architecture 1?185 built-in self test modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 built-in self test modes this section describes built-in self test (bist) modes. bist mode pattern generators and verifiers each transceiver channel in the hardcopy iv gx device contains a different bist pattern generator and verifier. using these bist patterns, you can verify the functionality of the functional blocks in the transceiver channel without requiring user logic. the bist functionality is provided as an optional mechanism for debugging transceiver channels. figure 1?154 shows the enabled input and output ports when you select bist mode (except incremental patterns). three types of pattern generators and verifiers are available: rx_seriallpbken port. therefore, the 8b/10b encoder/decoder blocks are bypassed in the basic prbs mode. figure 1?154. input and output ports for bist modes notes to figure 1?154 : (1) rx_serilalpbken is required in prbs. (2) rx_bisterr and rx_bistdone are only available in prbs and bist modes. tx_datain[] tx_digitalreset rx_digitalreset rx_seriallp b ken[] (1) pll_inclk bu ilt-in self test (bist) tx_dataout rx_bisterr (2) rx_bistdone (2)
1?186 chapter 1: hardcopy iv gx transceiver architecture built-in self test modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation different prbs patterns are available as a subprotocol under basic functional mode for single-width and double-width mode, as shown in the following sections. you can enable the serial loopback option in basic prbs mode to loop the generated pattern to the receiver channel. this creates a rx_seriallpbken port that you can use to dynamically control the serial loopback. the 8b/10b encoder/decoder blocks are bypassed in basic prbs mode. figure 1?155 shows the datapath for the prbs patterns. the generated prbs pattern is sent to the transmitter serializer. the verifier checks the data from the word aligner. prbs in single-width mode table 1?52 shows various prbs patterns and corresponding word alignment patterns for prbs in single-width mode configuration. figure 1?155. bist prbs, high frequency, and low frequency pattern datapath recei v er channel pcs transmitter channel pcs transmitter channel pma recei v er channel pma core fa b ric tx phase compen- sation fifo byte serializer 8b/10b encoder bist prbs, high-fre q, lo w -freg pattern generator serializer serial loop b ack can be dynamically enab led receiv er cdr de- serializer w ord aligner bist prbs v erifier deske w fifo rate match fifo 8b/10b decoder byte de- serializer byte ordering rx phase compen- sation fifo table 1?52. available prbs, high frequency, and low frequency patterns in single-width mode (part 1 of 2) patterns polynomial channel width 8 bit (1) word alignment pattern with channel width 8 bit maximum data rate with channel width 8 bit (gbps) channel width 10 bit (1) word alignment pattern maximum data rate with channel width 10 bit (gbps) prbs 7 x 7 + x 6 + 1 y 16?h3040 2.5 n ? ? prbs 8 x 8 + x 7 + 1 y 16?hff5a 2.5 n ? ? prbs 10 x 10 + x 7 + 1 n ? n/a y 10?h3ff 3.125 prbs 23 x 23 + x 18 + 1 y 16?hffff 2.5 n ? ? high frequency (2) 1010101010 y ? 2.5 y ? 3.125
chapter 1: hardcopy iv gx transceiver architecture 1?187 built-in self test modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 the status signals rx_bistdone and rx_bisterr indicate the status of the verifier. the rx_bistdone port gets asserted and stays high when the verifier either receives one full cycle of incremental pattern or it detects an error in the receiver data. the rx_bisterr signal gets asserted and stays high when the verifier detects an error. you can reset the prbs pattern generator and verifier by asserting the tx_digitalreset and rx_digitalreset signals, respectively. prbs in d ouble-width mode table 1?53 shows various prbs patterns and corresponding word alignment patterns for prbs in double-width mode configuration. the status signals rx_bisterr and rx_bistdone are available to indicate the status of the verifier. for more information about the behavior of these status signals, refer to ?single-width mode? on page 1?39 . low frequency (2) 0000011111 n ? ? y ? 3.125 notes to ta bl e 1? 52 : (1) channel width refers to the what is the channel width? option in the general screen of the altgx megawizard plug-in manager. based on the selection, an 8 or 10 bits wide pattern is generated as indicated by a yes (y) or no (n) . (2) a verifier is not available for the specified patterns. table 1?52. available prbs, high frequency, and low frequency patterns in single-width mode (part 2 of 2) patterns polynomial channel width 8 bit (1) word alignment pattern with channel width 8 bit maximum data rate with channel width 8 bit (gbps) channel width 10 bit (1) word alignment pattern maximum data rate with channel width 10 bit (gbps) table 1?53. available prbs, high frequency, and low frequency patterns in double-width mode patterns polynomial channel width 16 bit (1) word alignment pattern with channel width 16 bit maximum data rate with channel width 16 bit (gbps) channel width 20 bit (1) word alignment pattern maximum data rate with channel width 20 bit (gbps) prbs 7 x 7 + x 6 + 1 y 16?h3040 5 y 20?h43040 6.375 prbs 23 x 23 + x 18 + 1 y 32?h007ffff f 5 y 40?h00007ff fff 6.375 high frequency (2) 1010101010 y ? 5 y ? 6.375 low frequency (2) 0000011111 n ? ? y ? 6.375 notes to ta bl e 1? 53 : (1) channel width refers to the what is the channel width? option in the general screen of the altgx megawizard plug-in manager. based on the selection, a 16 or 20 bits wide pattern is generated as indicated by a yes ( y ) or no ( n ). (2) verifier is not available for the specified patterns.
1?188 chapter 1: hardcopy iv gx transceiver architecture loopback modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation loopback modes hardcopy iv gx devices provide various loopback options that allow you to verify the working of different functional blocks in the transceiver channel. the available loopback options are: serial loopback the serial loopback option is available for all functional modes except pci express (pipe) mode. figure 1?156 shows the datapath for serial loopback. the data from the core fabric passes through the transmitter channel and gets looped back to the receiver channel, bypassing the receiver buffer. the received data is available to the core logic for verification. using this option, you can check the working for all enabled pcs and pma functional blocks in the transmitter and receiver channel. when you enable the serial loopback option, the altgx megawizard plug-in manager provides the rx_seriallpbken port to dynamically enable serial loopback on a channel-by-channel basis. set the rx_seriallpbken signal to logic high to enable serial loopback. when serial loopback is enabled, the transmitter channel sends the data to both the tx_dataout output port and to the receiver channel. the differential output voltage on the tx_dataout ports is based on the selected v od settings. the looped back data is received by the receiver cdr and is retimed through different clock domains. you must provide an alignment pattern for the word aligner to enable the receiver channel to retrieve the byte boundary. figure 1?156. serial loopback datapath recei v er channel pcs transmitter channel pcs transmitter channel pma recei v er channel pma core fa b ric tx phase compen- sation fifo byte serializer 8b/10b encoder bist prbs, high-fre q, lo w -freg pattern generator serializer serial loop b ack can be dynamically enab led receiv er cdr de- serializer w ord aligner bist prbs v erifier deske w fifo rate match fifo 8b/10b decoder byte de- serializer byte ordering rx phase compen- sation fifo
chapter 1: hardcopy iv gx transceiver architecture 1?189 loopback modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 parallel loopback mode you can configure a transceiver channel in this mode by setting the which protocol will you be using ? field to basic and the which sub protocol will you be using? field to bist . you can only configure a receiver and transmitter transceiver channel in this functional mode. you can configure a transceiver channel in this mode in either a single-width or double-width configuration. the bist pattern generator and pattern verifier are located near the core fabric in the pcs block of the transceiver channel. this placement allows for testing the complete transmitter pcs and receiver pcs datapaths for bit errors. this mode is primarily used for transceiver channel debugging, if needed. the parallel loopback mode is available only with a built-in 16 bit incremental pattern generator and verifier. the channel width is fixed to 16 bits in this mode. also in this mode, the incremental pattern 00-ff is looped back to the receiver channel at the pcs functional block boundary before the pma and is sent out to the tx_dataout port. the received data is verified by the verifier. this loopback allows you to verify the complete pcs block. the differential output voltage of the transmitted serial data on the tx_dataout port is based on the selected v od settings. the datapath for parallel loopback is shown in figure 1?157 . the incremental data pattern is not available to the core logic for verification. table 1?54 shows the enabled pcs functional blocks for single-width and double-width mode. the last column in table 1?54 shows the supported channel width setting for parallel loopback. figure 1?157. enabled pcs functional blocks in parallel loopback recei v er channel pcs transmitter channel pcs transmitter channel pma recei v er channel pma core fa b ric bist incremental pattern generator tx phase compen- sation fifo byte serializer 8b/10b encoder serializer receiv er cdr de- serializer parallel loopb ack w ord aligner 8b/10b decoder byte de- serializer rx compen- sation fifo bist incremental pattern v erifier table 1?54. enabled pcs functional blocks for parallel loopback configuration 8b/10b encoder byte serializer data rate range supported channel width setting in the altgx megawizard plug-in manager for parallel loopback single-width mode enabled enabled 600 mbps to 3.125gbps 16 double-width mode enabled disabled 1gbps to 5gbps 16
1?190 chapter 1: hardcopy iv gx transceiver architecture loopback modes hardcopy iv device handbook volume 3 ? june 2009 altera corporation the status signals rx_bistdone and rx_bisterr indicate the status of the verifier. the rx_bistdone port is asserted and stays high when the verifier either receives one full cycle of incremental pattern or it detects an error in the receiver data. the rx_bisterr signal is asserted and stays high when the verifier detects an error. you can reset the incremental pattern generator and verifier by asserting the tx_digitalreset and rx_digitalreset signals, respectively. reverse serial loopback reverse serial loopback is available as a subprotocol under basic functional mode. in reverse serial loopback mode, the data is received through the rx_datain port, retimed through the receiver cdr and sent out to the tx_dataout port. the received data is also available to the core logic. figure 1?158 shows the transceiver channel datapath for reverse serial loopback mode. the active block of the transmitter channel is only the transmitter buffer. you can change the output differential voltage on the transmitter buffer through the altgx megawizard plug-in manager. the pre-emphasis settings for the transmitter buffer cannot be changed in this configuration. reverse serial loopback is often implemented when using a bit error rate tester (bert) on the upstream transmitter. reverse serial pre-cdr loopback the reverse serial pre-cdr loopback is available as a subprotocol under basic functional mode. in reverse serial pre-cdr loopback, the data received through the rx_datain port is looped back to the tx_dataout port before the receiver cdr. the received data is also available to the core logic. figure 1?159 shows the transceiver channel datapath for reverse serial pre-cdr loopback mode. the active block of the transmitter channel is only the transmitter buffer. you can change the output differential voltage and the pre-emphasis first post-tap values on the transmitter buffer through the altgx megawizard plug-in manager or through the dynamic reconfiguration controller. the pre-tap and second post-tap values cannot be changed in this loop back configuration. figure 1?158. reverse serial loopback datapath (grayed-out blocks are not active in this mode) receiver channel pcs transmitter channel pcs transmitter channel pma receiver channe l pma core fabric tx phase compen- sation fifo byte serialzier 8b/10b encoder serializer reverse serial loopback word aligner 8b/10b decoder byte de- serializer byte ordering rx phase compen- sation fifo receiver cdr de- serializer
chapter 1: hardcopy iv gx transceiver architecture 1?191 loopback modes ? june 2009 altera corporation hardcopy iv device handbook volume 3 pci express (pipe) reverse parallel loopback pci express (pipe) reverse parallel loopback is only available in pipe functional mode for gen1 and gen2 data rates. as shown in figure 1?160 , the received serial data passes through the receiver cdr, deserializer, word aligner, and rate matching fifo buffer. it is then looped back to the transmitter serializer and transmitted out through the tx_dataout port. the received data is also available to the core fabric through the rx_dataout port. this loopback mode is compliant with the pci express (pipe) specification 2.0. to enable this loopback mode, assert the tx_detectrxloopback port. 1 c r r fc figure 1?159. reverse serial pre-cdr loopback datapath receiver channel pcs transmitter channel pcs transmitter channel pma receiver channel pma core fabric serializer reverse serial pre-cdr loopback receiver cdr de- serializer word aligner 8b/10b decoder byte de- serializer byte ordering rx phase compen- sation fifo
1?192 chapter 1: hardcopy iv gx transceiver architecture calibration blocks hardcopy iv device handbook volume 3 ? june 2009 altera corporation in figure 1?160 , the grayed areas show the inactive paths when the pci express (pipe) reverse parallel loopback mode is enabled. calibration blocks hardcopy iv gx devices contain calibration circuits that calibrate the oct resistors and the analog portions of the transceiver blocks to ensure that the functionality is independent of process, voltage, or temperature variations. calibration block location figure 1?161 shows the location and number of calibration blocks available for different transceiver block device families. in figure 1?161 through figure 1?163 , the calibration block r0 and l0 refer to the calibration blocks on the right and left side, respectively. figure 1?160. pci express (pipe) reverse parallel loopback mode datapath (grayed-out blocks are not active in this mode) transmitter channel pcs transmitter channel pma cdr receiver channel pcs receiver channel pma core fabric pci express hardip pipe interface pci express hardip pipe interface tx phase compensation fifo byte serializer 8b/10b encoder serializer reverse parallel loopback path de- serializer word aligner rate match fifo 8b/10b decoder byte de- serializer rx phase compen- sation fifo figure 1?161. calibration blocks hardcopy iv gx device gxbl1 gxbl0 gxbr1 gxbr0 calibration block l0 calibration block r0 2k 2k
chapter 1: hardcopy iv gx transceiver architecture 1?193 calibration blocks ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 1?162 shows hardcopy iv gx device families that have three transceiver blocks each on the left and right side. figure 1?163 shows hardcopy iv gx device families that have two transceiver blocks only on the right side of the device. the quartus ii software automatically selects the appropriate calibration block based on the assignment of the transceiver tx_dataout and rx_datain pins. calibration the calibration block internally generates a constant internal reference voltage, independent of process, voltage, or temperature variations. it uses the internal reference voltage and external reference resistor (you must connect the resistor to the rref pin) to generate constant reference currents. these reference currents are used by the analog block calibration circuit to calibrate the transceiver blocks. the oct calibration circuit calibrates the oct resistors present in the transceiver channels. you can enable the oct resistors in the transceiver channels through the altgx megawizard plug-in manager. figure 1?162. calibration block locations in hardcopy iv gx device families with three-transceiver blocks (on each side) figure 1?163. calibration two transceiver blocks, right side only hardcopy iv gx device calibration block l1 calibration block r1 gxbl2 gxbr2 gxbl1 gxbr1 gxbl0 gxbr0 calibration block l0 calibration block r0 2k 2k 2k 2k hardcopy iv gx device gxbr1 gxbr0 calibration block r0 2k
1?194 chapter 1: hardcopy iv gx transceiver architecture document revision history hardcopy iv device handbook volume 3 ? june 2009 altera corporation you must connect a separate 2 k rref pin in the hardcopy iv gx device to ground. to ensure proper operation of the calibration block, the rref resistor connection in the board must be free from external noise. input signals to the calibration block figure 1?164 shows the required inputs to the calibration block. the altgx megawizard plug-in manager provides the cal_blk_clk and cal_blk_powerdown ports to control the calibration block. cal_blk_clk ?you must use the cal_blk_clk port to provide input clock to the calibration clock. the frequency of cal_blk_clk must be within 10 mhz to 125 mhz (this range is preliminary. final values will be available upon characterization). you can use dedicated clock routes such as the global or regional clock. if you do not have suitable input reference clock or dedicated clock routing resources available, use divide-down logic from the core fabric to generate a slow clock and use local clocking routing. drive the cal_blk_clk port of all altgx instances that are associated with the same calibration block from the same input pin or logic. cal_blk_powerdown ?you can perform calibration multiple times by using the cal_blk_powerdown port available through the altgx megawizard plug-in manager. assert this signal for approximately 500 ns (this is preliminary. final values will be available upon characterization). following de-assertion of cal_blk_powerdown , the calibration block restarts the calibration process. drive the cal_blk_powerdown port of all altgx instances that are associated with the same calibration block from the same input pin or logic. document revision history table 1?55 shows the revision history for this chapter. figure 1?164. input signals to the calibration blocks calibration block rref pin cal_blk_clk cal_blk_powerdown internal reference voltage generator reference signal oct calibration circuit analog block calibration circuit oct calibration control analog block calibration control table 1?55. document revision history date and document version changes made summary of changes june 2009, v1.0 initial release. ?
? june 2009 altera corporation hardcopy iv device handbook, volume 3 2. hardcopy iv gx dynamic reconfiguration introduction dynamic reconfiguration is a feature available for hardcopy ? iv gx transceivers. each transceiver channel has multiple physical medium attachment (pma) controls that you can program to achieve the desired bit error ratio (ber) for your system. when you enable the dynamic reconfiguration feature, you can reconfigure the pma controls, functional blocks, cmu phased-locked loops (plls), receiver clock data recovery (cdr), and input reference clocks of a transceiver channel without powering down other transceiver channels or the core fabric logic of the device. this chapter contains the following sections: ?conventions used in this chapter? ?dynamic reconfiguration modes? on page 2?3 ?quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration? on page 2?5 ?offset cancellation control for receiver channels? on page 2?43 ?the rx_tx_duplex_sel[1:0] port? on page 2?49 ?the logical_channel_address port? on page 2?51 ?pma controls reconfiguration? on page 2?52 ?description of transceiver channel reconfiguration modes? on page 2?62 ?error indication in the altgx_reconfig megawizard plug-in manager? on page 2?139 ?combining transceiver channels with dynamic reconfiguration enabled? on page 2?140 ?dynamic reconfiguration duration and core fabric resource utilization? on page 2?143 ?functional simulation of the offset cancellation process? on page 2?147 conventions used in this chapter the following conventions are used in this chapter: altgx_reconfig instance?this term represents the dynamic reconfiguration controller instance generated by the altgx_reconfig megawizard? plug-in manager. this term is used when the various inputs, outputs, and connections to the controller are explained. altgx instance?this term represents the transceiver instance generated by the altgx megawizard plug-in manager. this term is used when the various inputs, outputs, and connections to the transceiver channels are explained. hiv53002-1.0
2?2 chapter 2: hardcopy iv gx dynamic reconfiguration conventions used in this chapter hardcopy iv device handbook, volume 3 ? june 2009 altera corporation alternate transmitter pll?this term refers to one of the two cmu plls of a transceiver block. it refers to the cmu pll configured in the reconfig alt pll screen of the altgx megawizard plug-in manager. channel and tx pll select/reconfig?this term refers to the three dynamic reconfiguration modes: cmu pll reconfiguration, channel and cmu pll reconfiguration, and channel reconfiguration with tx pll select. cmu channel?this term refers to the cmu plls of a transceiver block configured as pma-only channels. dynamic reconfiguration controller?this term represents the dynamic reconfiguration controller. this term is used when a concept related to the controller is explained. logical channel addressing?this term is used whenever the concept of logical channel addressing is explained. this term does not refer to the logical_channel_address port or the use 'logical_channel_address' port for analog controls reconfiguration option available in the altgx_reconfig megawizard plug-in manager. logical reference index?this term refers to the logical identification value of 0 or 1 assigned to the main transmitter pll and the alternate transmitter pll. you set this value in the reconfig clks 1 and reconfig alt pll screens of the altgx megawizard plug-in manager. logical tx pll?this term refers to the logical reference index value of the transmitter plls stored in the .mif . main transmitter pll?this term refers to one of the two cmu plls of a transceiver block. it refers to the cmu pll configured in the general screen of the altgx megawizard plug-in manager. memory initialization file, also known as .mif ?when you enable .mif generation in your design, a file with the extension .mif gets generated. this file contains information about the various altgx megawizard plug-in manager options you can set. each word in the .mif is 16 bits wide. the dynamic reconfiguration controller writes information from the .mif into the transceiver channel, but only when you use the 'channel and tx pll select/reconfig' dynamic reconfiguration mode. for more information about implementing a .mif in a hardcopy asic, refer to the hardcopy iv device family overview chapter in volume 1 of the hardcopy iv device handbook . pma controls?this term represents analog controls (vod, pre-emphasis, manual equalization) as displayed in both the altgx and altgx_reconfig megawizard plug-in managers. pma-only channels?this term refers to both the cmu channels as well as the regular transceiver channels with only the pma blocks enabled. when you configure the altgx megawizard plug-in manager in basic (pma direct) protocol in the general screen, all the channels get configured as pma-only channels. regular transceiver channel?this term refers to a transmitter channel or a receiver channel or a duplex channel that has both pma and physical coding sublayer (pcs) blocks.
chapter 2: hardcopy iv gx dynamic reconfiguration 2?3 dynamic reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 dynamic reconfiguration modes the different modes of dynamic reconfiguration are as follows: offset cancellation for receiver channels pma controls reconfiguration transceiver channel reconfiguration 1 offset cancellation for receiver channels mode and pma controls reconfiguration mode are the same for both the regular transceiver channels and pma-only channels. these modes are described briefly in the following sections. offset cancellation the hardcopy iv gx device provides an offset cancellation circuit per receiver channel to counter the offset variations due to process, voltage, and temperature (pvt). these variations create an offset in the analog circuit voltages, pushing them out of the expected range. in addition to reconfiguring the transceiver channel, the dynamic reconfiguration controller performs offset cancellation on all receiver channels connected to it on power up. the offset cancellation for receiver channels option is automatically enabled in both the altgx and altgx_reconfig megawizard plug-in managers for receiver and transmitter and receiver only configurations. it is not available for transmitter only configurations. for receiver and transmitter and receiver only configurations, you must connect the necessary interface signals between the altgx_reconfig and altgx (with receiver channels) instances. for more information, refer to ?offset cancellation control for receiver channels? on page 2?43 . 1 for proper device operation, you must always connect the altgx_reconfig and altgx (with receiver channels) instances. pma controls reconfiguration you can dynamically reconfigure the following pma controls: pre-emphasis settings equalization settings dc gain settings voltage output differential (v od ) settings for more information, refer to ?pma controls reconfiguration? on page 2?52 . transceiver channel reconfiguration modes each transceiver block has four regular transceiver channels and two cmu channels. the regular transceiver channels have both pma and pcs blocks. the cmu channels are cmu plls configured in basic (pma direct) functional mode as pma-only channels. therefore, the cmu channels have only pma blocks.
2?4 chapter 2: hardcopy iv gx dynamic reconfiguration dynamic reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation regular transceiver channels for the regular transceiver channels, dynamic reconfiguration involves the reconfiguration of the following: transceiver channel functional mode transceiver channel data rate switch transceiver channel functional mode and data rate switch however, the following dynamic reconfigurations cannot be achieved for the regular transceiver channels in the hardcopy iv gx device: mode switch to and from any 4 and 8 configurations prototype design with stratix iv gx device is not backward compatible with stratix gx or stratix ii gx devices testability features (pseudo-random binary sequence [prbs] and built-in self te st [b is t ] ) mode switch to and from any n basic (pma direct) configuration mode switch to and from any 1 basic (pma direct) configuration 1 for more information about dynamic reconfiguration of the cmu channels, refer to ?pma controls reconfiguration? on page 2?52 . depending on how you want to reconfigure a transceiver channel, the transceiver channel reconfiguration is further classified into the following dynamic reconfiguration modes: data rate division in tx data rate division in tx mode is not available for non-basic (pma direct) bonded configurations, basic (pma direct) 1, and basic (pma direct) n configurations. for more information, refer to ?data rate division in tx mode? on page 2?63 . channel and tx pll select/reconfig channel and cmu pll reconfiguration channel reconfiguration with tx pll select cmu pll reconfiguration the modes grouped under channel and tx pll select/reconfig mode are not available for bonded non-basic (pma direct) configurations, basic (pma direct) 1, and basic (pma direct) n configurations. for more information, refer to ?channel and tx pll select/reconfig modes? on page 2?68 . offset cancellation is enabled by default. all other dynamic reconfiguration modes are available for selection through the reconfig_mode_sel[2:0] signal. based on which part of the transceiver channel you want to reconfigure, you can select one or more of these dynamic reconfiguration modes. the reconfig_mode_sel[2:0] signal is available as an input to the dynamic reconfiguration controller only when you select multiple dynamic reconfiguration modes.
chapter 2: hardcopy iv gx dynamic reconfiguration 2?5 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 based on the value you set at the reconfig_mode_sel[2:0] signal, the respective dynamic reconfiguration mode is enabled. the reconfig_mode_sel[2:0] signal is 3bits wide. table 2?1 shows the various dynamic reconfiguration modes supported by the regular transceiver channels and cmu channels, and the value that you need to set at the reconfig_mode_sel[2:0] input port to activate one of the selected dynamic reconfiguration modes. 1 the reconfig_mode_sel[2:0] input is available when you select more than one dynamic reconfiguration mode in the altgx_reconfig megawizard plug-in manager. the default value for this reconfig_mode_sel[2:0] input is 000. quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration the hardcopy iv gx device provides two megawizard plug-in manager interfaces to support dynamic reconfiguration: altgx and altgx_reconfig. this section provides information about the dynamic reconfiguration options available in the altgx and altgx_reconfig megawizard plug-in managers. altgx megawizard plug-in manager the altgx megawizard plug-in manager provides the following options in the reconfig screen to enable the various dynamic reconfiguration modes (shown in figure 2?1 ): the analog controls (vod, pre-emphasis, and manual equalization) option for the pma controls reconfiguration mode. the offset cancellation for receiver channels option is enabled by default and grayed out for the offset cancellation mode. the enable channel and transmitter pll reconfiguration option for the data rate division in tx, cmu pll reconfiguration, channel and cmu pll reconfiguration, and channel reconfiguration with tx pll select modes. tab le 2 ?1 . dynamic reconfiguration modes supported by regular transceiver channels and cmu channels dynamic reconfiguration mode regular transceiver channels cmu channels reconfig_mode_sel[2:0] (1) pma controls reconfiguration yes not supported 3?b000 data rate division in tx yes not supported 3?b011 channel and tx pll select/reconfig cmu pll reconfiguration yes not supported 3?b100 channel and cmu pll reconfiguration yes not supported 3?b101 channel reconfiguration with tx pll select yes not supported 3?b110 not supported not supported not supported 3?b111 note to tab l e 2 ?1 : (1) reconfig_mode_sel [2:0] = 3'b001 and 3'b010 are not supported.
2?6 chapter 2: hardcopy iv gx dynamic reconfiguration quartus ii megawizard plug-in manager interfaces to support dynamic hardcopy iv device handbook, volume 3 ? june 2009 altera corporation select the options in the preceding list to enable the corresponding dynamic reconfiguration modes. altgx_reconfig m egawizard plug-in manager the quartus ? ii software provides the altgx_reconfig megawizard plug-in manager to instantiate the dynamic reconfiguration controller. the following options are available in the reconfiguration settings screen to enable the various dynamic reconfiguration modes (shown in figure 2?2 ): the offset cancellation for receiver channels option is enabled by default and grayed out for the offset cancellation mode. the analog controls option for the pma controls reconfiguration mode. to dynamically reconfigure the pma controls, enable at least one of the pma control ports in the analog controls screen. the data rate division in tx option for the data rate division in tx mode. the channel and tx pll select/reconfig option for the cmu pll reconfiguration, channel and cmu pll reconfiguration, and channel reconfiguration with tx pll select modes. figure 2?1. dynamic reconfiguration settings in the altgx megawizard plug-in manager
chapter 2: hardcopy iv gx dynamic reconfiguration 2?7 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 select the options listed above to enable the corresponding dynamic reconfiguration modes. dynamic reconfiguration controller architecture the dynamic reconfiguration controller is a soft ip that utilizes the core fabric resources. you can use only one controller per transceiver block. you cannot use the dynamic reconfiguration controller to control multiple hardcopy iv gx devices or any off-chip interfaces. figure 2?3 shows the conceptual view of the dynamic reconfiguration controller architecture. figure 2?2. dynamic reconfiguration settings in the altgx_reconfig megawizard plug-in manager
2?8 chapter 2: hardcopy iv gx dynamic reconfiguration quartus ii megawizard plug-in manager interfaces to support dynamic hardcopy iv device handbook, volume 3 ? june 2009 altera corporation the dynamic reconfiguration controller has the following control logic modules: pma controls reconfiguration control logic offset cancellation control logic for receiver channels data rate division control logic to the tx local divider channel reconfiguration with tx pll select/reconfig control logic cmu pll reconfiguration control logic channel and cmu pll reconfiguration control logic channel reconfiguration with tx pll select control logic figure 2?3. block diagram of the dynamic reconfiguration controller note to figure 2?3 : (1) the pma control ports consist of the v od controls, pre-emphasis controls, dc gain controls, and manual equalization controls. for a detailed description of all the inputs and outputs of the altgx_reconfig instance, refer to ?dynamic reconfiguration controller port list? on page 2?11 . data data v alid busy error read dynamic reconfig u ration controller reconfig_clk w rite_all reconfig_fromgxb[] pma control ports (1) rate_switch_ctrl[1:0] (tx only) reset_reconfig_address reconfig_data[15:0] logical_tx_pll_sel logical_tx_pll_sel_en logical_channel_address[] rx_tx_duplex_sel[1:0] reconfig_mode_sel[2:0] offset cancellation control logic channel reconfig with tx pll select control logic channel and cmu pll reconfig control logic cmu pll reconfig control logic data rate switch control logic pma controls reconfig logic addr address translation parallel to serial converter reconfig_togxb[3:0] rate_switch_out[1:0] (tx only) reconfig_address_out[5:0] reconfig_address_en channel_reconfig_done
chapter 2: hardcopy iv gx dynamic reconfiguration 2?9 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 for pma controls reconfiguration, the dynamic reconfiguration control inputs to the controller are translated into address and data bus. the address and data bus are then converted into serial data and forwarded to the transceiver channel selected. for the data rate division control logic to the tx local divider, the rate_switch_ctrl[1:0] input to the controller is translated into address and data bus. the address and data bus are then converted into serial data and forwarded to the local divider in the transmitter channel. for the cmu pll reconfiguration, channel and cmu pll reconfiguration, and channel reconfiguration with tx pll select modes, the dynamic reconfiguration controller receives 16-bit words from a .mif that you generate and sends this information to the transceiver channel selected. for more information regarding .mif generation, refer to ?.mif generation? on page 2?69 . dynamic reconfiguration controller interface the dynamic reconfiguration controller interface consists of certain control input and output status signals. figure 2?4 shows the dynamic reconfiguration interface list, which contains all the inputs and outputs to the dynamic reconfiguration controller.
2?10 chapter 2: hardcopy iv gx dynamic reconfiguration quartus ii megawizard plug-in manager interfaces to support dynamic hardcopy iv device handbook, volume 3 ? june 2009 altera corporation figure 2?4. dynamic reconfiguration controller interface notes to figure 2?4 : (1) these ports assume that the dynamic reconfiguration controller is connected to a single channel in the design. (2) these are the optional pma control input signals and the optiona l pma control output status signals. you must select at leas t one of these pma control ports if you want to dynamically configure the pma controls of a transceiver channel. for a detailed description of all the inputs and outputs of the altgx_reconfig instance, refer to ?dynamic reconfiguration controller port list? on page 2?11 . (3) the logical_channel_address port is available for selection only when the number of channels controlled by the dynamic reconfiguration controller is more than one. the port is shown here to represent the complete port list. dynamic reconfigu ration controller reconfig_clk reconfig_fromgxb [16:0] read w rite_all reconfig_togx b [3..0] data_v alid bu sy error tx_preemp_1t_out [4..0] tx_preemp_2t_out [4..0] rx_eq ctrl [3..0] tx_v odctrl [2..0] (1), (2) (1), (2) rx_eqdcgain [2..0] (1), (2) tx_preemp_0t [4..0] (1), (2) tx_preemp_1t [4..0] (1), (2) tx_preemp_2t [4..0] (1), (2) reconfig_mode_sel [2:0] rate_s w itch_ctrl [1:0] logical_tx_pll_sel logical_tx_pll_sel_en reset_reconfig_address rate_s witch_out [1:0] reconfig_data [15:0] channel_reconfig_done reconfig_address_en reconfig_address_o ut [5:0] tx_v odctrl_o ut [2..0] (1), (2) rx_eq ctrl_out [3..0] (1), (2) rx_eqdcgain_out [2..0] (1), (2) tx_preemp_0t_o ut [4..0] (1), (2) (1), (2) (1), (2) rx_tx_du plex_sel [1:0] (3) logical_channel_address [ 8:0]
chapter 2: hardcopy iv gx dynamic reconfiguration 2?11 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 dynamic reconfiguration controller port list table 2?2 describes the input control ports and output status ports of the dynamic reconfiguration controller. tab le 2 ?2 . dynamic reconfiguration controller port list (altgx_reconfig instance) (part 1 of 9) port name input/ output description clock inputs to altgx_reconfig instance reconfig_clk input the frequency range of this clock depends on the following transceiver channel configuration modes: (37.5 mhz to 50 mhz) (37.5 mhz to 50 mhz) (2.5 mhz to 50 mhz) for more information, refer to table 2?3 on page 2?20 . by default, the quartus ii software assigns a global clock resource to this port. altgx and altgx_reconfig interface signals reconfig_fromgxb input the width of this signal is determined by the value you set in the what is the number of channels controlled by the reconfig controller? option in the reconfiguration settings screen. for more information, refer to ?connecting the reconfig_fromgxb and reconfig_togxb ports? on page 2?40 . reconfig_togxb[3..0] output the width of this signal is fixed to 4 bits. it is independent of the value you set in the what is the number of channels controlled by the reconfig controller? option in the reconfiguration settings screen. for more information, refer to ?connecting the reconfig_fromgxb and reconfig_togxb ports? on page 2?40 . core fabric and altgx_reconfig interface signals write_all input assert this signal for one reconfig_clk clock cycle to initiate a write transaction from the altgx_reconfig instance to the altgx instance. for more information, refer to ?dynamically reconfiguring pma controls? on page 2?53 .
2?12 chapter 2: hardcopy iv gx dynamic reconfiguration quartus ii megawizard plug-in manager interfaces to support dynamic hardcopy iv device handbook, volume 3 ? june 2009 altera corporation busy output this signal is used to indicate the busy status of the dynamic reconfiguration controller during: offset cancellation?after the device powers up, this signal remains low for the first reconfig_clk clock cycle. it then is asserted and remains high when the dynamic reconfiguration controller performs offset cancellation on all the receiver channels connected to the altgx_reconfig instance. de-assertion of the busy signal indicates the successful completion of the offset cancellation process. for more information, refer to ?operation? on page 2?44 . pma controls reconfiguration mode?this signal is high when the dynamic reconfiguration controller performs a read or write transaction. all other dynamic reconfiguration modes?this signal is high when the dynamic reconfiguration controller writes the .mif into the transceiver channel. read input assert this signal for one reconfig_clk clock cycle to initiate a read transaction. the read port is applicable only to the pma controls reconfiguration mode. the read port is available when you select analog controls in the reconfiguration settings screen and select at least one of the pma control ports in the analog controls screen. for more information, refer to ?dynamically reconfiguring pma controls? on page 2?53 . data_valid output the data_valid port is applicable only to pma controls reconfiguration mode. this port indicates the validity of the data read from the transceiver by the dynamic reconfiguration controller. the current data on the output read ports is the valid data only if data_valid is high. this signal is enabled when you enable at least one pma control port used in read transactions, for example tx_vodctrl_out . error output this indicates that an unsupported operation is attempted. you can select this in the error checks/data rate switch screen. the dynamic reconfiguration controller de-asserts the busy signal and asserts the error signal for two reconfig_clk cycles when you attempt an unsupported operation. for more information, refer to the ?error indication in the altgx_reconfig megawizard plug-in manager? on page 2?139 . tab le 2 ?2 . dynamic reconfiguration controller port list (altgx_reconfig instance) (part 2 of 9) port name input/ output description
chapter 2: hardcopy iv gx dynamic reconfiguration 2?13 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 logical_channel_address [8:0] input the logical_channel_address port is enabled by the altgx_reconfig megawizard plug-in manager when you enable the use 'logical_channel_address' port for analog controls reconfiguration option in the analog controls screen. the width of the logical_channel_address port depends on the value you set in the what is the number of channels controlled by the reconfig controller? option in the reconfiguration settings screen. the logical_channel_address port can be enabled only when the number of channels controlled by the dynamic reconfiguration controller is more than one. for more information, refer to ?logical channel addressing of regular transceiver channels? on page 2?23 and ?logical channel addressing of pma-only channels? on page 2?32 . rx_tx_duplex_sel[1:0] input this is a 2-bit wide signal. you can select this in the error checks/data rate switch screen. the advantage of using this optional port is that it allows you to reconfigure only the transmitter portion of a channel, even if the channel configuration is duplex. for a setting of: rx_tx_duplex_sel[1:0] = 2'b00 => the transmitter and receiver portion of the channel is reconfigured. rx_tx_duplex_sel[1:0] = 2'b01 => the receiver portion of the channel is reconfigured. rx_tx_duplex_sel[1:0] = 2'b10 => the transmitter portion of the channel is reconfigured. tab le 2 ?2 . dynamic reconfiguration controller port list (altgx_reconfig instance) (part 3 of 9) port name input/ output description
2?14 chapter 2: hardcopy iv gx dynamic reconfiguration quartus ii megawizard plug-in manager interfaces to support dynamic hardcopy iv device handbook, volume 3 ? june 2009 altera corporation analog settings control/status signals tx_vodctrl[2..0] (1) input this is an optional transmit buffer v od control signal. it is 3 bits per transmitter channel. the number of settings varies based on the transmit buffer supply setting and the termination resistor setting on the tx analog screen of the altgx megawizard plug-in manager. the width of this signal is fixed to 3 bits if you enable either the use 'logical_channel_address' port for analog controls reconfiguration option or the use same control signal for all the channels option in the analog controls screen. otherwise, the width of this signal is 3 bits per channel. for more information, refer to ?dynamically reconfiguring pma controls? on page 2?53 . the following shows the v od values corresponding to the tx_vodctrl settings for 100- termination. for more information, refer to the programmable output differential voltage section of the hardcopy iv gx transceiver architecture chapter in volume 3 of the hardcopy iv device handbook . tx_vodctrl[2:0] v od (mv) for 1.4 v v cc h 3?b000 200 3?b001 400 3?b010 600 3?b011 700 3?b100 800 3?b101 900 3?b110 1000 3?b111 1200 tab le 2 ?2 . dynamic reconfiguration controller port list (altgx_reconfig instance) (part 4 of 9) port name input/ output description
chapter 2: hardcopy iv gx dynamic reconfiguration 2?15 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 tx_preemp_0t[4..0] (1) input this is an optional pre-emphasis control for pre-tap for the transmit buffer. depending on what value you set at this input, the controller dynamically writes the value to the pre-emphasis control register of the transmit buffer. this signal controls both pre-emphasis positive and its inversion. the width of this signal is fixed to 5 bits if you enable either the use 'logical_channel_address' port for analog controls reconfiguration option or the use same control signal for all the channels option in the analog controls screen. otherwise, the width of this signal is 5 bits per channel. for more information, refer to ?dynamically reconfiguring pma controls? on page 2?53 . the following values are the legal settings allowed for this signal: 0 represents 0 1-15 represents -15 to -1 16 represents 0 17 - 31 represents 1 to 15 in pci express (pipe) configuration, set tx_preemp_0t[4:0] to 5'b00000 when you do a rate switch from gen 1 to gen 2 mode. this is to ensure that tx_preemp_0t[4:0] does not add to the signal boost, when tx_pipemargin , tx_pipeswing , and tx_pipedeemph take affect in pci express (gen 2) mode. for more information, refer to the programmable pre-emphasis section of the hardcopy iv gx transceiver architecture chapter in volume 3 of the hardcopy iv device handbook . tx_preemp_1t[4..0] (1) input this is an optional pre-emphasis write control for the first post-tap for the transmit buffer. depending on what value you set at this input, the controller dynamically writes the value to the first post-tap control register of the transmit buffer. the width of this signal is fixed to 5 bits if you enable either the use 'logical_channel_address' port for analog controls reconfiguration option or the use same control signal for all the channels option in the analog controls screen. otherwise, the width of this signal is 5 bits per channel. for more information, refer to ?dynamically reconfiguring pma controls? on page 2?53 for additional details and the programmable pre-emphasis section of the hardcopy iv gx transceiver architecture chapter in volume 3 of the hardcopy iv device handbook . tab le 2 ?2 . dynamic reconfiguration controller port list (altgx_reconfig instance) (part 5 of 9) port name input/ output description
2?16 chapter 2: hardcopy iv gx dynamic reconfiguration quartus ii megawizard plug-in manager interfaces to support dynamic hardcopy iv device handbook, volume 3 ? june 2009 altera corporation tx_preemp_2t[4..0] (1) input this is an optional pre-emphasis write control for the second post-tap for the transmit buffer. this signal controls both pre-emphasis positive and its inversion. depending on what value you set at this input, the controller dynamically writes the value to the pre-emphasis control register of the transmit buffer. the width of this signal is fixed to 5 bits if you enable either the use 'logical_channel_address' port for analog controls reconfiguration option or the use same control signal for all the channels option in the analog controls screen. otherwise, the width of this signal is 5 bits per channel. for more information, refer to ?dynamically reconfiguring pma controls? on page 2?53 . the following values are the legal settings allowed for this signal: 0 represents 0 1-15 represents -15 to -1 16 represents 0 17-31 represents 1 to 15 in pci express (pipe) configuration, set tx_preemp_2t[4:0] to 5'b00000 when you do a rate switch from gen 1 to gen 2 mode. this is to ensure that tx_preemp_2t[4:0] does not add to the signal boost when tx_pipemargin , tx_pipeswing , and tx_pipedeemph take affect in pci express (gen 2) mode. for more information, refer to the programmable pre-emphasis section of the hardcopy iv gx transceiver architecture chapter in volume 3 of the hardcopy iv device handbook . rx_eqctrl[3..0] (1) input this is an optional write control to write an equalization control value for the receive side of the pma. the width of this signal is fixed to 4 bits if you enable either the use 'logical_channel_address' port for analog controls reconfiguration option or the use same control signal for all the channels option in the analog controls screen. otherwise, the width of this signal is 4 bits per channel. for more information, refer to ?dynamically reconfiguring pma controls? on page 2?53 and the programmable equalization and dc gain section of the hardcopy iv gx transceiver architecture chapter in volume 3 of the hardcopy iv device handbook . tab le 2 ?2 . dynamic reconfiguration controller port list (altgx_reconfig instance) (part 6 of 9) port name input/ output description
chapter 2: hardcopy iv gx dynamic reconfiguration 2?17 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 rx_eqdcgain[2..0] (1) , (2) input this is an optional equalizer dc gain write control. the width of this signal is fixed to 3 bits if you enable either the use 'logical_channel_address' port for analog controls reconfiguration option or the use same control signal for all the channels option in the analog controls screen. otherwise, the width of this signal is 3 bits per channel. for more information, refer to ?dynamically reconfiguring pma controls? on page 2?53 . the following values are the legal settings allowed for this signal: 3?b000 => 0 db 3?b001 => 3 db 3?b010 => 6 db 3?b011 => 9 db 3?b100 => 12 db all other values => n/a for more information, refer to the programmable equalization and dc gain section of the hardcopy iv gx transceiver architecture chapter in volume 3 of the hardcopy iv device handbook. tx_vodctrl_out[2..0] output this is an optional transmit v od read control signal. this signal reads out the value written into the v od control register. the width of this output signal depends on the number of channels controlled by the dynamic reconfiguration controller. tx_preemp_0t_out[4..0] output this is an optional pre-tap, pre-emphasis read control signal. this signal reads out the value written by its input control signal. the width of this output signal depends on the number of channels controlled by the dynamic reconfiguration controller. tx_preemp_1t_out[4..0] output this is an optional first post-tap, pre-emphasis read control signal. this signal reads out the value written by its input control signal. the width of this output signal depends on the number of channels controlled by the dynamic reconfiguration controller. tx_preemp_2t_out[4..0] output this is an optional second post-tap pre-emphasis read control signal. this signal reads out the value written by its input control signal. the width of this output signal depends on the number of channels controlled by the dynamic reconfiguration controller. rx_eqctrl_out[3..0] output this is an optional read control signal to read the setting of equalization setting of the altgx instance. the width of this output signal depends on the number of channels controlled by the dynamic reconfiguration controller. rx_eqdcgain_out[2..0] output this is an optional equalizer dc gain read control signal. this signal reads out the settings of the altgx instance dc gain. the width of this output signal depends on the number of channels controlled by the dynamic reconfiguration controller. tab le 2 ?2 . dynamic reconfiguration controller port list (altgx_reconfig instance) (part 7 of 9) port name input/ output description
2?18 chapter 2: hardcopy iv gx dynamic reconfiguration quartus ii megawizard plug-in manager interfaces to support dynamic hardcopy iv device handbook, volume 3 ? june 2009 altera corporation transceiver channel reconfiguration control/status signals reconfig_mode_sel[2:0] input set the following values at this signal to activate the appropriate dynamic reconfiguration mode: 3?b000 ? pma controls reconfiguration mode. this is the default value. 3?b011 ? data rate division in tx mode 3?b100 ? cmu pll reconfiguration mode 3?b101 ? channel and cmu pll reconfiguration mode 3?b110 ? channel reconfiguration with tx pll select mode 3?b111 ? not supported reconfig_address_out[5:0] output this signal is always available for you to select in the channel and tx pll reconfiguration screen. this signal is applicable only in the dynamic reconfiguration modes grouped under channel and tx pll select/reconfig option. this signal represents the current address used by the altgx_reconfig instance when writing the .mif into the transceiver channel. this signal increments by 1, from 0 to last address, then starts at 0 again. you can use this signal to indicate the end of all the .mif write transactions ( reconfig_address_out[5:0] changes from the last address to 0 at the end of all the .mif write transactions). reconfig_address_en output this is an optional signal you can select in the channel and tx pll reconfiguration screen. this signal is applicable only in dynamic reconfiguration modes grouped under the channel and tx pll select/reconfig option. the dynamic reconfiguration controller asserts reconfig_address_en to indicate that reconfig_address_out[5:0] has changed. this signal gets asserted only after the dynamic reconfiguration controller completes writing one 16-bit word of the .mif . reset_reconfig_address input this is an optional signal you can select in the channel and tx pll reconfiguration screen. this signal is applicable only in dynamic reconfiguration modes grouped under the channel and tx pll select/reconfig option. enable this signal and assert it for one reconfig_clk clock cycle if you want to reset the reconfiguration address used by the altgx_reconfig instance during reconfiguration. reconfig_data[15:0] input this signal is applicable only in the dynamic reconfiguration modes grouped under the channel and tx pll select/reconfig option. this is a 16-bit word carrying the reconfiguration information. it is stored in a .mif file that you need to generate. the altgx_reconfig instance requires that you provide reconfig_data [15:0] on every .mif write transaction using the write_all signal. tab le 2 ?2 . dynamic reconfiguration controller port list (altgx_reconfig instance) (part 8 of 9) port name input/ output description
chapter 2: hardcopy iv gx dynamic reconfiguration 2?19 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 rate_switch_ctrl[1:0] input this signal is available when you select data rate division in tx mode. based on the value you set here, the divide-by setting of the local divider in the transmitter channel gets modified. the legal values for this port are: 2?b00 ? divide by 1 2?b01 ? divide by 2 2?b10 ? divide by 4 2?b11 ? not supported for more information, refer to ?data rate division in tx mode? on page 2?63 . rate_switch_out[1:0] input this signal is available when you select data rate division in tx mode. you can read the existing local divider settings of a transmitter channel at this port. the decoding for this signal is listed below: 2?b00 ? division of 1 2?b01 ? division of 2 2?b10 ? division of 4 2?b11? not supported for more information, refer to ?data rate division in tx: operation? on page 2?66 . logical_tx_pll_sel input at this port you specify the identity of the tx pll you want to reconfigure. you can also specify the identity of the tx pll that you want the transceiver channel to listen to. when you enable this signal, the value set at this signal overwrites the logical_tx_pll value contained in the .mif . the value at this port needs to be held at a constant logic level until reconfiguration is done. logical_tx_pll_sel_en input if you want to use the logical_tx_pll_sel port only under some conditions and use the logical_tx_pll value contained in the .mif otherwise, enable this optional logical_tx_pll_sel_en port. only when logical_tx_pll_sel_en is enabled and set to 1 does the dynamic reconfiguration controller use logical_tx_pll_sel to identify the tx pll. the value at this port needs to be held at a constant logic level until reconfiguration is done. channel_reconfig_done output this signal goes high for one reconfig_clk clock cycle to indicate that the dynamic reconfiguration controller has finished writing all the words of the .mif . this signal is applicable only in channel and cmu pll reconfiguration and channel reconfiguration with tx pll select modes. notes to ta bl e 2? 2 : (1) not all combinations of the input bits are legal values. (2) in pci express (pipe) mode, this input needs to be tied to 001 to be pci e-compliant. tab le 2 ?2 . dynamic reconfiguration controller port list (altgx_reconfig instance) (part 9 of 9) port name input/ output description
2?20 chapter 2: hardcopy iv gx dynamic reconfiguration quartus ii megawizard plug-in manager interfaces to support dynamic hardcopy iv device handbook, volume 3 ? june 2009 altera corporation clock requirements for the altgx instance and altgx_reconfig instance this section describes the dynamic reconfiguration clock requirements for both the altgx instance (transceiver instance) and the altgx_reconfig instance (dynamic reconfiguration controller instance). clock requirements for the altgx instance for all functional mode configurations except pci express (pipe) configurations, you must connect the reconfig_clk input port of the altgx instance to the same clock that is connected to the reconfig_clk input port of the altgx_reconfig instance. the offset cancellation circuit requires that the minimum frequency of its input clock is 37.5 mhz. therefore, the altgx configurations, including a receiver, require that the minimum frequency of reconfig_clk (the clock used by the offset cancellation circuit) is 37.5 mhz. for pci express (pipe) configurations only, the fixedclk input port is used to clock the offset cancellation circuit instead of the reconfig_clk input port. therefore, the reconfig_clk input port frequency range can vary from 2.5 mhz to 50 mhz in pci express (pipe) configurations. table 2?3 shows the range of frequency values for the reconfig_clk port. clock requirements for the altgx_reconfig instance you must connect the reconfig_clk input port of the altgx_reconfig instance to the same clock that is connected to the reconfig_clk input port of the altgx instance. table 2?3 shows the range of frequency values of the reconfig_clk input port for receiver only , receiver and transmitter , and transmitter only configuration modes of the altgx instance. table 2?3 also shows the clock requirements for the reconfig_clk input port to the altgx_reconfig instance based on altgx configurations. 1 based on altgx configurations ( receiver only , transmitter only , receiver and transmitter configurations) controlled by the altgx_reconfig instance, select the fastest reconfig_clk frequency value. this satisfies both the offset cancellation control for receiver channels and the dynamic reconfiguration of the transmitter and receiver channels. tab le 2 ?3 . reconfig_clk settings for altgx instance (note 1) altgx instance configuration reconfig_clk frequency range receiver and transmitter reconfiguration configuration 37.5 mhz to 50 mhz receiver only reconfiguration configuration 37.5 mhz to 50 mhz transmitter only reconfiguration configuration 2.5 mhz to 50 mhz note to tab l e 2 ?3 : (1) altera recommends the reconfig_clk signal be driven on a global clock resource.
chapter 2: hardcopy iv gx dynamic reconfiguration 2?21 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 interfacing altgx_reconfig and altgx instances this section describes the various dynamic reconfiguration settings available in the altgx_reconfig and altgx megawizard plug-in managers and how to set them. it also provides information about the interface signals and connections between the altgx_reconfig and altgx instances. there are two ways to connect the altgx_reconfig instance to the altgx instance in your design: single dynamic reconfiguration controller?you can use a single altgx_reconfig instance to control all the altgx instances in your design. figure 2?5 shows a block diagram of a single altgx_reconfig instance controlling multiple altgx instances. figure 2?5. block diagram of a single dynamic reconfiguration controller in a design altgx_reco nfig instance altgx instance 1 reconfig_fromgxb [n:0] reconfig_togxb [3:0] altgx instance 2
2?22 chapter 2: hardcopy iv gx dynamic reconfiguration quartus ii megawizard plug-in manager interfaces to support dynamic hardcopy iv device handbook, volume 3 ? june 2009 altera corporation multiple dynamic reconfiguration controllers?your design can have multiple altgx_reconfig instances, where every altgx instance is controlled by its own altgx_reconfig instance. figure 2?6 shows a block diagram of multiple altgx_reconfig instances, each controlling a single altgx instance. to enable dynamic reconfiguration of a transceiver channel, you must understand the following: logical channel addressing?the dynamic reconfiguration controller identifies a transceiver channel by using the logical channel address. the what is the starting channel number? option in the reconfig screen of the altgx megawizard plug-in manager allows you to set the logical channel address of all the channels within the altgx instance. this concept is explained in detail in ?logical channel addressing? on page 2?23 . total number of channels controlled by the altgx_reconfig instance?every dynamic reconfiguration controller in a design might be connected to either a single altgx instance or multiple altgx instances. depending on the number of channels within each of these altgx instances, you must set the total number of channels controlled by the dynamic reconfiguration controller in the altgx_reconfig megawizard plug-in manager. this concept is explained in ?total number of channels controlled by the altgx_reconfig instance? on page 2?35 . connecting the reconfig_fromgxb and reconfig_togxb ports between the altgx and altgx_reconfig instances. figure 2?6. block diagram of multiple dynamic reconfiguration controllers in a design altgx instance 1 altgx_reco nfig instance 1 reconfig_fromgxb [n:0] reconfig_togxb [3:0] altgx instance 2 altgx_reco nfig instance 2 reconfig_fromgxb [n:0] reconfig_togxb [3:0]
chapter 2: hardcopy iv gx dynamic reconfiguration 2?23 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 logical channel addressing when you configure an altgx instance in basic (pma direct) functional mode, all the channels within the altgx instance are pma-only channels. depending on the pins you assign to these pma-only channels, they can either be: regular transceiver channels with pma-only or cmu channels however, when you configure an altgx instance with both the pcs and pma blocks, all the channels within the altgx instance can only be regular transceiver channels. the following sections describe the concept of logical channel addressing for regular transceiver channels, pma-only channels, and a combination of pma-only channels and regular transceiver channels that are not in basic (pma direct) functional mode. logical channel addressing of regular transceiver channels this section describes how to set the what is the starting channel number? option using five different case scenarios for the regular transceiver channels. figure 2?7 shows the what is the starting channel number? option in the reconfig screen of the altgx megawizard plug-in manager. figure 2?7. what is the starting channel number? option in the altgx megawizard plug-in manager
2?24 chapter 2: hardcopy iv gx dynamic reconfiguration quartus ii megawizard plug-in manager interfaces to support dynamic hardcopy iv device handbook, volume 3 ? june 2009 altera corporation this value determines the logical channel address of all the transceiver channels in the altgx instance. you must always set the starting channel number in an altgx instance as a multiple of 4. 1 you must set the next multiple of 4 for the what is the starting channel number? option of the following altgx instances, if any. 1 based on the value you entered for the what is the starting channel number? option, the atlgx megawizard plug-in manager assigns consecutive numbers as the logical channel address for all the channels within an altgx instance. the following sections describe the logical channel addressing of regular transceiver channels for five example scenarios in detail. 1 the first three example scenarios: case 1, 2, and 3 have a single altgx_reconfig instance connected to two altgx instances. the difference between these three cases is the number of channels configured in the altgx instances. regular transceiver channels: case 1 table 2?4 shows an example scenario for case 1. table 2?5 shows the logical channel addressing of regular transceiver channels in case 1. tab le 2 ?4 . example scenarios for logical channel addressing in altgx instances for case 1 example scenario number of altgx instances number of altgx_reconfig instances case 1 two altgx instances: altgx instance 1 (1 channel) altgx instance 2 (3 channels) one altgx_reconfig instance controlling both the altgx instances tab le 2 ?5 . logical channel addressing of regular transceiver channels for case 1 altgx instances altgx_reconfig instance altgx megawizard plug-in manager setting altgx instance 1 altgx instance 2 altgx_reconfig instance 1: controls both altgx instance 1 and altgx instance 2. refer to table 2?16 on page 2?37 for the altgx_reconfig instance 1 settings. what is the number of channels? in the general screen 13 what is the starting channel number? in the reconfig screen set this option to 0 because the starting channel number increments in steps of 4, you must set the starting channel number of the next altgx instance as a multiple of 4. therefore, set this option to 4 . the logical channel addresses of the first channel is 0 the logical channel addresses of the first to third channels are 4 , 5 , and 6 , respectively.
chapter 2: hardcopy iv gx dynamic reconfiguration 2?25 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 figure 2?8 shows the logical channel addresses of all the channels within altgx instance 1 and altgx instance 2. regular transceiver channels: case 2 table 2?6 shows an example scenario for case 2. figure 2?8. case 1?block diagram of the altgx instances and altgx_reconfig instance (note 1) notes to figure 2?8 : (1) for more information, refer to ?regular transceiver channels: case 1? on page 2?24 . (2) reconfig_fromgxb[33:0] = { reconfig_fromgxb[16:0] , reconfig_fromgxb[16:0] }. channel 0 (logical_address_channel = 0) channel 0 (logical_address_channel = 4) channel 1 (logical_address_channel = 5) channel 2 (logical_address_channel = 6) altgx_reco nfig instance set the what is the number of channels controlled by the reconfig controller? option = 8 reconfig_fromgxb [16:0] reconfig_togx b [3:0] reconfig_fromgxb [16:0] reconfig_fromgxb [33:0] altgx instance 1 single channel instance the what is the starting channel number? option = 0 altgx instance 2 three channel instance the what is the starting channel number? option = 4 case 1 (2) tab le 2 ?6 . example scenarios for logical channel addressing in altgx instances for case 2 example scenario number of altgx instances number of altgx_reconfig instances case 2 two altgx instances:  altgx instance 1 (6 channels)  altgx instance 2 (3 channels) one altgx_reconfig instance controlling both the altgx instances.
2?26 chapter 2: hardcopy iv gx dynamic reconfiguration quartus ii megawizard plug-in manager interfaces to support dynamic hardcopy iv device handbook, volume 3 ? june 2009 altera corporation table 2?7 shows the logical channel addressing of regular transceiver channels in case 2. 1 for case 2, do not set the what is the starting channel number? option to 4 for altgx instance 2 (as in case 1) because the logical channel addresses 4 and 5 are used already for the fifth and sixth channels of altgx instance 1. instead, use the next multiple of 4 to assign it as the starting channel number of altgx instance 2. tab le 2 ?7 . logical channel addressing of regular transceiver channels for case 2 altgx instances altgx_reconfig instance altgx megawizard plug-in manager setting altgx instance 1 altgx instance 2 altgx_reconfig instance 1: controls both altgx instance 1 and altgx instance 2. for more information, refer to table 2?16 on page 2?37 for the altgx_reconfig instance 1 settings. what is the number of channels? in the general screen 63 what is the starting channel number? in the reconfig screen set this option to 0 because the starting channel number increments in steps of 4, you must set the starting channel number of the next altgx instance as a multiple of 4. therefore, set this option to 8 . the logical channel addresses of the first to sixth channels are 0 , 1 , 2 , 3 , 4 , and 5 , respectively. the logical channel addresses of the first to third channels are 8 , 9 , and 10 , respectively.
chapter 2: hardcopy iv gx dynamic reconfiguration 2?27 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 figure 2?9 shows the logical channel addresses of all the channels within altgx instance 1 and altgx instance 2. figure 2?9. case 2?block diagram of the altgx instances and altgx_reconfig instance (note 1) notes to figure 2?9 : (1) for more information, refer to ?regular transceiver channels: case 2? on page 2?25 . (2) reconfig_fromgxb[50:0] = {reconfig_fromgxb[16:0], reconfig_fromgxb[33:0]}. channel 3 (logical_address_channel = 3) channel 0 (logical_address_channel = 8) channel 0 (logical_address_channel = 9) channel 0 (logical_address_channel = 10) altgx_reco nfig instance channel 4 (logical_address_channel = 4) channel 0 (logical_address_channel = 5) channel 1 (logical_address_channel = 1) channel 2 (logical_address_channel = 2) channel 0 (logical_address_channel = 0) set the what is the number of channels controlled by the reconfig controller? option = 12 reconfig_fromgxb [33:0] reconfig_togxb [3:0] (1) reconfig_fromgxb [16:0] reconfig_fromgxb [50:0] (2) altgx instance 1 six channel instance the what is the starting channel number? option = 0 altgx instance 2 three channel instance the what is the starting channel number? option = 8 case 2
2?28 chapter 2: hardcopy iv gx dynamic reconfiguration quartus ii megawizard plug-in manager interfaces to support dynamic hardcopy iv device handbook, volume 3 ? june 2009 altera corporation regular transceiver channels: case 3 table 2?8 shows an example scenario for case 3. table 2?9 shows the logical channel addressing of regular transceiver channels in case 3. tab le 2 ?8 . example scenarios for logical channel addressing in altgx instances for case 3 example scenario number of altgx instances number of altgx_reconfig instances case 3 two altgx instances: altgx instance 1 (6 channels) altgx instance 2 (6 channels) one altgx_reconfig instance controlling both the altgx instances. tab le 2 ?9 . logical channel addressing of regular transceiver channels for case 3 altgx instances altgx_reconfig instance altgx megawizard plug-in manager setting altgx instance 1 altgx instance 2 altgx_reconfig instance 1: controls both altgx instance 1 and altgx instance 2. for more information, refer to table 2?16 on page 2?37 for the altgx_reconfig instance 1 settings. what is the number of channels? in the general screen 66 what is the starting channel number? in the reconfig screen set this option to 0 because the starting channel number increments in steps of 4, you must set the starting channel number of the next altgx instance as a multiple of 4. therefore, set this option to 8 . the logical channel addresses of the first to sixth channels are 0 , 1 , 2 , 3 , 4 , and 5 , respectively. the logical channel addresses of the first to third channels are 8 , 9 , 10 , 11 , 12 , and 13 , respectively.
chapter 2: hardcopy iv gx dynamic reconfiguration 2?29 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 for case 3, do not set the what is the starting channel number? option to 4 for altgx instance 2 (as in case 1) because the logical channel addresses 4 and 5 are used already for the fifth and sixth channels of altgx instance 1. instead, use the next multiple of 4 to assign it as the starting channel number of altgx instance 2. figure 2?10 shows the logical channel addresses of all the channels within altgx instance 1 and altgx instance 2. figure 2?10. block diagram of the altgx instances and altgx_reconfig instance for case 3 (note 1) notes to figure 2?10 : (1) for more information, refer to ?regular transceiver channels: case 3? on page 2?28 . (2) reconfig_fromgxb[67:0] = { reconfig_fromgxb[33:0] , reconfig_fromgxb[33:0] }. tx only channel 3 (logical_address_channel = 3) altgx_reco nfig instance tx only channel 4 (logical_address_channel = 4) tx only channel 5 (logical_address_channel = 5) tx only channel 1 (logical_address_channel = 1) tx only channel 2 (logical_address_channel = 2) tx only channel 0 (logical_address_channel = 0) rx only channel 3 (logical_address_channel = 11) rx only channel 4 (logical_address_channel = 12) rx only channel 5 (logical_address_channel = 13) rx only channel 1 (logical_address_channel = 9) rx only channel 2 (logical_address_channel = 10) rx only channel 0 (logical_address_channel = 8) set the what is the number of channels controlled by the reconfig controller? option = 16 reconfig_fromgxb [33:0] reconfig_togxb [3:0] (1) reconfig_fromgxb [33:0] reconfig_fromgxb [67:0] (2) altgx instance 1 six channel instance the what is the starting channel number? option = 0 altgx instance 2 six channel instance the what is the starting channel number? option = 8 case 3
2?30 chapter 2: hardcopy iv gx dynamic reconfiguration quartus ii megawizard plug-in manager interfaces to support dynamic hardcopy iv device handbook, volume 3 ? june 2009 altera corporation regular transceiver channels: case 4 similarly, in this example there are multiple altgx_reconfig instances, each controlling a single altgx instance in your design. case 4 explains the scenario under which you must set the what is the starting channel number? option differently. this scenario assumes that each altgx instance has its own altgx_reconfig instance. table 2?10 shows an example scenario for case 4. table 2?11 shows the logical channel addressing of regular transceiver channels in case 4. table 2?10. example scenarios for logical channel addressing in altgx instances for case 4 example scenario number of altgx instances number of altgx_reconfig instances case 4 two altgx instances: altgx instance 1 altgx instance 2 two altgx_reconfig instances: altgx_reconfig instance 1 and altgx_reconfig instance 2 altgx_reconfig instance 1 controls altgx instance 1 altgx_reconfig instance 2 controls altgx instance 2 table 2?11. logical channel addressing of regular transceiver channels for case 4 altgx instances altgx_reconfig instance altgx_reconfig instance altgx megawizard plug-in manager setting altgx instance 1 altgx instance 2 altgx_reconfig instance 1: controls altgx instance 1. for more information, refer to table 2?16 on page 2?37 for the altgx_reconfig instance 1 settings. altgx_reconfig instance 2: controls altgx instance 2. for more information, refer to table 2?16 on page 2?37 for the altgx_reconfig instance 2 settings. what is the number of channels? in the general screen 55 what is the starting channel number? in the reconfig screen set this option to 0 set this option to 0 (because altgx instance 2 is controlled by a separate altgx_reconfig instance 2) the logical channel addresses of the first to fifth channels are 0 , 1 , 2 , 3 , and 4 , respectively. the logical channel addresses of the first to third channels are 0 , 1 , 2 , 3 , and 4 , respectively.
chapter 2: hardcopy iv gx dynamic reconfiguration 2?31 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 figure 2?11 shows the logical channel addresses of all the channels within altgx instance 1 and altgx instance 2. regular transceiver channels: case 5 in this example, you have only one altgx instance (altgx instance 1) and one altgx_reconfig instance in the design: altgx instance 1?the number of channels in this instance is 1 altgx .v or altgx.vhd is stamped five times in the design figure 2?11. block diagram of the altgx instances and altgx_reconfig instances for case 4 (note 1) note to figure 2?11 : (1) for more information, refer to ?regular transceiver channels: case 4? on page 2?30 . channel 3 (logical_address_channel = 3) altgx_reco nfig instance 1 channel 4 (logical_address_channel = 4) channel 1 (logical_address_channel = 1) channel 2 (logical_address_channel = 2) channel 0 (logical_address_channel = 0) channel 3 (logical_address_channel = 3) channel 4 (logical_address_channel = 4) channel 1 (logical_address_channel = 1) channel 2 (logical_address_channel = 2) channel 0 (logical_address_channel = 0) set the what is the number of channels controlled by the reconfig controller? option = 8 reconfig_fromgxb [33:0] reconfig_togxb [3:0] (1) altgx_reco nfig instance 2 set the what is the number of channels controlled by the reconfig controller? option = 8 (1) altgx instance 1 fiv e channel instance the what is the starting channel number? option = 0 altgx instance 2 fiv e channel instance the what is the starting channel number? option = 0 reconfig_fromgxb [33:0] reconfig_togxb [3:0] case 4
2?32 chapter 2: hardcopy iv gx dynamic reconfiguration quartus ii megawizard plug-in manager interfaces to support dynamic hardcopy iv device handbook, volume 3 ? june 2009 altera corporation table 2?12 shows an example scenario for case 5. altgx instance 1 parameter settings set the what is the starting channel number? option to 0 . this implies that the atlgx megawizard plug-in manager sets the logical channel address of the single channel of altgx instance 1 = 0. when you stamp the above configured transceiver instance five times, the starting channel numbers of the other four instances (assume instance 2, instance 3, instance 4, instance 5) are 4, 8, 12 , and 16 , respectively. specify the starting channel number of the other stamped instances using the defparam parameter (for verilog) as shown: defparam instance2. starting_channel_number = 4; defparam instance3. starting_channel_number = 8; and so on for the remaining stamped instances. logical channel addressing of pma-only channels this section describes how to set the what is the starting channel number? option for altgx instances with pma-only channels. if your design requires only the pma portion of the transceiver channels, configure the altgx megawizard plug-in manager in basic (pma direct) functional mode in the general screen. therefore, all the channels in the altgx instance are configured as pma-only channels. the pma-only channels are comprised of cmu channels, regular transceiver channels configured in basic (pma direct) functional mode, or both cmu channels and regular transceiver channels configured in basic (pma direct) functional mode. 1 cmu channels are always pma-only channels. the regular transceiver channels can be optionally configured as pma-only channels. set the starting channel number for the pma-only channels in the same what is the starting channel number? option shown in figure 2?7 on page 2?23 . the value you set in the what is the starting channel number? option determines the logical channel addresses of all the pma-only channels within the altgx instance. you must always set the what is the starting channel number? option as a multiple of 4. the logical channel addresses of the pma-only channels within the same altgx instance also increment in multiples of 4 (unlike the logical channel addressing of regular transceiver channels that are not configured in basic (pma direct) functional mode, where the logical channel address increments in steps of 1 within the same altgx instance). table 2?12. example scenarios for logical channel addressing in altgx instances for case 5 example scenario number of altgx instances number of altgx_reconfig instances case 5 one altgx instance (altgx instance 1) stamped five times one altgx_reconfig instance controlling all five stamped altgx.v or altgx.vhd instances
chapter 2: hardcopy iv gx dynamic reconfiguration 2?33 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 table 2?13 shows an example scenario in which the logical channel address of the pma-only channels is set based on the value you entered in the what is the starting channel number? option. table 2?13 shows the logical channel addressing of regular transceiver channels in case 6. 1 you must set the next multiple of 4 as the starting channel number for the following altgx instances, if any. logical channel addressing: combination of pma-only channels and regular transceiver channels that are not in basic (pma direct) functional mode this section describes how to set the what is the starting channel number? option for multiple altgx instances controlled by the same altgx_reconfig instance, where one altgx instance can have pma-only channels and the other altgx instance can have regular transceiver channels that are not in basic (pma direct) functional mode. table 2?13. logical channel addressing of regular transceiver channels for case 6 altgx instances altgx_reconfig instance altgx megawizard plug-in manager setting altgx instance 1 configured in basic (pma direct) functional mode altgx_reconfig instance 1: controls altgx instance 1. for more information, refer to table 2?17 on page 2?39 for the altgx_reconfig instance 1 settings. what is the number of channels? in the general screen 8 (pma-only channels) what is the starting channel number? in the reconfig screen set this option to 0 the logical channel addresses of the first to sixth channels are 0 , 4 , 8 , 12 , 16 , 20 , 24 , and 28 , respectively.
2?34 chapter 2: hardcopy iv gx dynamic reconfiguration quartus ii megawizard plug-in manager interfaces to support dynamic hardcopy iv device handbook, volume 3 ? june 2009 altera corporation table 2?14 shows an example scenario in which the logical channel address of both the pma-only channels and regular transceiver channels is set based on the value you entered in the what is the starting channel number? option. highest possible logical channel address table 2?15 shows the highest possible logical channel address assigned to a transceiver channel in a hardcopy iv gx device. the maximum number of transceiver channels in the largest hardcopy iv gx device is 24 (12 transceiver channels located in two transceiver blocks on the right side of the device and 12 transceiver channels located in two transceiver blocks on the left side of the device). these 24 transceiver channels can be individually configured as 24 transmitter only and 24 receiver only channels. you can achieve this by using 24 transmitter only altgx instances and 24 receiver only altgx instances in your design. table 2?14. logical channel addressing of a combination of pma-only channels and regular transceiver channels that are not in basic (pma direct) functional mode for case 7 altgx instances altgx_reconfig instance altgx megawizard plug-in manager setting altgx instance 1 configured in basic functional mode altgx instance 2 altgx_reconfig instance 1: controls both altgx instance 1 and altgx instance 2. for more information, refer to table 2?18 on page 2?39 for the altgx_reconfig instance 1 settings. what is the number of channels? in the general screen 66 what is the starting channel number? in the reconfig screen set this option to 0 because the starting channel number increments in steps of 4, you must set the starting channel number of the next altgx instance as a multiple of 4. therefore, set this option as 8 for altgx instance 2. this is because the starting channel numbers 0 and 4 have already been used in altgx instance 1. the logical channel addresses of the first to fifth channels are 0 , 1 , 2 , 3 , and 4 , respectively. the logical channel addresses of the first to fourth channels are 8 , 12 , 16 , and 20 , respectively.
chapter 2: hardcopy iv gx dynamic reconfiguration 2?35 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 the highest logical channel address is assigned to the receiver only channel in the 48th altgx instance; therefore, the setting is 184. 1 the highest possible logical channel address assigned to a transceiver channel in a hardcopy iv gx device is the same whether the channel is a regular transceiver channel or a pma-only channel. the quartus ii software automatically packs the logical channels into the physical placements. the physical placement includes combining channels into the same transceiver block. for more information, refer to ?combining transceiver channels with dynamic reconfiguration enabled? on page 2?140 . total number of channels controlled by the altgx_re config inst ance the dynamic reconfiguration controller requires information about the total number of channels connected to it. based on this information, the reconfig_fromgxb and logical_channel_address input ports vary in width. therefore, provide this information in the what is the number of channels controlled by the reconfig controller? option in the reconfiguration settings screen of the altgx_reconfig megawizard plug-in manager, as shown in figure 2?12 . this section describes how to set the total number of channels controlled by the dynamic reconfiguration controller (altgx_reconfig instance). the maximum number of channels that you can set in this option is 256. table 2?15. highest possible logical channel address 48 altgx instances altgx_reconfig instance altgx megawizard plug-in manager setting altgx instance 1 altgx instance 2 altgx_reconfig instance 1: controls all 48 altgx instances. what is the number of channels? in the general screen 24 24 what is the starting channel number? in the reconfig screen tx instance 1: 0 tx instance 2: 4 . . . . . . tx instance 24: 96 rx instance 1: 100 rx instance 2: 104 . . . . . . rx instance 24: 184
2?36 chapter 2: hardcopy iv gx dynamic reconfiguration quartus ii megawizard plug-in manager interfaces to support dynamic hardcopy iv device handbook, volume 3 ? june 2009 altera corporation in this example, one altgx_reconfig instance is controlling all the altgx instances in a design. use the following rules for setting the what is the number of channels controlled by the controller? option: determine the highest logical channel address among all the transceiver instances connected to the same dynamic reconfiguration controller. for information about determining the logical channel address using the starting channel number, refer to ?logical channel addressing? on page 2?23 . round the logical channel address value to the next higher multiple of 4. use this value to set the what is the number of channels controlled by the reconfig controller ? option. total number of channels controlled by the altgx_reconfig instance?regular transceiver channels consider the example scenarios described in: table 2?3 on page 2?20 table 2?5 on page 2?24 table 2?7 on page 2?26 table 2?9 on page 2?28 table 2?11 on page 2?30 using the information from the tables listed, set the what is the number of channels controlled by the reconfig controller option for the same example scenarios. figure 2?12. what is the number of channels controlled by the reconfig controller? option in the altgx_reconfig megawizard plug-in manager
chapter 2: hardcopy iv gx dynamic reconfiguration 2?37 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 table 2?16 shows the altgx and altgx_reconfig settings for instances 1 and 2 in cases 1 through 5. table 2?16. altgx and altgx_reconfig settings for instances 1 and 2 in cases 1 through 5 (part 1 of 2) example scenario altgx instance 1 settings altgx instance 2 settings altgx_reconfig instance 1 settings altgx_reconfig instance 2 settings case 1 for a block diagram of the altgx instances and the altgx_reconfig instance in this design, refer to figure 2?8 on page 2?25 . one regular transceiver channel. set the what is the starting channel number? option in the reconfig screen to 0 . the logical channel address of the first channel is 0 . three regular transceiver channels. set the what is the starting channel number? option in the reconfig screen to 4 . the logical channel address of the first to third channels are 4 , 5 , and 6 , respectively. determine the highest logical channel address (6) for altgx instance 1. round it up to the next multiple of 4. set the what is the number of channels controlled by the controller? option in the reconfiguration settings screen to 8 . ? case 2 for a block diagram of the altgx instances and the altgx_reconfig instance in this design, refer to figure 2?9 on page 2?27 . six regular transceiver channels. set the what is the starting channel number? option in the reconfig screen to 0 . the logical channel address of the first to sixth channels are 0 , 1 , 2 , 3 , 4 , and 5 , respectively. three regular transceiver channels. set the what is the starting channel number? option in the reconfig screen to 8 . the logical channel address of the first to third channels are 8 , 9 , and 10 , respectively. determine the highest logical channel address (10). round it up to the next multiple of 4. set the what is the number of channels controlled by the controller? option in the reconfiguration settings screen to 12 . ? case 3 for a block diagram of the altgx instances and the altgx_reconfig instance in this design, refer to figure 2?10 on page 2?29 . six regular transceiver channels. set the what is the starting channel number? option in the reconfig screen to 0 . the logical channel address of the first to sixth channels are 0 , 1 , 2 , 3 , 4 , and 5 , respectively. six regular transceiver channels. set the what is the starting channel number? option in the reconfig screen to 8 . the logical channel address of the first to sixth channels are 8 , 9 , 10 , 11 , 12 , and 13 , respectively. determine the highest logical channel address (13). round it up to the next multiple of 4. set the what is the number of channels controlled by the controller? option in the reconfiguration settings screen to 16 . ?
2?38 chapter 2: hardcopy iv gx dynamic reconfiguration quartus ii megawizard plug-in manager interfaces to support dynamic hardcopy iv device handbook, volume 3 ? june 2009 altera corporation case 4 for a block diagram of the altgx instances and the altgx_reconfig instance in this design, refer to figure 2?11 on page 2?31 . five regular transceiver channels controlled by altgx_reconfig instance 1. set the what is the starting channel number? option in the reconfig screen to 0 . the logical channel address of the first to fifth channels are 0 , 1 , 2 , 3 , and 4 , respectively. five regular transceiver channels controlled by altgx_reconfig instance 2. set the what is the starting channel number? option in the reconfig screen to 0 . the logical channel address of the first to fifth channels are 0, 1 , 2 , 3 , and 4 , respectively. determine the highest logical channel address (4) for altgx instance 1. round it up to the next multiple of 4. set the what is the number of channels controlled by the controller? option in the reconfiguration settings screen to 8 . determine the highest logical channel address (4) for altgx instance 2. round it up to the next multiple of 4. set the what is the number of channels controlled by the controller? option in the reconfiguration settings screen to 8 . case 5 altgx instance 1 stamped five times. specify the starting channel number of the other stamped instances using the defparam parameter (for verilog) as shown: defparam instance2. starting_chan nel_number = 4; defparam instance3. starting_chan nel_number = 8 ; and so on for the remaining stamped instances. the logical channel addresses of the channels in the stamped instances are 0 , 4 , 8 , 12 , and 16 , respectively. ? determine the highest logical channel address (16). round it up to the next multiple of 4. set the what is the number of channels controlled by the controller? option in the reconfiguration settings screen to 20 . ? table 2?16. altgx and altgx_reconfig settings for instances 1 and 2 in cases 1 through 5 (part 2 of 2) example scenario altgx instance 1 settings altgx instance 2 settings altgx_reconfig instance 1 settings altgx_reconfig instance 2 settings
chapter 2: hardcopy iv gx dynamic reconfiguration 2?39 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 total number of channels controlled by the altgx_reconfig instance?pma-only channels consider the example scenario shown in table 2?13 on page 2?33 to see how to set the what is the number of channels controlled by the reconfig controller? option in the altgx_reconfig megawizard plug-in manager for the same example scenario. table 2?17 shows the altgx and altgx_reconfig settings in case 6. total number of channels controlled by the altgx_reconfig instance?pma-only channels and regular transceiver channels that are not in basic (pma direct) functional mode consider the example scenario shown in table 2?14 on page 2?34 to set the what is the number of channels controlled by the reconfig controller? option in the altgx_reconfig megawizard plug-in manager. table 2?18 shows the altgx and altgx_reconfig settings for instances 1 and 2 for case 7. table 2?17. altgx and altgx_reconfig settings for instances 1 and 2 in case 6 example scenario altgx instance 1 settings altgx instance 2 settings altgx_reconfig instance 1 settings case 6 eight pma-only channels. set the what is the starting channel number? option in the reconfig screen to 0 . the logical channel address of the first to eighth channels are 0 , 4 , 8 , 12 , 16 , 20 , 24 , and 28 , respectively. ? determine the highest logical channel address (28). round it up to the next multiple of 4. set the what is the number of channels controlled by the controller? option in the reconfiguration settings screen to 32 . table 2?18. altgx and altgx_reconfig settings for instances 1 and 2 in case 7 example scenario altgx instance 1 settings altgx instance 2 settings altgx_reconfig instance 1 settings case 7 five regular transceiver channels that are not in basic (pma direct) functional mode. set the what is the starting channel number? option in the reconfig screen to 0 . the logical channel address of the first to fifth channels are 0, 1 , 2 , 3 , and 4 , respectively. four pma-only channels. set the what is the starting channel number? option in the reconfig screen to 8 . the logical channel address of the first to fourth channels are 8 , 12 , 16 , and 20 , respectively. determine the highest logical channel address (20). round it up to the next multiple of 4. set the what is the number of channels controlled by the controller? option in the reconfiguration settings screen to 24 .
2?40 chapter 2: hardcopy iv gx dynamic reconfiguration quartus ii megawizard plug-in manager interfaces to support dynamic hardcopy iv device handbook, volume 3 ? june 2009 altera corporation connecting the reconfig_fromgxb and reconfig_togxb ports the reconfig_fromgxb and reconfig_togxb signals in the dynamic reconfiguration interface must be connected between the altgx_reconfig instance and the altgx instance to successfully complete the dynamic reconfiguration process: reconfig_togxb[3:0] ?this is an input port of the altgx instance and an output port of the altgx_reconfig instance. you must connect the reconfig_togxb[3:0] input port of every altgx instance controlled by the dynamic reconfiguration controller to the reconfig_togxb[3:0] output port of the altgx_reconfig instance. for more information, refer to figure 2?13 on page 2?41 . reconfig_fromgxb ?this is an output port in the altgx instance and an input port in the altgx_reconfig instance. this signal is transceiver-block based. therefore, the width of this signal increases in steps of 17 bits per transceiver block. in the altgx megawizard plug-in manager, the width of this signal depends on the following: whether the channels configured in the altgx instance are regular transceiver channels or pma-only channels. the number of channels you select in the what is the number of channels? option in the general screen. for example, if the channels in the altgx instance are regular transceiver channels and if you select the number of channels as follows: 1 channels 4, then the output port reconfig_fromgxb = 17 bits 5 channels 8, then the output port reconfig_fromgxb = 34 bits 9 channels 12, then the output port reconfig_fromgxb = 51 bits however, if the channels in the altgx instance are pma-only channels and if you select the number of channels as follows: number of pma-only channels = n, then the output port reconfig_fromgxb = n*17 bits (for example, reconfig_fromgxb = 6 * 17 bits for 6 pma-only channels) in the altgx_reconfig megawizard plug-in manager, the width of this signal depends on the value you select in the what is the number of channels controlled by the reconfig controller? option in the reconfiguration settings screen. for example, if you select the total number of channels controlled by altgx_reconfig instance as follows: 1 channels 4, then the input port reconfig_fromgxb = 17 bits 5 channels 8, then the input port reconfig_fromgxb = 34 bits 9 channels 12, then the input port reconfig_fromgxb = 51 bits
chapter 2: hardcopy iv gx dynamic reconfiguration 2?41 quartus ii megawizard plug-in manager interfaces to support dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 to connect the reconfig_fromgxb port between the altgx_reconfig instance and multiple altgx instances, follow these rules: ta k e th e reconfig_fromgxb[16:0] of altgx instance 1 and connect it to the reconfig_fromgxb[16:0] of the altgx_reconfig instance. connect the reconfig_fromgxb[] port of the next altgx instance to the next available bits of the altgx_reconfig instance, and so on. similarly, connect the reconfig_fromgxb port of the altgx instance, which has the highest what is the starting channel number? option, to the msb of the reconfig_fromgxb port of the altgx_reconfig instance. the quartus ii fitter produces an error if the dynamic reconfiguration option is enabled in the altgx instance but the reconfig_fromgxb and reconfig_togxb ports are not connected to the altgx_reconfig instance. connecting reconfig_fromgxb for regular transceiver channels figure 2?13 shows how to connect the reconfig_fromgxb output port of the altgx instance to the reconfig_fromgxb input port of the altgx_reconfig instance for regular transceiver channels. figure 2?13. reconfig_fromgxb and reconfig_togxb connections between the altgx_reconfig instance and the altgx instances (note 1) , (2) notes to figure 2?13 : (1) reconfig_fromgxb[50:0] = { reconfig_fromgxb[16:0] , reconfig_fromgxb[33:0] }. (2) figure 2?13 assumes that all the channels depicted are regular transceiver channels. altgx_reco nfig instance reconfig_fromgxb [50:0] (1) reconfig_fromgxb2 [33:0] reconfig_fromgxb1 [16:0] reconfig_togx b [3:0] reconfig_togx b [3:0] reconfig_togx b [3:0] altgx instance 2 altgx instance 1
2?42 chapter 2: hardcopy iv gx dynamic reconfiguration quartus ii megawizard plug-in manager interfaces to support dynamic hardcopy iv device handbook, volume 3 ? june 2009 altera corporation table 2?19 shows the connecting reconfig_fromgxb port for regular transceiver channels. you must connect the reconfig_fromgxb input port of the altgx_reconfig instance to both the reconfig_fromgxb1 output port of altgx instance 1 and the reconfig_fromgxb2 output port of altgx instance 2, as shown in figure 2?13 on page 2?41 . the lowest what is the starting channel number? option transceiver block is connected to the lowest significant bit and so on. the reconfig_fromgxb1 of altgx instance 1 must be connected to the reconfig_fromgxb[16:0] of the altgx_reconfig instance. similarly, the reconfig_fromgxb2 of altgx instance 2 must be connected to the reconfig_fromgxb[50:17] of the altgx_reconfig instance. connecting reconfig_fromgxb for the pma-only channels consider the scenario for pma-only channels. table 2?19. connecting the reconfig_fromgxb port for regular transceiver channels altgx settings and instances altgx_reconfig setting and instance altgx setting altgx instance 1 (basic functional mode) altgx instance 2 (basic functional mode) altgx_reconfig setting altgx_reconfig instance 1 what is the number of channels? option in the general screen 3 (regular transceiver channels) 5 (regular transceiver channels) what is the number of channels controlled by the reconfig controller? option in the reconfiguration settings screen. determine the highest logical channel address (8). round it up to the next multiple of 4. set this option to 12 . what is the starting channel number? option in the reconfig screen set this option to 0 . the logical channel addresses of the 1st to 3rd channels are 0, 1, and 2, respectively. set this option to 4. the logical channel addresses of the 1st to 5th channels are 4, 5, 6, 7, and 8, respectively. reconfig_ fromgxb1 and reconfig_ fromgxb2 outputs reconfig_ fromgxb1 is 17 bits wide ( 1 * 17) reconfig_ fromgxb2 is 34 bits wide ( 2 * 17) reconfig_ fromgxb input reconfig_ fromgxb is 51 bits wide ( 12 regular transceiver channels can logically fit into 3 transceiver blocks) table 2?20. connecting reconfig_fromgxb and reconfig_togxb for pma-only channels (part 1 of 2) altgx setting and instances altgx_reconfig settings and instance altgx megawizard plug-in manager settings altgx instance 1 configured in basic (pma direct) functional mode altgx instance 2 configured in basic (pma direct) functional mode altgx_reconfig megawizard plug-in manager settings altgx_reconfig instance 1
chapter 2: hardcopy iv gx dynamic reconfiguration 2?43 offset cancellation control for receiver channels ? june 2009 altera corporation hardcopy iv device handbook, volume 3 1 you must connect the reconfig_fromgxb input port of the altgx_reconfig instance to both the reconfig_fromgxb1 output port of altgx instance 1 and the reconfig_fromgxb2 output port of altgx instance 2, as follows: reconfig_fromgxb[101:0] = { reconfig_fromgxb2[84:0] , reconfig_fromgxb1[16:0]} the lowest what is the starting channel number? option transceiver block is connected to the lowest significant bit, and so on. the reconfig_fromgxb1 of altgx instance 1 must be connected to reconfig_fromgxb[16:0] of the altgx_reconfig instance. similarly, reconfig_fromgxb2 of altgx instance 2 must be connected to reconfig_fromgxb[101:17] of the altgx_reconfig instance. 1 the reconfig_togxb output of altgx_reconfig instance 1 is fixed to 3 bits and must be connected to the same reconfig_togxb ports of both the altgx instances. offset cancellation control for receiver channels as the silicon progresses toward smaller process nodes, the performance of circuits at these smaller nodes depends more on process variations. these process variations result in analog voltages being offset from required ranges. the hardcopy iv gx device provides an offset cancellation circuit per receiver channel to counter offset variations due to process, voltage, and temperature. the offset cancellation logic corrects these offsets. the receiver buffer and receiver clock data recovery require offset cancellation. what is the number of channels? option in the general screen 1 (pma-only channels) 5 (pma-only channels) what is the number of channels controlled by the reconfig controller? option in the reconfiguration settings screen determine the highest logical channel address (20). round it up to the next multiple of 4. set this option to 24 what is the starting channel number? option in the reconfig screen set this option to 0 . the logical channel address of the first channel is 0 . set this option to 4 . the logical channel addresses of the first to fifth channels are 4 , 8 , 12 , 16 , and 20 , respectively. reconfig_ fromgxb1 and reconfig_ fromgxb2 outputs reconfig_ fromgxb1 is 17 bits wide ( 1 * 17) reconfig_ fromgxb2 is 85 bits wide ( 5 * 17) reconfig_ fromgxb input reconfig_ fromgxb is 102 bits wide ( 6 * 17, 24 channels can logically fit into 6 transceiver blocks) table 2?20. connecting reconfig_fromgxb and reconfig_togxb for pma-only channels (part 2 of 2) altgx setting and instances altgx_reconfig settings and instance
2?44 chapter 2: hardcopy iv gx dynamic reconfiguration offset cancellation control for receiver channels hardcopy iv device handbook, volume 3 ? june 2009 altera corporation offset cancellation is automatically executed once every time the device is powered on. the control logic for offset cancellation is integrated into the dynamic reconfiguration controller. you must connect the altgx_reconfig instance to the altgx instances with receiver channels in your design. you must connect the reconfig_fromgxb, reconfig_togxb , and necessary clock signals to both the altgx_reconfig and altgx (with receiver channels) instances. 1 for proper device operation, you must always connect the altgx_reconfig and altgx (with receiver channels) instances. 1 the offset cancellation control functionality remains the same for both regular transceiver channels and pma-only channels. operation every altgx instance for receiver and transmitter or receiver only configurations require that the offset cancellation for receiver channels option is enabled in the reconfig screen of the altgx megawizard plug-in manager. this option is enabled by default for the above two configurations, as shown in figure 2?14 . it is disabled for the transmitter only configuration.
chapter 2: hardcopy iv gx dynamic reconfiguration 2?45 offset cancellation control for receiver channels ? june 2009 altera corporation hardcopy iv device handbook, volume 3 figure 2?14 shows the offset cancellation for receiver channels option enabled by default in the altgx instance. because this option is enabled by default, the altgx instance must be connected to an altgx_reconfig instance (dynamic reconfiguration controller). the offset cancellation controls are also enabled by default in the reconfiguration settings screen of the altgx_reconfig instance. you must also set the starting channel number in the what is the starting channel number? option for every altgx instance connected to the altgx_reconfig instance. for more information, refer to ?logical channel addressing? on page 2?23 . figure 2?14. offset cancellation for receiver channels option in the altgx megawizard plug-in manager
2?46 chapter 2: hardcopy iv gx dynamic reconfiguration offset cancellation control for receiver channels hardcopy iv device handbook, volume 3 ? june 2009 altera corporation figure 2?15 shows the offset cancellation for receiver channels option enabled by default in the altgx_reconfig megawizard plug-in manager. when the device powers up, the dynamic reconfiguration controller initiates offset cancellation on the receiver channel by disconnecting the receiver input pins from the receiver data path. it also sets the receiver cdr into a fixed set of dividers to guarantee a voltage controlled oscillator (vco) clock rate within the range necessary to provide proper offset cancellation. subsequently, the offset cancellation process goes through different states and culminates in the offset cancellation of the receiver buffer and receiver cdr. after offset cancellation is complete, the user divider settings are restored. the dynamic reconfiguration controller sends and receives data to the transceiver channel through the reconfig_togxb and reconfig_fromgxb signals. you must connect these signals between the altgx_reconfig instance and the altgx instance. you must also set the what is the number of channels controlled by the reconfig controller? option in the reconfiguration settings screen of the altgx_reconfig megawizard plug-in manager. for more information, refer to ?total number of channels controlled by the altgx_reconfig instance? on page 2?35 . the use 'logical_channel_address' port for analog controls reconfiguration option in the analog controls screen of the altgx_reconfig megawizard plug-in manager is not applicable for the receiver offset cancellation process. 1 if the design does not require pma controls reconfiguration and uses optimum le resources, you can connect all the altgx instances in the design to a single dynamic reconfiguration controller (altgx_reconfig instance). figure 2?15. offset cancellation for receiver channels option in the altgx_reconfig megawizard plug-in manager
chapter 2: hardcopy iv gx dynamic reconfiguration 2?47 offset cancellation control for receiver channels ? june 2009 altera corporation hardcopy iv device handbook, volume 3 1 the gxb_powerdown signal must not be asserted during the offset cancellation sequence. 1 to understand the impact on system start-up when you control all the transceiver channels using a single dynamic reconfiguration controller, refer to ?pma controls reconfiguration duration? on page 2?143 . in this example, the design has altgx instances with channels of both transmitter only and receiver only configurations. you must include the transmitter only channels while setting the what is the starting channel number? option in the altgx instance and setting the what is the number of channels controlled by the reconfig controller? option in the altgx_reconfig instance for receiver offset cancellation. after the device powers up, the busy signal remains low for the first reconfig_clk clock cycle. the busy signal then gets asserted for the second reconfig_clk clock cycle, when the dynamic reconfiguration controller initiates the offset cancellation process. the de-assertion of the busy signal indicates the successful completion of the offset cancellation process. figure 2?16 shows the dynamic reconfiguration signals transition during offset cancellation on receiver channels. 1 due to the offset cancellation process, the transceiver reset sequence has changed. for more information, refer to the reset control and power down chapter in volume 2 of the stratix iv device handbook . figure 2?16. dynamic reconfiguration signals transition during offset cancellation on receiver channels note to figure 2?16 : (1) after device power up, the busy signal remains low for the first reconfig_clk cycle. reconfig_clk busy (1)
2?48 chapter 2: hardcopy iv gx dynamic reconfiguration offset cancellation control for receiver channels hardcopy iv device handbook, volume 3 ? june 2009 altera corporation example for the offset cancellation process of a receiver channel you must always connect the altgx_reconfig instance to the altgx instances. even if you do not require dynamic reconfiguration, you must set the options described in table 2?21 . table 2?21 describes the various altgx_reconfig and altgx megawizard plug-in manager settings that you must set to perform the offset cancellation process of a receiver channel. table 2?21. example for the offset cancellation process of a receiver channel altgx setting and instances altgx_reconfig settings and instance altgx setting altgx instance 1 altgx instance 2 altgx_reconfig setting altgx_reconfig instance 1 what is the number of channels? option in the general screen 5 (regular transceiver channels) 3 (regular transceiver channels) what is the number of channels controlled by the reconfig controller? option in the reconfiguration settings screen. for more information about this setting, refer to ?total number of channels controlled by the altgx_reconfig instance? on page 2?35 . determine the highest logical channel address (10). round it up to the next multiple of 4. set this option to 12 . what is the starting channel number? option in the reconfig screen. for more information, refer to ?logical channel addressing? on page 2?23 . set this option to 0 . the logical channel addresses of the 1st to 5th channels are 0 , 1 , 2 , 3 , and 4 , respectively. set this option to 8 . the logical channel addresses of the 1st to 3rd channels are 8 , 9 , and 10 , respectively. reconfig_ fromgxb1 and reconfig_ fromgxb2 outputs. reconfig_ fromgxb1 is 34 bits wide (2 * 17) reconfig_ fromgxb2 is 17 bits wide (1 * 17) reconfig_ fromgxb input reconfig_ fromgxb is 51 bits wide (3 * 17, 12 channels can logically fit into 3 transceiver blocks)
chapter 2: hardcopy iv gx dynamic reconfiguration 2?49 the rx_tx_duplex_sel[1:0] port ? june 2009 altera corporation hardcopy iv device handbook, volume 3 figure 2?17 shows the altgx_reconfig instance connected to both the altgx instance 1 and altgx instance 2. altgx instances and altgx_reconfig instance connections 1. connect the reconfig_fromgxb1[33:0] output port from altgx instance 1 to the reconfig_fromgxb[33:0] input port of the altgx_reconfig instance. 2. similarly, connect the reconfig_fromgxb2[16:0] output port from altgx instance 2 to the reconfig_fromgxb[50:17] input port of the altgx_reconfig instance. 3. connect the reconfig_togxb[3:0] output port of the altgx_reconfig instance to the reconfig_togxb[3:0] input ports of both altgx instance 1 and altgx instance 2. for more information, refer to ?connecting the reconfig_fromgxb and reconfig_togxb ports? on page 2?40 . dynamic reconfiguration controller-offset cancellation control sequence 1. the altgx_reconfig instance automatically performs offset cancellation on all receiver channels of the altgx instances connected to it on power up. 2. the busy signal is low for the first reconfig_clk clock cycle after power up. 3. the busy signal gets asserted for the second reconfig_clk clock cycle after power up. 4. the de-assertion of the busy signal indicates the successful completion of the offset cancellation process. the rx_tx_duplex_sel[1:0] port the width of the rx_tx_duplex_sel port is fixed to 2 bits. the rx_tx_duplex_sel[1:0] port is available for selection in all dynamic reconfiguration modes. figure 2?17. example of the altgx_reconfig and altgx instances set up for the offset cancellation process of a receiver channel notes to figure 2?17 : (1) reconfig_fromgxb[50:0] = { reconfig_fromgxb2[16:0] , reconfig_fromgxb1[33:0]}. (2) all the channels are regular transceiver channels. altgx_reco nfig instance set the what is the number of channels controlled by the reconfig controller? option = 12 set the what is the starting channel number? option = 8 set the what is the starting channel number? option = 0 reconfig_fromgxb[50:0] (1) reconfig_fromgxb2[16:0] reconfig_fromgxb1[33:0] bu sy altgx instance 2 (number of channels is 3) altgx instance 1 (number of channels is 5) reconfig_clk
2?50 chapter 2: hardcopy iv gx dynamic reconfiguration the rx_tx_duplex_sel[1:0] port hardcopy iv device handbook, volume 3 ? june 2009 altera corporation you can enable this port by selecting the use 'rx_tx_dupl ex_sel' port to enable rx only and tx only or duplex reconfiguration options in the error checks/data rate switch screen of the altgx_reconfig megawizard plug-in manager, as shown in figure 2?18 . this option is available only when you select one of the dynamic reconfiguration modes (in addition to the default offset cancellation for receiver channels option) in the reconfiguration settings screen of the altgx_reconfig megawizard plug-in manager. table 2?22 shows the settings for the rx_tx_duplex_sel [1:0] input port of the altgx_reconfig instance for this port. for .mif -based dynamic reconfiguration modes, the advantage of using the rx_tx_duplex_sel [1:0] port is that you can inform the dynamic reconfiguration controller to load only the receiver settings, transmitter settings, or both receiver and transmitter settings, through this port. figure 2?18. use 'rx_tx_duplex_sel' port to enable rx only option and the tx only or duplex reconfiguration options in the altgx_reconfig megawizard plug-in manager table 2?22. setting the rx_tx_duplex_sel[1:0] input port of the altgx_reconfig instance rx_tx_duplex_sel[1:0] reconfiguration mode 2?b00 receiver and transmitter 2?b01 receiver only 2?b10 transmitter only 2?b11 unsupported value note to tab l e 2 ?2 2 : (1) for more information, refer to ?dynamic reconfiguration controller port list? on page 2?11 .
chapter 2: hardcopy iv gx dynamic reconfiguration 2?51 the logical_channel_address port ? june 2009 altera corporation hardcopy iv device handbook, volume 3 consider a scenario where a receiver only altgx instance is controlled by the dynamic reconfiguration controller and the .mif contains all the transmitter settings. enabling the rx_tx_duplex_sel [1:0] port in this scenario and setting it to 2?b01 ensures that the dynamic reconfiguration controller writes nothing into the physical transmitter portion of the receiver only altgx instance (because the .mif contains transmitter settings that are not applicable to the receiver only configuration). the logical_channel_address port the logical_channel_address port is used to select a specific channel that is controlled by the altgx_reconfig instance. the logical_channel_address port is optional for the following mode: pma controls reconfiguration mode however, it is always available for the following dynamic reconfiguration modes: data rate division in tx mode channel and tx pll select/reconfig modes figure 2?19 shows the use 'logical_channel_address' port for analog controls reconfiguration option in the analog controls screen of the altgx_reconfig megawizard plug-in manager. figure 2?19. the logical_channel_address port in the altgx_reconfig megawizard plug-in manager
2?52 chapter 2: hardcopy iv gx dynamic reconfiguration pma controls reconfiguration hardcopy iv device handbook, volume 3 ? june 2009 altera corporation the width of the logical_channel_address port depends on the following two conditions: what number you set in the what is the number of channels controlled by the reconfig controller? option in the reconfiguration settings screen. the maximum width of this port is 9 bits (because 9 bits are required to represent a maximum number of 384 channels). whether the channel controlled by the altgx_reconfig instance is a regular transceiver channel or pma-only channel. table 2?23 shows the width of the logical_channel_address port set differently for regular transceiver channels and pma-only channels. pma controls reconfiguration you can reconfigure the following pma controls: pre-emphasis settings equalization settings dc gain settings voltage output differential (v od ) settings cmu channels these are cmu plls configured in basic (pma direct) functional mode (pma-only channels). for the cmu channels, dynamic reconfiguration involves reconfiguring the following: pma controls reconfiguration only 1 for basic (pma direct) 1 and n configurations, only pma controls reconfiguration is available. the following dynamic reconfigurations cannot be achieved for the cmu channels in the hardcopy iv gx device: 1 to n, or vice versa n mode to another n mode 1 pma controls reconfiguration is available for both regular transceiver channels and cmu channels. table 2?23. width of the logical_channel_address port for regular transceiver channels versus pma-only channels eight regular transceiver channels eight pma-only channels logical_channel_address port width = 3 bits logical_channel_address port width = 5 bits
chapter 2: hardcopy iv gx dynamic reconfiguration 2?53 pma controls reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 dynamic reconfiguration controller ports for pma controls the pma control ports for the altgx_reconfig megawizard plug-in manager are available in the analog controls screen, as shown in figure 2?20 . here you can select the pma control ports you want to reconfigure (for example, use tx_vodctrl to write new v od settings or tx_vodctrl_out to read the existing v od settings). dynamically reconfiguring pma controls you can dynamically reconfigure the pma controls of a transceiver channel using two methods: method 1?you can reconfigure the pma controls of a specific transceiver channel. for more information, refer to ?method 1? on page 2?54 . method 2?you can dynamically reconfigure the pma controls of the transceiver channels without using the logical_channel_address port. if you use this method, the pma controls of all the transceiver channels connected to the dynamic reconfiguration controller are reconfigured. for more information, refer to ?method 2? on page 2?56 . for both methods, you can additionally use the rx_tx_duplex_sel [1:0] port. the width of this port is fixed to 2 bits. the two methods are described in the following sections. figure 2?20. dynamic reconfiguration controller ports for pma controls in the altgx_reconfig megawizard plug-in manager
2?54 chapter 2: hardcopy iv gx dynamic reconfiguration pma controls reconfiguration hardcopy iv device handbook, volume 3 ? june 2009 altera corporation method 1 using method 1, you can dynamically reconfigure the pma controls of a transceiver channel by using the logical_channel_address port without affecting the remaining active channels. you can enable the logical_channel_address_port port by selecting the use 'logical_channel_address' port for analog controls reconfiguration option in the analog controls screen, as shown in figure 2?19 on page 2?51 . this method is applicable only for a design where the dynamic reconfiguration controller controls more than one channel. you can additionally reconfigure either the receiver portion, transmitter portion, or both the receiver and transmitter portions of the transceiver channel by setting the corresponding value on the rx_tx_duplex_sel [1:0] input port. connecting the pma control ports when using method 1, the selected pma control ports remain fixed in width, regardless of the number of channels controlled by the altgx_reconfig instance: tx_vodctrl and tx_vodctrl_out are fixed to 3 bits tx_preemp_0t, tx_preemp_1t, tx_preemp_2t, tx_preemp_0t_out, tx_preemp_1t_out and tx_preemp_2t_out are fixed to 5 bits rx_eqdcgain and rx_eqdcgain_out are fixed to 3 bits rx_eqctrl and rx_eqctrl_out are fixed to 4 bits write transaction set the selected pma control ports to the desired settings (for example, tx_vodctrl = 3'b000). set the input port logical_channel_address to the logical channel address of the transceiver channel whose pma controls you want to reconfigure. set the rx_tx_duplex_sel [1:0] port to 2'b10 so that only the transmit pma controls are written to the transceiver channel. ensure that the busy signal is low before you start a write transaction. assert the write_all signal for one reconfig_clk clock cycle. this initiates the write transaction. the busy output status signal is asserted high to indicate that the dynamic reconfiguration controller is busy writing the pma control values. when the write transaction has completed, the busy signal goes low. figure 2?21 shows the write transaction waveform.
chapter 2: hardcopy iv gx dynamic reconfiguration 2?55 pma controls reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 read transaction in this example, you want to read the existing v od values from the transmit v od control registers of the transmitter portion of a specific channel controlled by the altgx_reconfig instance. the read transaction in this scenario is explained in the following steps: 1. set the input logical_channel_address port to the logical channel address of the transceiver channel whose pma controls you want to read (for example, tx_vodctrl_out ). 2. set the rx_tx_duplex_sel [1:0] port to 2'b10 so that only the transmit pma controls are read from the transceiver channel. 3. ensure that the busy signal is low before you start a read transaction. 4. assert the read signal for one reconfig_clk clock cycle. this initiates the read transaction. the busy output status signal is asserted high to indicate that the dynamic reconfiguration controller is busy reading the pma control values. once the read transaction has completed, the busy signal goes low. the data_valid signal gets asserted indicating that the data available at the read control signal is valid. figure 2?21. method 1?write transaction waveform notes to figure 2?21 : (1) consider that you want to write to only the transmitter portion of the channel. (2) this waveform assumes that the number of channels connected to the dynamic reconfiguration c ontroller is four. therefore, th e logical_channel_address port is 2 bits wide. reconfig_clk rx_tx_duplex_sel [1:0] (1 ) write_all 2?b00 2?b10 2?b01 2?b00 3?b000 3?b111 busy tx_vodctrl [2:0] logical_address_channel [1:0] (2)
2?56 chapter 2: hardcopy iv gx dynamic reconfiguration pma controls reconfiguration hardcopy iv device handbook, volume 3 ? june 2009 altera corporation figure 2?22 shows the read transaction waveform. 1 simultaneous write and read transactions are not allowed. method 2 method 2 does not require the logical_channel_address port to dynamically reconfigure the pma controls of the transceiver channels. using method 2, the pma controls of all the transceiver channels connected to the altgx_reconfig instance are reconfigured. method 2 is further classified into: the use the same control signal for all the channels option enabled the use the same control signal for all the channels option disabled figure 2?22. method 1?read transaction waveform notes to figure 2?22 : (1) consider that you want to read from only the transmitter portion of the channel. (2) this waveform assumes that the number of channels connected to the dynamic reconfiguration c ontroller is four. therefore, th e logical_channel_address port is 2 bits wide. reconfig_clk rx_tx_duplex_sel [1:0] (1) write_all 2?b00 2?b10 2?b01 2?b00 3?b000 3?b0 3?bxxx busy tx_vodctrl [2:0] logical_address_channel [1:0] (2) data_valid
chapter 2: hardcopy iv gx dynamic reconfiguration 2?57 pma controls reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 figure 2?23 shows the use the same control signal for all channels option in the altgx_reconfig megawizard plug-in manager. use the same control signal for all channels option enabled the use the same control signal for all channels option is available in the analog controls screen of the altgx_reconfig megawizard plug-in manager. if enabled, the width of the pma control ports are fixed as shown below. pma control ports used in a write transaction: tx_vodctrl is fixed to 3 bits tx_preemp_0t, tx_preemp_1t , and tx_preemp_2t are fixed to 5 bits rx_eqdcgain is fixed to 3 bits rx_eqctrl is fixed to 4 bits pma control ports used in a read transaction: tx_vodctrl_out is 3 bits per channel tx_preemp_0t_out, tx_preemp_1t_out , and tx_preemp_2t_out are 5 bits per channel rx_eqdcgain_out is 3 bits per channel rx_eqctrl_out is to 4 bits per channel for example, if the number of channels controlled by the dynamic reconfiguration controller is 2, tx_vodctrl_out is 6 bits wide. figure 2?23. use the same control signals for all channels option in the altgx_reconfig megawizard plug-in manager
2?58 chapter 2: hardcopy iv gx dynamic reconfiguration pma controls reconfiguration hardcopy iv device handbook, volume 3 ? june 2009 altera corporation write transaction the value you set at the selected pma control ports gets written to all the transceiver channels connected to the altgx_reconfig instance. consider that you have enabled tx_vodctrl in the altgx_reconfig megawizard plug-in manager to reconfigure the v od of the transceiver channels. the following are the steps involved in the write transaction to reconfigure the v od , as shown in figure 2?24 : 1. before you initiate a write transaction, set the selected pma control ports to the desired settings (for example, tx_vodctrl = 3'b000). 2. set the rx_tx_duplex_sel [1:0] port to 2'b10 so that only the transmit pma controls are written to the transceiver channel. 3. ensure that the busy signal is low before you start a write transaction. 4. assert the write_all signal for one reconfig_clk clock cycle. this initiates the write transaction. 5. the busy output status signal is asserted high to indicate that the dynamic reconfiguration controller is busy writing the pma control values. once the write transaction has completed, the busy signal goes low . figure 2?24. method 2: write transaction waveform?use the same control signal for all channels option enabled note to figure 2?24 : (1) consider that you want to write to only the transmitter portion of the channel. reconfig_clk rx_tx_duplex_sel [1:0] write_all (1) 2?b00 2?b10 3?b000 3?b111 busy tx_vodctrl [2:0]
chapter 2: hardcopy iv gx dynamic reconfiguration 2?59 pma controls reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 read transaction if you want to read the existing values from a specific channel connected to the altgx_reconfig instance, observe the corresponding byte positions of the pma control output port after the read transaction is complete. for example, if the number of channels controlled by the altgx_reconfig instance is 2, the tx_vodctrl_out is 6 bits wide. the tx_vodctrl_out[2:0] corresponds to channel 1 and similarly, tx_vodctrl_out[5:3] corresponds to channel 2. the following list shows the steps to read the v od values of the second channel: 1. before you initiate a read transaction, set the rx_tx_duplex_sel [1:0] port to 2'b10 so that only the transmit pma controls are read from the transceiver channel. 2. ensure that the busy signal is low before you start a read transaction. 3. assert the read signal for one reconfig_clk clock cycle. this initiates the read transaction. 4. the busy output status signal is asserted high to indicate that the dynamic reconfiguration controller is busy reading the pma control settings. 5. once the read transaction has completed, the busy signal goes low. the data_valid signal is asserted, indicating that the data available at the read control signal is valid. to read the current v od values in channel 2, observe the values in tx_vodctrl_out[5:3].
2?60 chapter 2: hardcopy iv gx dynamic reconfiguration pma controls reconfiguration hardcopy iv device handbook, volume 3 ? june 2009 altera corporation figure 2?25 shows the read transaction waveform. it assumes that the transmit v od settings written in channels 1 and 2 prior to the read transaction are 3'b001 and 3'b010, respectively. 1 simultaneous write and read transactions are not allowed. use the same control signal for all channels option disabled when the use the same control signal for all channels option is disabled, the pma control ports for write transaction are separate for each channel. pma control ports used in a write transaction: tx_vodctrl is 3 bits per channel tx_preemp_0t, tx_preemp_1t , and tx_preemp_2t are 5 bits per channel rx_eqdcgain is 3 bits per channel rx_eqctrl is 4 bits per channel for example, if you have two channels, tx_vodctrl is 6 bits wide ( tx_vodctrl[2:0] corresponds to channel 1 and tx_vodctrl[5:3] corresponds to channel 2). figure 2?25. method 2?read transaction waveform note to figure 2?25 : (1) consider that you want to read from only the transmitter portion of all the channels. reconfig_clk rx_tx_duplex_sel [1:0] read (1 ) 2?b00 2?b10 6?bxxxxxx 6?b010001 6?b000000 busy tx_vodctrl [5:0] data_valid
chapter 2: hardcopy iv gx dynamic reconfiguration 2?61 pma controls reconfiguration ? june 2009 altera corporation hardcopy iv device handbook, volume 3 pma control ports used in a read transaction the width of the pma control ports for a read transaction are always separate for each channel (the same as the pma control ports, as explained in ?use the same control signal for all channels option enabled? on page 2?57 ). write transaction because the pma controls of all channels are written, if you want to reconfigure a specific channel connected to the altgx_reconfig instance, set the new value to the corresponding pma control port of the channel under consideration and retain the previously stored values in the other active channels using a read transaction prior to this write transaction. for example, assume that the number of channels controlled by the altgx_reconfig is 2, tx_vodctrl in this case is 6 bits wide. the tx_vodctrl[2:0] corresponds to channel 1, and similarly, tx_vodctrl[5:3] corresponds to channel 2. follow these steps: 1. if you want to dynamically reconfigure the pma controls of only channel 2 with a new value, first perform a read transaction to retrieve the existing pma control values from tx_vodctrl_out[5:0] . take tx_vodctrl_out[2:0] and provide this value in tx_vodctrl[2:0] to the write in channel 1. by doing so, channel 1 gets overwritten with the same value. 2. perform a write transaction. this ensures that the new values are written only to channel 2, while channel 1 remains unchanged.
2?62 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation figure 2?26 shows a write transaction waveform with the use the same control signal for all channels option disabled. 1 simultaneous write and read transactions are not allowed. read transaction the read transaction is explained in ?read transaction? on page 2?59 . description of transceiver channel reconfiguration modes this section describes the following dynamic reconfiguration modes: data rate division in tx mode channel and tx pll select/reconfig modes channel and cmu pll reconfiguration channel reconfiguration with tx pll select cmu pll reconfiguration figure 2?26. method 2: write transaction waveform with the use the same control signal for all channels option disabled notes to figure 2?26 : (1) consider that you want to write to only the transmitter portion of the channel. (2) the waveform assumes that the number of channels controlled by the dynamic reconfiguration controller (altgx_reconfig instan ce) is 2 and that the tx_vodctrl control port is enabled. reconfig_clk (1) (2) rx_tx_duplex_sel [1:0] write_all 2?b00 2?b10 6?b000011 6?b000000 busy tx_vodctrl [5:0]
chapter 2: hardcopy iv gx dynamic reconfiguration 2?63 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 1 you can enable all the above dynamic reconfiguration modes together by selecting the enable channel and transmitter pll reconfiguration option in the reconfig screen of the altgx megawizard plug-in manager (shown in figure 2?27 ). (you do not have the option to individually enable any of the above dynamic reconfiguration modes in the altgx megawizard plug-in manager.) data rate division in tx mode you can use the date rate division in tx mode to modify the data rate of the transmitter channel in multiples of 1, 2, and 4. this dynamic reconfiguration mode is available only for the transmit side and not for the receive side. figure 2?27. the enable channel and transmitter pll reconfiguration option in the altgx megawizard plug-in manager
2?64 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation blocks reconfigured in the data rate division in tx mode the only block that is reconfigured by this mode is the tx local divider block of a transmitter channel. the tx local divider can be set to a divide by value of /1, /2, or /4, as shown in figure 2?28 . you must be aware of the device operating range before you enable and use this feature. there are no legal checks that are imposed by the quartus ii software because it is an on-the-fly control feature. you also need to ensure that a specific functional mode supports the data rate range before dividing the clock when using this rate switch option. 1 the date rate division in tx mode is applicable only to regular transceiver channels and not the pma-only channels. altgx megawizard plug-in manager setup enable the following settings in the altgx megawizard plug-in manager: 1. select the channel and transmitter pll reconfiguration option in the reconfig screen to enable the altgx_reconfig instance to modify the tx channel local divider values dynamically. 2. set the what is the starting channel number? option in the reconfig screen. for more information, refer to ?logical channel addressing? on page 2?23 . the alternate reference clock is not required because a single clock source is used. the /1, /2, or /4 data rates can be derived from the single input reference clock. figure 2?28. local divider of a transmitter channel high-speed clock from tx pll0 high-speed clock from tx pll1 /n /1, /2, or /4 /4, /5, /8, or /10 high-speed serial clock lo w -speed parallel clock
chapter 2: hardcopy iv gx dynamic reconfiguration 2?65 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 altgx_reconfig m egawizard plug-in manager setup enable the following settings in the altgx_reconfig megawizard plug-in manager for data rate division in tx mode: 1. set the what is the number of channels controlled by the reconfig controller? option in the reconfiguration settings screen. for more information, refer to ?total number of channels controlled by the altgx_reconfig instance? on page 2?35 . 2. specify the logical channel address of the transmitter channel at the logical_channel_address input port. 3. select the data rate division in tx option in the reconfiguration settings screen, as shown in figure 2?29 . 4. the rate_switch_ctrl[1:0] input port is available when you enable the data rate division in tx option. the value you set at the rate_switch_ctrl[1:0] signal determines the tx local divider settings, as shown in table 2?24 . figure 2?29. the data rate division in tx option in the altgx_reconfig megawizard plug-in manager table 2?24. tx local divider settings based on the rate_switch_ctrl[1:0] port rate_switch_ctrl[1:0] local divider settings 2?b00 divide by 1 2?b01 divide by 2 2?b10 divide by 4 2?b11 not supported
2?66 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation if you want to read the existing local divider settings of the transmitter channel, select the use 'rate_switch_out' port to read out the current data rate division option in the error checks/data rate switch screen. decoding for the rate_switch_out[1:0] output signal is the same as the rate_switch_ctrl[1:0] input signal. 1 dynamic rate switch has no effect on the dividers on the receive side of the transceiver channel. it can be used only for the transmitter. 1 the data rate division in tx mode does not require a .mif . for more information about read and write transactions, refer to ?data rate division in tx: operation? in the following section. data rate division in tx: operation the following sections describe the steps involved in write and read transactions for the data rate division in tx mode. data rate division in tx: write transaction 1. set the reconfig_mode_sel[2:0] signal to 3?b011 to activate this mode. 2. set the rate_switch_ctrl[1:0] signal to the corresponding tx local divider setting. 3. set the logical_channel_address port to the logical channel address of the transmitter channel whose local divider settings you want to reconfigure. 4. ensure that the busy signal is low. 5. initiate a write transaction by asserting the write_all signal for one reconfig_clk cycle.
chapter 2: hardcopy iv gx dynamic reconfiguration 2?67 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 figure 2?30 shows a write transaction in data rate division in tx mode. data rate division in tx: read transaction 1. set the reconfig_mode_sel[2:0] signal to 3?b011 to activate this mode. 2. select the rate_switch_out[1:0] signal to read out the existing tx local divider settings. 3. set the logical_channel_address port to the logical channel address of the transmitter channel whose local divider settings you want to read. 4. ensure that the busy signal is low. 5. assert the read signal for one reconfig_clk cycle. figure 2?30. write transaction in data rate division in tx mode notes to figure 2?30 : (1) the waveform assumes that you want to reconfigure the local divider settings of the transmitter channel to ?divide by 4?. th erefore, the value set at rate_switch_ctrl[1:0 ] is 2'b10. (2) the waveform assumes that the value set in the what is the number of channels controlled by the reconfig controller? option of the altgx_reconfig megawizard plug-in manager is 4 . therefore, the logical_channel_address input is 2 bits wide. (3) the waveform also assumes that you want to reconfigure the local divider settings of the transmitter channel whose logical channel address is 2'b01. busy 2'bxx 2'b01 2'bxx 2'b10 2'bxx 2'bxx 3'b011 3'bxxx reconfig_mode_sel[2:0] reconfig_clk rate_s w itch_ctrl[1:0] (1) logical_channel_address (2), (3) w rite_all
2?68 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation figure 2?31 shows a read transaction waveform in data rate division in tx mode. 1 do not perform a read transaction in date rate division in tx mode if rate_switch_out[1:0] is not selected in the altgx_reconfig megawizard plug-in manager. channel and tx pll select/reconfig modes a .mif is required when you want to dynamically: enable or disable functional blocks of the transceiver channel (use channel and cmu pll reconfiguration mode) reconfigure the functional mode of the transceiver channel from one to another (use channel and cmu pll reconfiguration mode) reconfigure the core fabric transceiver channel interface from one width to another (use channel and cmu pll reconfiguration mode) reconfigure the data rate of the transceiver channel by selecting another transmitter pll (use channel reconfiguration with tx pll select mode) reconfigure the data rate of the transceiver channel by reconfiguring the cmu pll (use cmu pll reconfiguration mode) figure 2?31. read transaction in data rate division in tx mode notes to figure 2?31 : (1) the waveform assumes that the existing local divider settings of the transmitter channel are ?divide by 2?. therefore, the v alue read out at rate_switch_out[1:0] is 2'b01. (2) the waveform assumes that the value set in the what is the number of channels controlled by the reconfig controller? option of the altgx_reconfig megawizard plug-in manager is 4 . therefore, the logical_channel_address input is 2 bits wide. (3) the waveform assumes that you want to read the existing local divider settings of the transmitter channel whose logical chan nel address is 2'b01. read busy 2'bxx 2'b01 2'bxx invalid output 2'b01 2'bxx 3'b011 3'bxxx reconfig_mode_sel[2:0] reconfig_clk logical_channel_address (1), (2) rate_s witch_out[1:0] (3) data_v alid
chapter 2: hardcopy iv gx dynamic reconfiguration 2?69 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 .mif generation to understand using .mifs , it is helpful to understand these two concepts: how to generate a .mif ??the quartus ii software generates .mifs when you provide the appropriate project settings (for more information, refer to ?quartus ii settings for .mif generation? on page 2?70 ) and then compile an altgx instance. how is a .mif used between the altgx_reconfig instance and the altgx instance??the quartus ii software provides a design flow called the user memory initialization file flow, as explained below. .mif-based design flow the .mif -based design flow involves writing the contents of the .mif to the transceiver channel or cmu pll. when you want to reconfigure the transceiver channel or cmu pll, you must configure the required settings for the transceiver channel or cmu pll in the altgx megawizard plug-in manager and compile the altgx instance. the dynamic reconfiguration controller requires that you write these configured settings through the .mif into the transceiver channel or cmu pll (using the write_all and reconfig_data[15:0] signals). the maximum possible size of the .mif is 55 words. each word contains legal register settings of the transceiver channel stored in 16 bits. reconfig_address_out[5:0] provides the address (location) of the 16- bit word in the .mif . the .mif size depends on the altgx configuration shown in table 2?25 . 1 the dynamic reconfiguration controller ignores a new 16-bit word if the previously initiated write transaction is not complete. as explained previously, an ongoing or active write transaction is signified by the busy signal. you can only input a new word of 16 bits when the busy signal is de-asserted. the quartus ii software creates the .mif under the /reconfig_mif folder. the file name is based on the altgx instance name ( .mif ), for example, basic_gxb .mif . one design can have multiple .mifs (there is no limit) and you can use one .mif to reconfigure multiple channels. you can store these .mifs in on-chip or off-chip memory. table 2?25. .mif size for the altgx configuration altgx configuration .mif size in words (1) duplex (receiver and transmitter) 55 receiver only 37 transmitter only 19 note to tab l e 2 ?2 5 : (1) each word in the .mif is 16 bits wide.
2?70 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation quartus ii settings for .mif generation the .mif is not generated by default in a quartus ii compilation. this following are the quartus ii software settings you must enable to generate a .mif file: 1. on the assignments menu, select settings ( figure 2?32 ). 2. select fitter settings, then choose more settings ( figure 2?33 ). figure 2?32. step 1 to enable .mif generation figure 2?33. step 2 to enable .mif generation
chapter 2: hardcopy iv gx dynamic reconfiguration 2?71 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 3. in the option box of the more fitter settings page, set the generate gxb reconfig mif option to on based on the dynamic reconfiguration mode enabled ( figure 2?34 ). the .mif is generated in the assembler stage of the compilation process. however, for any change in the design or the above settings, the quartus ii software runs through the fitter stage before starting the assembler stage. reusing .mifs to configure the transceiver plls and receiver plls for multiple data rates, it is important to understand the input reference clock requirements. this helps you to efficiently create the clocking scheme for reconfiguration and to reuse the .mifs across all channels in the device. this section reviews the new clocking enhancements and the implications of using input clocks from various clock sources. the available clock inputs appear as a pll_inclk_rx_cruclk[] port and can be provided from the inter-transceiver block lines (also known as inter quad [iq] lines), from the global clock networks that are driven by an input pin, or by a pll cascade clock. 1 for more information about input reference clocking, refer to the input reference clocking section of the stratix iv transceiver clocking chapter of volume 2 of the stratix iv device handbook . the following section describes the clocking requirements to reuse .mifs . figure 2?34. step 3 to enable .mif generation
2?72 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation input reference clock requirements for reusing .mifs the .mif contains information about the input clock multiplexer settings and the functional blocks that you selected during the altgx megawizard plug-in manager instantiation. when you enable the quartus ii settings described in the section, the quartus ii software generates a .mif for each channel. you can use this .mif to dynamically reconfigure any of the other transceiver channels in the device if you satisfy the following two requirements for the input reference clocks: the order of the clock inputs must be consistent. for example, assume that a .mif is generated for a transceiver channel in transceiver block 0 and the input clock source is connected to the pll_inclk_rx_cruclk [0] port. when the generated .mif is used for a channel in other transceiver blocks (for example, transceiver block 1), the same clock source needs to be connected to the pll_inclk_rx_cruclk [0] port. figure 2?35 and figure 2?36 show the incorrect and correct order of input reference clocks, respectively. in figure 2?35 , the clocking is incorrect when reusing the .mif because the input reference clock is not connected to the corresponding pll_inclk_rx_cruclk [] ports in the two instances. figure 2?35 shows the incorrect input reference clock connections when reusing a .mif . figure 2?35. incorrect input reference clock connections when reusing a .mif altgx instance 1 hardcopy iv gx de v ice 156.25 mhz 125 mhz transcei v er block 0 transcei v er block 1 altgx instance 2 pll_inclk_rx_cr uclk[0] pll_inclk_rx_cr uclk[1] pll_inclk_rx_cr uclk[0] pll_inclk_rx_cr uclk[1]
chapter 2: hardcopy iv gx dynamic reconfiguration 2?73 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 figure 2?36 shows the correct input reference clock connections when reusing a .mif . 1 you can reuse the .mif generated for a transceiver channel on one side of the device, for a transceiver channel on the other side of device, only if the input reference clock frequencies and order of the pll_inclk_rx_cruclk [] ports in the altgx instances on both sides are identical. in addition to the input reference clock requirements when reusing a .mif , refer to ?the logical_tx_pll_sel and logical_tx_pll_sel_en ports? on page 2?109 for additional ways to reuse a . mif . the logical_channel_address port in .mif-based dynamic reconfiguration modes based on the value you set at the logical_channel_address [8:0] port, the dynamic reconfiguration controller writes the .mif contents into the transceiver channel you specify. this signal is enabled only when the number of channels controlled by the dynamic reconfiguration controller is more than one. because transceiver channel reconfiguration is done on a per-channel basis, you must use this signal and provide the necessary logical channel address to write the .mif words successfully into the channel. for more information about the logical_channel_address port, refer to ?dynamic reconfiguration controller port list? on page 2?11 . 1 in cmu pll reconfiguration mode, use logical_channel_address to specify the transceiver channel that the cmu pll (under reconfiguration) is connected to. figure 2?36. correct input reference clock connections when reusing a .mif hardcopy i v gx de v ice 156.25 mhz 125 mhz transcei v er block 0 transcei v er block 1 altgx instance 1 altgx instance 2 pll_inclk_rx_cr uclk[0] pll_inclk_rx_cr uclk[1] pll_inclk_rx_cr uclk[1] pll_inclk_rx_cr uclk[0]
2?74 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation channel and cmu pll reconfiguration mode you can reconfigure a transceiver channel to a different functional mode and data rate by using this dynamic reconfiguration mode. to reconfigure a channel successfully, select the appropriate options in the altgx megawizard plug-in manager (described in the following sections), and generate a .mif . the altgx_reconfig instance reconfigures the transceiver channel by writing the .mif contents into the channel. 1 channel and cmu pll reconfiguration mode only affects the channel involved in the reconfiguration (the transceiver channel specified by the logical_channel_address port), without affecting the remaining transceiver channels controlled by the dynamic reconfiguration controller. 1 channel and cmu pll reconfiguration mode is applicable to the regular transceiver channels configured in non basic (pma direct) mode only. 1 channel and cmu pll reconfiguration mode is not applicable to the following: regular transceiver channels configured in basic (pma direct) 1 and n configurations cmu channels configured in basic (pma direct) 1 and n configurations regular transceiver channels configured in bonded configurations regular transceiver channels configured in cei configuration channel and cmu pll reconfiguration mode can be classified as follows: data rate reconfiguration functional mode reconfiguration data rate and functional mode reconfiguration data rate reconfiguration you can reconfigure the data rate of the transceiver channel by reconfiguring the cmu pll connected to the transceiver channel. you can reconfigure the data rate of the transceiver channel by selecting another transmitter pll to supply clocks to the transceiver channel. every transmitter channel has one local clock divider. similarly, every receiver channel has one local clock divider. you can reconfigure the data rate of a transceiver channel by reconfiguring these local clock dividers to 1, 2, or 4. when you reconfigure these local clock dividers, ensure that the functional mode of the transceiver channel supports the reconfigured data rate.
chapter 2: hardcopy iv gx dynamic reconfiguration 2?75 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 functional mode reconfiguration you can reconfigure the existing functional mode of the transceiver channel to a totally different functional mode using this feature. the following are the various ways you can reconfigure the existing functional mode: you can switch only between one non-basic (pma direct) configuration to another non-basic (pma direct) configuration you can switch between one protocol configuration (for example, xaui configuration) to another protocol configuration (for example, gige configuration) you can switch between one protocol configuration (for example, serial rapidio configuration) to a basic configuration you can switch between basic configuration to another basic functional mode you cannot dynamically reconfigure the following: you cannot switch from a cei configuration to any other functional mode you cannot switch between basic (pma direct) 1 configuration to basic (pma direct) 1 configuration you cannot switch between basic (pma direct) n configuration to basic (pma direct) n configuration you cannot switch from a bonded mode configuration (for example: pci express [pipe] 4 configuration) to any other functional mode there is no limit to the number of functional modes you can reconfigure the transceiver channel to, if the various clocks involved support the transition. for more information about core clocks, refer to ?core clocking setup? on page 2?79 . 1 in addition to the categories mentioned, you can also choose to reconfigure both the data rate and functional mode of a transceiver channel. 1 for the following sections, assume that the transceiver channel has the receiver and transmitter configuration in the altgx megawizard plug-in manager, unless specified as transmitter only or receiver only . blocks reconfigured in channel and cmu pll reconfiguration mode the blocks that get reconfigured by this dynamic reconfiguration mode are the pcs and pma blocks of a transceiver channel, local divider settings of the transmitter and receiver channel, and the cmu pll.
2?76 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation figure 2?37 shows the functional blocks that you can dynamically reconfigure using this feature. channel reconfiguration supported configurations channel reconfiguration is applicable only to the following non-bonded configurations of a physical transceiver channel: receiver and transmitter configuration transmitter only configuration receiver only configuration independent transmitter and independent receiver combined into the same physical channel in transmitter only configuration, the physical transceiver channel has only one transmitter. the .mif for the transmitter only file has the bits for the transmitter portion only. the receiver only configuration is the same as the transmitter only configuration except it pertains to the receiver. 1 channel reconfiguration from a transmitter only configuration to a receiver only configuration and vice versa is not allowed. figure 2?37. channel and cmu pll reconfiguration in a transceiver block fu ll d u plex transcei v er channel tx cha nnel rx cha nnel refclk0 refclk1 clock m ux clock m ux cmu channel cmu pll0 cmu pll1 logical tx pll select clock m ux local divider digital+analog logic digital+analog logic rx pll blocks that can be reconfigured in channel and cmu pll reconfigu ration mode
chapter 2: hardcopy iv gx dynamic reconfiguration 2?77 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 altgx megawizard plug-in manager setup for channel and cmu pll reconfiguration mode to reconfigure the transceiver channel and cmu pll, set up the altgx megawizard plug-in manager as shown in the following steps. the dynamic reconfiguration controller reconfigures the transceiver channel and the cmu pll with the new information stored in the .mif . 1. select the channel and transmitter pll reconfiguration option in the reconfig screen. 2. if you want to reconfigure the data rate of the transceiver channel by reconfiguring the cmu pll, provide the new data rate you want the cmu pll to run at in the general screen. 3. provide the logical reference index value in the what is the main pll logical reference index? option in the reconfig clks screen. selecting the logical reference index of the cmu pll in figure 2?38 , transceiver channel 1 listens to cmu0 pll of the transceiver block. similarly, transceiver channel 2 listens to cmu1 pll of the transceiver block.
2?78 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation you can direct the altgx_reconfig instance to dynamically reconfigure cmu0 pll by specifying its logical reference index (the identity of a cmu pll). similarly, you can direct the altgx_reconfig instance to dynamically reconfigure cmu1 pll instead by providing the logical reference index of cmu1 pll. the allowed values for the logical reference index are 0 or 1. similarly, the cmu plls in all the transceiver blocks can be assigned a logical reference index value of 0 or 1. 1 the logical reference index of cmu0 pll within a transceiver block is always the complement of the logical reference index of cmu1 pll within the same transceiver block. figure 2?38. logical reference index of cmu plls in a transceiver block fu ll d u plex transcei v er channel 1 tx cha nn el 1 cmu channels full duplex transceiver channel 2 rx pll digital +analog logic digital+analog logic tx channel 2 logical tx pll select rx channel 2 2.5 gbps 2.5 gbps 2.5 gbps local divider clock mux refclk0 refclk1 156.25 mhz 125 mhz clock m ux clock m ux 6.25 gbps cmu0 pll 2.5 gbps cmu1 pll rx cha nn el 1 logical tx pll select clock m ux 6.25 gbps rx pll 6.25 gbps digital+analog logic 6.25 gbps digital+analog logic local divider
chapter 2: hardcopy iv gx dynamic reconfiguration 2?79 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 1 this logical reference index value is stored as logical tx pll, along with the other transceiver channel settings in the .mif . 4. provide the number of input reference clocks available for the cmu pll in the how many input clocks? option in the reconfig clks screen. the maximum number of input reference clocks allowed is 10. for more information about this setting, refer to ?general guidelines for specifying the input reference clocks? on page 2?115 . 5. provide the identification of the input reference clock used by the cmu pll in the what is the selected input clock source for the transmitter pll and receiver pll? option in the reconfig clks screen. 6. set up transceiver and core clocking, which is explained in the following section. transceiver clocking setup you must set up the transceiver clocking options as part of channel reconfiguration for functional mode switch over or data rate transition. transceiver clocking covers all the clock options you need to set up. two cmu plls for data rates and functional modes input reference clocks for transmit and receive core clocking setup the transceiver core clocks are the write and read clocks of the transmit phase compensation fifo and the receive phase compensation fifo, respectively. core clocking is classified as transmitter core clocking and receiver core clocking. table 2?26 explains transmitter core clocking. similarly, table 2?27 explains receiver core clocking. table 2?26. transmitter core clocking (part 1 of 2) transmitter core clocking refers to the clock that is used to write the parallel data from the core fabric into the transmit phase compensation fifo. you can use one of the following clocks to write into the transmit phase compensation fifo: tx_coreclk ?you can use a clock of the same frequency as tx_clkout from the core fabric to provide the write clock to the transmit phase compensation fifo. if you use tx_coreclk , it overrides the tx_clkout options in the altgx megawizard plug-in manager. tx_clkout ?the quartus ii software automatically routes tx_clkout to the core fabric and back into the transmit phase compensation fifo. there are two options available within the tx_clkout option in the reconfig 2 screen, as shown in figure 2?39 . the following are the two tx_clkout options in the reconfig 2 screen of the altgx megawizard plug-in manager (1) : option 1: share a single transmitter clock between transmitters option 2: use the respective channel transmitter core clocks
2?80 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation enable this option if you want tx_clkout of the first channel (channel 0) of the transceiver block to provide the write clock to the transmitter phase compensation fifos of the remaining channels in the transceiver block. this option is typically enabled when all the channels of a transceiver block are of the same functional mode and data rate, and are reconfigured to the identical functional mode and data rate. consider the following scenario: ? four regular transceiver channels configured at 3 gbps and in the same functional mode. ? channel and cmu pll reconfiguration mode is enabled in the altgx_reconfig megawizard plug-in manager. ? you want to reconfigure all four regular transceiver channels to 1.5 gbps and vice versa. option 1 is applicable in this scenario because it saves clock resources. figure 2?40 shows the sharing of channel 0's tx_clkout between all four regular channels of a transceiver block. enable this option if you want the individual transmitter channel tx_clkout signals to provide the write clock to their respective transmit phase compensation fifos. this option is typically enabled when each transceiver channel is reconfigured to a different functional mode using channel reconfiguration. consider the following scenario: ? four regular transceiver channels configured at 3 gbps and different functional modes. ? channel and cmu pll reconfiguration mode is enabled in the altgx_reconfig megawizard plug-in manager. ? you want to reconfigure each of the four regular transceiver channels to different data rates and different functional modes. option 2 is applicable in this scenario because the design requires all four regular transceiver channels to be reconfigured to different data rates and functional modes. figure 2?41 shows how each transmitter channel's tx_clkout signal provides a clock to the transmit phase compensation fifos of the respective transceiver channels. therefore, each channel can be reconfigured to a different functional mode using the channel and cmu pll reconfiguration mode. note to tab l e 2 ?2 6 : (1) the reconfig 2 screen is not available for pma-only channels (channels configured in basic [pma direct] 1 and n modes). table 2?26. transmitter core clocking (part 2 of 2)
chapter 2: hardcopy iv gx dynamic reconfiguration 2?81 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 figure 2?39. two options within the tx_clkout option in the reconfig 2 screen of the altgx megawizard plug-in manager
2?82 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation figure 2?40. option 1 for transmitter core clocking (channel and cmu pll reconfiguration mode) tx0 (3 gbps) tx1 (3 gbps) tx2 (3 gbps) tx3 (3 gbps) rx3 rx2 rx1 rx0 cmu1 pll cmu0 pll asic core transcei v er block tx_clko ut[0] lo w -speed parallel clock generated b y the tx0 local di v ider (tx_clkout[0]) high-speed serial clock generated b y the cmu0 pll
chapter 2: hardcopy iv gx dynamic reconfiguration 2?83 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 figure 2?41. option 2 for transmitter core clocking (channel and cmu pll reconfiguration mode) table 2?27. receiver core clocking (part 1 of 2) receiver core clocking refers to the clock that is used to read the parallel data from the receiver phase compensation fifo into the core fabric. you can use one of the following clocks to read from the receive phase compensation fifo: rx_coreclk ?you can use a clock of the same frequency as rx_clkout from the core fabric to provide the read clock to the receive phase compensation fifo. if you use rx_coreclk , it overrides the rx_clkout options in the altgx megawizard plug-in manager. rx_clkout ?the quartus ii software automatically routes rx_clkout to the core fabric and back into the receive phase compensation fifo. there are three options available within the rx_clkout option in the reconfig 2 screen. the following are the three rx_clkout options in the reconfig 2 screen of the altgx megawizard plug-in manager (1) : option 1: share a single transmitter core clock between receivers option 2: use respective channel transmitter core clocks option 3: use respective channel receiver core clocks tx0 (3 gbps) tx1 (3 gbps) tx2 (3 gbps) tx3 (3 gbps) rx0 rx1 rx2 rx3 cmu1 pll cmu0 pll asic core transcie v er block high-speed serial clock generated b y the cmu0 pll tx_clko ut[0] tx_clko ut[1] tx_clko ut[2] tx_clko ut[3]
2?84 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation enable this option if you want tx_clkout of the first channel (channel 0) of the transceiver block to provide the read clock to the receive phase compensation fifos of the remaining receiver channels in the transceiver block. this option is typically enabled when all the channels of a transceiver block are in a basic or protocol configuration with rate matching enabled and are reconfigured to another basic or protocol configuration with rate matching enabled. consider the following scenario: ? four regular transceiver channels configured to basic 2 gbps functional mode with rate matching enabled. ? channel and cmu pll reconfiguration mode is enabled in the altgx_reconfig megawizard plug-in manager. ? you want to reconfigure all four regular transceiver channels to 3.125 gbps configuration with rate matching enabled. option 1 is applicable in this scenario. figure 2?42 shows the sharing of channel 0?s tx_clkout between all four channels of a transceiver block. enable this option if you want the individual transmitter channel?s tx_clkout signal to provide the read clock to its respective receive phase compensation fifo. this option is typically enabled when all the transceiver channels have rate matching enabled with different data rates and are reconfigured to another basic or protocol functional mode with rate matching enabled. consider the following scenario: ? tx1/rx1: you want to dynamically reconfigure basic 1 gbps configuration with rate matching enabled to basic 2 gbps configuration with rate matching enabled. ? tx3/rx3: you want to dynamically reconfigure basic 4 gbps configuration with rate matching enabled to basic 1 gbps configuration with rate matching enabled. ? tx0/rx0: you want to dynamically reconfigure basic 3.125 gbps configuration with rate matching enabled to 1 gbps configuration with rate matching and vice versa. ? channel and cmu pll reconfiguration mode is enabled in the altgx_reconfig megawizard plug-in manager. option 2 is applicable in this scenario because the design requires the individual transceiver channels to be reconfigured with different data rates to another basic or protocol functional mode with rate matching. therefore, each channel can be reconfigured to another basic or protocol functional mode with rate matching enabled and a different data rate. figure 2?43 shows the respective tx_clkout of each channel clocking the respective channels of a transceiver block. enable this option if you want the individual channel?s rx_clkout signal to provide the read clock to its respective receive phase compensation fifo. this option is typically enabled when the channel is reconfigured from a basic or protocol configuration with or without rate matching to another basic or protocol configuration with or without rate matching. consider the following scenario: ? tx1/rx1: gige configuration to sonet/sdh oc48 configuration. ? tx2/rx2: basic 2.5 gbps configuration with rate matching disabled to basic 1.244 gbps configuration with rate matching disabled. ? channel and cmu pll reconfiguration mode is enabled in the altgx_reconfig megawizard plug-in manager option 3 is applicable in this scenario. figure 2?44 shows the respective rx_clkout of each channel, clocking the respective receiver channels of a transceiver block. note to tab l e 2 ?2 7 : (1) the reconfig 2 screen is not available for pma-only channels (channels configured in basic [pma direct] 1 and n modes). table 2?27. receiver core clocking (part 2 of 2)
chapter 2: hardcopy iv gx dynamic reconfiguration 2?85 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 figure 2?42. receiver core clocking for option 1 high speed serial clock generated b y the cmu0 pll low speed parallel clock generated b y the tx0 local di vider (tx_clko ut[0]) high speed serial clock generated b y the cmu1 pll asic core transcei v er block tx_clko ut[0] tx0 (2 gbps) rx0 tx1 (2 gbps) tx2 (2 gbps) tx3 (2 gbps) rx1 rx2 rx3 cmu1 pll cmu0 pll fo ur regu lar transceiv er channels configured at basic 2g with rate matching and set up to s witch to 3.125 g bps with rate matching
2?86 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation figure 2?43. receiver core clocking for option 2 high speed serial clock generated b y the cmu0 pll high speed serial clock generated b y the cmu1 pll asic core transcei v er block tx_clko ut[0] tx_clko ut[1] tx_clko ut[2] tx_clko ut[3] rx0 rx1 rx2 rx3 tx0 (2 gbps) tx1 (2 gbps) tx2 (2 gbps) tx3 (2 gbps) cmu1 pll cmu0 pll fo ur regu lar transceiv er channels configured at basic 2g with rate matching and set up to s w itch to different functional modes w ith rate matching (and different data rates)
chapter 2: hardcopy iv gx dynamic reconfiguration 2?87 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 figure 2?44. receiver core clocking for option 3 high-speed serial clock generated b y the cmu0 pll high-speed serial clock generated b y the cmu1 pll asic core transcei v er block rx_clko ut[0] rx_clko ut[1] rx_clko ut[2] rx_clko ut[3] rx3 rx2 rx3 rx0 tx0 (2 gbps) tx1 (2 gbps) tx2 (2 gbps) tx3 (2 gbps) cmu1 pll cmu0 pll
2?88 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation figure 2?45. rx_clkout options in the altgx megawizard plug-in manager
chapter 2: hardcopy iv gx dynamic reconfiguration 2?89 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 7. core fabric-transceiver channel interface selection this section describes the altgx megawizard plug-in manager settings related to the core fabric-transceiver channel interface data width when you select and activate channel and cmu pll reconfiguration mode. you need to set up the core fabric-transceiver channel interface data width when channel reconfiguration involves the following: functional mode reconfiguration involving changes in the core fabric-transceiver channel data width functional mode reconfiguration involving enabling and disabling the static pcs blocks of the transceiver channel you can set up the core fabric-transceiver channel interface data width by enabling the channel interface option in the reconfig screen, as shown in figure 2?46 . enable the channel interface option if the reconfiguration of the transceiver channel involves the following changes: the reconfigured channel has a changed core fabric-transceiver channel interface data width the reconfigured channel has changed input control signals and output status signals figure 2?46. channel interface option in the altgx megawizard plug-in manager
2?90 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation there are two new signals available when you enable this option: tx_datainfull ?the width of this input signal depends on the number of channels you set up in the general screen. it is 44 bits wide per channel. this signal is available only for transmitter only and receiver and transmitter configurations. this port replaces the existing tx_datain port. rx_dataoutfull ?the width of this output signal depends on the number of channels you set up in the general screen. it is 64 bits wide per channel. this signal is available only for receiver only and receiver and transmitter configurations. this port replaces the existing rx_dataout port. 1 in addition to these two new ports, you can select the necessary control and status signals for the reconfigured channel in the reconfig 2 screen. f for more information about control and status signals, refer to the transceiver port list in the hardcopy iv gx transceiver architecture chapter in volume 3 of the hardcopy iv device handbook . these control and status signals are not applicable in basic (pma direct) functional mode. the following signals are not available when you enable this option. core fabric-receiver interface: rx_dataout rx_syncstatus rx_patterndetect rx_a1a2sizeout rx_ctrldetect rx_errdetect rx_disperr core fabric-transmitter interface: tx_datain tx_ctrlenable tx_forcedisp tx_dispval the quartus ii software has legal checks for the connectivity of tx_datainfull and rx_dataoutfull and the various control and status signals you enable in the reconfig 2 screen. for example, the quartus ii software allows you to select and connect the pipestatus and powerdn signals. it assumes that you are planning to switch to and from pci express (pipe) functional mode. table 2?28 describes the tx_datainfull[43:0] core fabric-transceiver channel interface signals.
chapter 2: hardcopy iv gx dynamic reconfiguration 2?91 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 table 2?28. tx_datainfull[43:0] core fabric-transceiver channel interface signal descriptions (part 1 of 3) core fabric-transceiver channel interface description transmit signal description (based on hardcopy iv gx supported core fabric-transceiver channel interface widths) 8-bit core fabric-transceiver channel interface tx_datainfull[7:0] : 8-bit data ( tx_datain ) the following signals are used only in 8b/10b modes: tx_datainfull[8] : control bit ( tx_ctrlenable ) tx_datainfull[9] : force disparity enable for tx_datainfull[7:0] (non pipe mode). transmitter force disparity compliance (pipe) ( tx_forcedisp ) in all modes except pipe. for pipe mode, ( tx_forcedispcompliance ) is used. tx_datainfull[10] : forced disparity value for tx_datainfull[7:0] ( tx_dispval ) 10-bit core fabric-transceiver channel interface tx_datainfull[9:0] : 10-bit data ( tx_datain ) 16-bit core fabric-transceiver channel interface with pcs-pma set to 16/20 bits two 8-bit data ( tx_datain ) tx_datainfull[7:0] - tx_datain (lsbyte) and tx_datainfull[18:11] - tx_datain (msbyte) the following signals are used only in 8b/10b modes: tx_datainfull[8] - tx_ctrlenable (lsb) and tx_datainfull[19] - tx_ctrlenable (msb) force disparity enable tx_datainfull[9] - tx_forcedisp (lsb) and tx_datainfull[20] - tx_forcedisp (msb) force disparity value tx_datainfull[10] - tx_dispval (lsb) and tx_datainfull[21] - tx_dispval (msb)
2?92 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation 16-bit core fabric-transceiver channel interface with pcs-pma set to 8/10 bits two 8-bit data ( tx_datain ) tx_datainfull[7:0] - tx_datain (lsbyte) and tx_datainfull[29:22] - tx_datain (msbyte) the following signals are used only in 8b/10b modes: two c on tro l bit s ( tx_ctrlenable ) tx_datainfull [8] - tx_ctrlenable (lsb) and tx_datainfull [30] - tx_ctrlenable (msb) force disparity enable for non-pipe: tx_datainfull[9] - tx_forcedisp (lsb) and tx_datainfull[31] - tx_forcedisp (msb) for pipe: tx_datainfull[9] - tx_forcedispcompliance (lsb) and tx_datainfull[31] - tx_forcedispcompliance (msb) force disparity value tx_datainfull[10] - tx_dispval (lsb) and tx_datainfull[32] - tx_dispval (msb) 20-bit core fabric-transceiver channel interface with pcs-pma set to 20 bits two 1 0-b it data ( tx_datain ) tx_datainfull[9:0] - tx_datain (lsbyte) and tx_datainfull[20:11] - tx_datain (msbyte) 20-bit core fabric-transceiver channel interface with pcs-pma set to 10 bits two 1 0-b it data ( tx_datain ) tx_datainfull[9:0] - tx_datain (lsbyte) and tx_datainfull[31:22] - tx_datain (msbyte) table 2?28. tx_datainfull[43:0] core fabric-transceiver channel interface signal descriptions (part 2 of 3) core fabric-transceiver channel interface description transmit signal description (based on hardcopy iv gx supported core fabric-transceiver channel interface widths)
chapter 2: hardcopy iv gx dynamic reconfiguration 2?93 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 32-bit core fabric-transceiver channel interface with pcs-pma set to 16/20 bits four 8-bit data ( tx_datain ) tx_datainfull[7:0] - tx_datain (lsbyte) and tx_datainfull[18:11] tx_datainfull[29:22] tx_datainfull[40:33] - tx_datain (msbyte) the following signals are used only in 8b/10b modes: four control bits ( tx_ctrlenable ) tx_datainfull[8] - tx_ctrlenable (lsb) and tx_datainfull[19] tx_datainfull[30] tx_datainfull[41] - tx_ctrlenable (msb) force disparity enable ( tx_forcedisp ) tx_datainfull [9]- tx_forcedisp (lsb) and tx_datainfull[20] tx_datainfull[31] tx_datainfull[42] - tx_forcedisp (msb) force disparity value ( tx_dispval ) tx_datainfull[10] - tx_dispval (lsb) and tx_datainfull[21] tx_datainfull[32] tx_datainfull[43] - tx_dispval (msb) 40-bit core fabric-transceiver channel interface with pcs-pma set to 20 bits four 10-bit data ( tx_datain ) tx_datainfull[9:0] - tx_datain (lsbyte) and tx_datainfull[20:11] tx_datainfull[31:22] tx_datainfull[42:33] - tx_datain (msbyte) table 2?28. tx_datainfull[43:0] core fabric-transceiver channel interface signal descriptions (part 3 of 3) core fabric-transceiver channel interface description transmit signal description (based on hardcopy iv gx supported core fabric-transceiver channel interface widths)
2?94 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation table 2?29. rx_dataoutfull[63:0] core fabric-transceiver channel interface signal descriptions (part 1 of 7) core fabric-transceiver channel interface description receive signal description (based on hardcopy iv gx supported core fabric-transceiver channel interface widths) 8-bit core fabric-transceiver channel interface the following signals are used in 8-bit 8b/10b modes: rx_dataoutfull[7:0] : 8-bit decoded data ( rx_dataout ) rx_dataoutfull[8] : control bit ( rx_ctrldetect ) rx_dataoutfull[9] : code violation status signal. it indicates error detected in rx_dataoutfull[7:0] , which is replaced by invalid code-group (invalid or running disp.error) in gige mode. in pci express, when code violation occurs, the edb character is placed on the erroneous data byte (= k30.7) ( rx_errdetect ) rx_dataoutfull [10]: rx_syncstatus rx_dataoutfull[11] : disparity error status signal. it indicates disparity error detected in rx_dataoutfull[7:0] ( rx_disperr ) rx_dataoutfull[12] : pattern detect status signal ( rx_patterndetect ) rx_dataoutfull[13] : rate match fifo deletion status indicator ( rx_rmfifodatadeleted ) in non-pipe/pcie modes. rx_dataoutfull[14] : rate match fifo insertion status indicator ( rx_rmfifodatainserted ) in non-pipe/pcie modes. rx_dataoutfull[14:13] : pipe/pci-e mode: 2'b00: data ok; 2'b01: 1 skp deletion; 2'b10: elastic buffer underflow if data is 0xfe, else 1 skp insertion; 2b11: elastic buffer overflow ( rx_pipestatus ) rx_dataoutfull[15] : 8b/10b running disparity indicator ( rx_runningdisp ) the following signals are used in 8-bit sonet/sdh mode: rx_dataoutfull[7:0] : 8-bit un-encoded data ( rx_dataout ) rx_dataoutfull[8] : rx_a1a2sizeout rx_dataoutfull[10] : rx_syncstatus rx_dataoutfull[11] : reserved rx_dataoutfull[12] : rx_patterndetect 10-bit core fabric-transceiver channel interface rx_dataoutfull[9:0] : 10-bit un-encoded data ( rx_dataout ) rx_dataoutfull[10] : rx_syncstatus rx_dataoutfull[11] : 8b/10b disparity error indicator ( rx_disperr ) rx_dataoutfull[12] : rx_patterndetect rx_dataoutfull[13] : rate match fifo deletion status indicator ( rx_rmfifodatadeleted ) in non pipe/pcie modes rx_dataoutfull[14] : rate match fifo insertion status indicator (r x_rmfifodatainserted) in non pipe/pcie modes rx_dataoutfull[15] : 8b/10b running disparity indicator ( rx_runningdisp )
chapter 2: hardcopy iv gx dynamic reconfiguration 2?95 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 16-bit core fabric-transceiver channel interface with pcs-pma set to 16/20 bits two 8-bit unencoded data ( rx_dataout ) rx_dataoutfull[7:0] - rx_dataout (lsbyte) and rx_dataoutfull[23:16] - rx_dataout (msbyte) the following signals are used in 16-bit 8b/10b modes: two control bits rx_dataoutfull[8] - rx_ctrldetect (lsb) and rx_dataoutfull[24] - rx_ctrldetect (msb) two receiver error detect bits rx_dataoutfull[9] - rx_errdetect (lsb) and rx_dataoutfull[25] - rx_errdetect (msb) two receiver sync status bits rx_dataoutfull [10] - rx_syncstatus (lsb) and rx_dataoutfull[26] - rx_syncstatus (msb) two receiver disparity error bits rx_dataoutfull [11] - rx_disperr (lsb) and rx_dataoutfull[27] - rx_disperr (msb) two receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) and rx_dataoutfull[28] - rx_patterndetect (msb) rx_dataoutfull[13] and rx_dataoutfull [45]: rate match fifo deletion status indicator ( rx_rmfifodatadeleted ) in non-pipe/pcie modes rx_dataoutfull[14] and rx_dataoutfull [46]: rate match fifo insertion status indicator ( rx_rmfifodatainserted ) in non-pipe/pcie modes two 2-bit pipe status bits rx_dataoutfull[14:13] - rx_pipestatus (lsb) and rx_dataoutfull[30:29] - rx_pipestatus (msb) pipe/pci-e mode: 2'b00: data ok 2'b01: 1 skp deletion 2'b10: elastic buffer underflow if data is 8?hfe, else 1 skp insertion 2'b11: elastic buffer overflow rx_dataoutfull[15] and rx_dataoutfull[47] : 8b/10b running disparity indicator ( rx_runningdisp ) 16-bit core fabric-transceiver channel interface with pcs-pma set to 8/10 bits two 8-bit data rx_dataoutfull[7:0] - rx_dataout (lsbyte) and rx_dataoutfull[39:32] - rx_dataout (msbyte) table 2?29. rx_dataoutfull[63:0] core fabric-transceiver channel interface signal descriptions (part 2 of 7) core fabric-transceiver channel interface de scription receive signal description (based on hardcopy iv gx supported core fabric-transceiver channel interface widths)
2?96 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation 16-bit core fabric-transceiver channel interface with pcs-pma set to 8/10 bits (continued) the following signals are used in 16-bit 8b/10b mode: two control bits rx_dataoutfull[8] - rx_ctrldetect (lsb) and rx_dataoutfull[40] - rx_ctrldetect (msb) two receiver error detect bits rx_dataoutfull[9] - rx_errdetect (lsb) and rx_dataoutfull[41] - rx_errdetect (msb) two receiver sync status bits rx_dataoutfull[10] - rx_syncstatus (lsb) and rx_dataoutfull[42] - rx_syncstatus (msb) two receiver disparity error bits rx_dataoutfull[11] - rx_disperr (lsb) and rx_dataoutfull[43] - rx_disperr (msb) two receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) and rx_dataoutfull[44] - rx_patterndetect (msb) rx_dataoutfull[13] and rx_dataoutfull[45] : rate match fifo deletion status indicator ( rx_rmfifodatadeleted ) in non-pipe/pcie modes rx_dataoutfull[14] and rx_dataoutfull[46] : rate match fifo insertion status indicator ( rx_rmfifodatainserted ) in non-pipe/pcie modes two 2-bit pipe status bits rx_dataoutfull[14:13] - rx_pipestatus (lsb) and rx_dataoutfull[46:45] - rx_pipestatus (msb) pipe/pci-e mode: 2'b00: data ok 2'b01: 1 skp deletion 2'b10: elastic buffer underflow if data is 8?hfe, else 1 skp insertion 2'b11: elastic buffer overflow ( rx_pipestatus ) rx_dataoutfull [15] and rx_dataoutfull[47] : 8b/10b running disparity indicator ( rx_runningdisp ) the following signals are used in 16-bit sonet/sdh mode: two 8-bit data rx_dataoutfull[7:0] - rx_dataout (lsbyte) and rx_dataoutfull[39:32] - rx_dataout (msbyte) two receiver alignment pattern length bits rx_dataoutfull[8] - rx_a1a2sizeout (lsb) and rx_dataoutfull[40] - rx_a1a2sizeout (msb) table 2?29. rx_dataoutfull[63:0] core fabric-transceiver channel interface signal descriptions (part 3 of 7) core fabric-transceiver channel interface description r eceive signal description (based on hardcopy iv gx supported core fabric-transceiver channel interface widths)
chapter 2: hardcopy iv gx dynamic reconfiguration 2?97 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 16-bit core fabric-transceiver channel interface with pcs-pma set to 8/10 bits (continued) two receiver sync status bits rx_dataoutfull[10] - rx_syncstatus (lsb) and rx_dataoutfull[42] - rx_syncstatus (msb) two receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) and rx_dataoutfull[44] - rx_patterndetect (msb) 20-bit core fabric-transceiver channel interface with pcs-pma set to 20 bits two 10-bit data ( rx_dataout ) rx_dataoutfull[9:0] - rx_dataout (lsbyte) and rx_dataoutfull[25:16] - rx_dataout (msbyte) wo receiver sync status bits rx_dataoutfull[10] - rx_syncstatus (lsb) and rx_dataoutfull[26] - rx_syncstatus (msb) rx_dataoutfull[11] and rx_dataoutfull [27]: 8b/10b disparity error indicator ( rx_disperr ) two receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) and rx_dataoutfull[28] - rx_patterndetect (msb) rx_dataoutfull[13] and rx_dataoutfull[29] : rate match fifo deletion status indicator ( rx_rmfifodatadeleted ) in non-pipe/pcie modes rx_dataoutfull[14] and rx_dataoutfull[30] : rate match fifo insertion status indicator ( rx_rmfifodatainserted ) in non-pipe/pcie modes rx_dataoutfull[15] and rx_dataoutfull[31] : 8b/10b running disparity indicator ( rx_runningdisp ) table 2?29. rx_dataoutfull[63:0] core fabric-transceiver channel interface signal descriptions (part 4 of 7) core fabric-transceiver channel interface description receive signal description (based on hardcopy iv gx supported core fabric-transceiver channel interface widths)
2?98 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation 20-bit core fabric-transceiver channel interface with pcs-pma set to 10 bits two 10-bit data rx_dataoutfull[9:0] - rx_dataout (lsbyte) and rx_dataoutfull[41:32] - rx_dataout (msbyte) two receiver sync status bits rx_dataoutfull[10] - rx_syncstatus (lsb) and rx_dataoutfull[42] - rx_syncstatus (msb) rx_dataoutfull[11] and rx_dataoutfull[43] : 8b/10b disparity error indicator ( rx_disperr ) two receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) and rx_dataoutfull[44] - rx_patterndetect (msb) rx_dataoutfull[13] and rx_dataoutfull[45] : rate match fifo deletion status indicator ( rx_rmfifodatadeleted ) in non-pipe/pcie modes rx_dataoutfull[14] and rx_dataoutfull[46] : rate match fifo insertion status indicator ( rx_rmfifodatainserted ) in non-pipe/pcie modes rx_dataoutfull[15] and rx_dataoutfull[47] : 8b/10b running disparity indicator ( rx_runningdisp ) table 2?29. rx_dataoutfull[63:0] core fabric-transceiver channel interface signal descriptions (part 5 of 7) core fabric-transceiver channel interface description receive signal description (based on hardcopy iv gx supported core fabric-transceiver channel interface widths)
chapter 2: hardcopy iv gx dynamic reconfiguration 2?99 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 32-bit mode four 8-bit un-encoded data ( rx_dataout ) rx_dataoutfull[7:0] - rx_dataout (lsbyte) rx_dataoutfull[23:16] rx_dataoutfull[39:32] rx_dataoutfull[55:48] - rx_dataout (msbyte) the following signals are used in 32-bit 8b/10b mode: four control data bits ( rx_dataout ) rx_dataoutfull[8] - rx_ctrldetect (lsb) rx_dataoutfull[24] rx_dataoutfull[40] rx_dataoutfull[56] - rx_ctrldetect (msb) four receiver error detect bits rx_dataoutfull[9] - rx_errdetect (lsb) rx_dataoutfull[25] rx_dataoutfull[41] rx_dataoutfull[57] - rx_errdetect (msb) four receiver pattern detect bits rx_dataoutfull [10]- rx_syncstatus (lsb) and rx_dataoutfull[26] rx_dataoutfull[42] rx_dataoutfull[58] - rx_syncstatus (msb) four receiver disparity error bits rx_dataoutfull[11] - rx_disperr (lsb) rx_dataoutfull[27] rx_dataoutfull[43] rx_dataoutfull[59] - rx_disperr (msb) four receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) rx_dataoutfull[28] rx_dataoutfull[44] rx_dataoutfull[60] - rx_patterndetect (msb) rx_dataoutfull[13] , rx_dataoutfull[29] , rx_dataoutfull[45] and rx_dataoutfull[61] : rate match fifo deletion status indicator ( rx_rmfifodatadeleted ) in non-pipe/pcie modes rx_dataoutfull[14] , rx_dataoutfull[30] , rx_dataoutfull[46] , and rx_dataoutfull[62] : rate match fifo insertion status indicator ( rx_rmfifodatainserted ) in non-pipe/pcie modes table 2?29. rx_dataoutfull[63:0] core fabric-transceiver channel interface signal descriptions (part 6 of 7) core fabric-transceiver channel interface description receive signal description (based on hardcopy iv gx supported core fabric-transceiver channel interface widths)
2?100 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation 32-bit mode (continued) rx_dataoutfull[15] , rx_dataoutfull[31] , rx_dataoutfull[47] , and rx_dataoutfull[63] : 8b/10b running disparity indicator ( rx_runningdisp ) the following signals are used in 32-bit sonet/sdh scrambled backplane mode: four control data bits ( rx_dataout ) rx_dataoutfull[7:0] - rx_dataout (lsbyte) rx_dataoutfull[23:16] rx_dataoutfull[39:32] rx_dataoutfull[55:48] - rx_dataout (msbyte) rx_dataoutfull[8] , rx_dataoutfull[24], rx_dataoutfull[40] , and rx_dataoutfull[56] : four rx_a1a2sizeout four receiver sync status bits rx_dataoutfull[10] - rx_syncstatus (lsb) rx_dataoutfull[26] rx_dataoutfull[42] rx_dataoutfull[58] - rx_syncstatus (msb) four receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) rx_dataoutfull[28] rx_dataoutfull[44] rx_dataoutfull[60] - rx_patterndetect (msb) 40-bit mode four 10-bit control data bits ( rx_dataout ) rx_dataoutfull[9:0] - rx_dataout (lsbyte) r x_dataoutfull[25:16] rx_dataoutfull[41:32] rx_dataoutfull[57:48] - rx_dataout (msbyte) four receiver sync status bits rx_dataoutfull[10] - rx_syncstatus (lsb) rx_dataoutfull[26] rx_dataoutfull[42] rx_dataoutfull[58] - rx_syncstatus (msb) four receiver pattern detect bits rx_dataoutfull[12] - rx_patterndetect (lsb) rx_dataoutfull[28] rx_dataoutfull[44] rx_dataoutfull[60] - rx_patterndetect (msb) table 2?29. rx_dataoutfull[63:0] core fabric-transceiver channel interface signal descriptions (part 7 of 7) core fabric-transceiver channel interface description receive signal description (based on hardcopy iv gx supported core fabric-transceiver channel interface widths)
chapter 2: hardcopy iv gx dynamic reconfiguration 2?101 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 altgx_reconfig megawizard plug-in manager setup for channel and cmu pll reconfiguration mode use the following steps to setup channel and cmu pll reconfiguration mode in the altgx_reconfig megawizard plug-in manager: 1. set the what is the number of channels controlled by the reconfig controller? option in the reconfiguration settings screen. for more information, refer to ?total number of channels controlled by the altgx_reconfig instance? on page 2?35 . 2. select the c hannel and tx pll select/reconfig option in the reconfiguration settings screen, as shown in figure 2?47 . the following control signals are always available when you enable the channel and tx pll select/reconfig option: channel_reconfig_done ?the dynamic reconfiguration controller asserts the channel_reconfig_done signal to indicate that all the words of the .mif have been written into the transceiver. reconfig_address_out[5:0] ?this output signal provides the address value that you can use to read the appropriate word from the .mif . use the value at this port in combination with the reconfig_address_en signal to decide when to write the next word. the following options are optional and available for selection in the channel and tx pll reconfiguration screen: reset_reconfig_address ?use this signal to reset the reconfig_address_out[5:0] value to 0. reconfig_address_en ?the altgx_reconfig instance asserts this output signal to indicate the change in value on the reconfig_address_out[5:0] port. this signal only gets asserted after the dynamic reconfiguration controller completes writing a 16-bit word of the .mif . logical_tx_pll_sel and logical_tx_pll_sel_en ?for more information about these two ports, refer to ?the logical_tx_pll_sel and logical_tx_pll_sel_en ports? on page 2?109 . through the rx_tx_duplex_sel[1:0] signal, the dynamic reconfiguration controller has information about whether the targeted transceiver channel is an receiver only , transceiver only , or receiver and transmitter configuration. for more information about this signal, refer to ?dynamic reconfiguration controller port list? on page 2?11 . the .mif also contains information about the transceiver channel configuration. the altgx_reconfig megawizard plug-in manager asserts the error signal if there is a mismatch between the rx_tx_duplex_sel [1:0] signal and the .mif contents. channel and cmu pll reconfiguration operation in channel reconfiguration, only a write transaction can occur; no read transactions are allowed. 1. set the reconfig_mode_sel[2:0] control signal to 3?b101 . when you use this feature, the dynamic reconfiguration controller requires that you provide the 16-bit words through the .mif on every write transaction.
2?102 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation 2. set the rx_tx_duplex_sel [1:0] port to enable the transmitter portion, receiver portion, or receiver and transmitter portion for reconfiguration. 3. set the logical_channel_address port to specify the logical channel address of the transceiver channel. 4. ensure the busy signal is low and assert the write_all signal for one reconfig_clk clock cycle. 5. figure 2?47 shows a .mif write transaction when using channel and cmu pll reconfiguration mode. channel reconfiguration with tx pll select mode this section describes the channel reconfiguration with tx pll select mode. you can reconfigure the data rate of a transceiver channel by switching between the two cmu plls present in a transceiver block and reconfiguring the receiver plls. the two cmu plls can be set to different base rates. you can choose one of the cmu plls based on the data rate you want the channel to run at. you can use the channel reconfiguration with tx pll select mode along with the cmu pll reconfiguration mode. you can first reconfigure the second pll to the desired data rate using cmu pll reconfiguration mode. then use channel reconfiguration with tx pll select mode to reconfigure the transceiver channel to listen to the second pll. figure 2?47. .mif write transaction in channel and cmu pll reconfiguration mode notes to figure 2?47 : (1) the waveform assumes that the altgx_reconfig controls two channels. therefore, the logical_channel_address signal is 2 bits wide. the logical_channel_address port is set to 2?b01 to reconfigure the second transceiver channel. (2) the rx_tx_duplex_sel[1:0] port is set to 2?b00 to match the receiver and transmitter configuration of the specified transceiver channel. (3) this waveform assumes that the transceiver channel is configured in basic mode with the receiver and transmitter configurati on. therefore, the .mif size is 54. addr0 addr1 1 st 16-bits don?t care 2 nd 16-bits addr0 addr37 55 th 16-bits don?t care 3?b101 2?b00 2?b01 reconfig_mode_sel[1:0] logical_channel_address[1:0] (1) rx_tx_du plex_sel[1:0] (2) reconfig_clk w rite_all bu sy reconfig_address_out[5:0] reconfig_address_en reconfig_data[15:0] (3) channel_reconfig_done
chapter 2: hardcopy iv gx dynamic reconfiguration 2?103 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 blocks reconfigured in the channel reconfiguration with tx pll select mode the block that gets reconfigured in this mode is the multiplexer, which selects the output of one of the cmu plls and forwards it to the transceiver channel. figure 2?48 shows the multiplexer that you can dynamically reconfigure using the channel reconfiguration with tx pll select feature. altgx megawizard plug-in manager setup for channel reconfiguration with tx pll select mode to reconfigure the transceiver channel by selecting an alternate transmitter pll instead of the existing cmu pll, you must set up the altgx megawizard plug-in manager as shown in the following sections. the dynamic reconfiguration controller reconfigures the multiplexer, selecting between the outputs of the two cmu plls with the new information stored in the .mif . in addition to the seven settings explained in ?altgx megawizard plug-in manager setup for channel and cmu pll reconfiguration mode? on page 2?77 , you must also set up the following design aspect: main pll and alternate pll to reconfigure the cmu pll during run time, you need the flexibility to select one of the two cmu plls. figure 2?48. channel reconfiguration with tx pll select in a transceiver block fu ll d u plex transcei v er channel tx cha nnel rx cha nnel cmu channels refclk0 refclk1 clock m ux clock m ux cmu0 pll cmu1 pll logical tx pll select clock m ux local divider rx pll digital+analog logic digital+analog logic blocks that can be reconfigured in channel reconfigu ration w ith tx pll select mode
2?104 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation consider that the transceiver channel is listening to cmu0 pll and that you want to reconfigure cmu0 pll, as shown in figure 2?49 . you can select cmu0 pll by specifying its identity in the altgx megawizard plug-in manager. this identification is referred to as the logical tx pll value. this value provides a logical identification to cmu0 pll and associates it with a transceiver channel without requiring the knowledge of its physical location. in the altgx megawizard plug-in manager, the transmitter pll configuration set in the general screen is called the main pll. when you provide the main pll with a logical tx pll value, for example 1, the alternate pll automatically takes the complement value 0. the logical tx pll value for the main pll is stored along with the other transceiver channel information in the generated .mif . 1 you can reuse the .mif generated for one cmu pll to reconfigure the other cmu pll in the same or other transceiver blocks. provide the logical tx pll value for the main pll in the what is the main pll logical reference index? option in the reconfig clks screen. figure 2?49. reconfiguring the cmu0 pll fu ll d u plex transcei v er channel tx cha nnel rx cha nnel local divider acti v e connections main pll logical_tx_pll value = 1 (provided by the user in the altgx megawizard plug-in manager) alternate pll logical_tx_pll value = 0 (automatically set by the altgx megawizard plug-in manager) 1 0 un u sed connections cmu channels refclk0 refclk1 156.25 mhz 125 mhz clock m ux clock m ux 6.25 gbps cmu0 pll 2.5 gbps cmu1 pll logical tx pll select clock m ux 6.25 gbps rx pll 6.25 gbps digital+analog logic 6.25 gbps digital+analog logic
chapter 2: hardcopy iv gx dynamic reconfiguration 2?105 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 cmu pll reconfiguration mode is also useful when used in combination with the dynamic reconfiguration mode: channel reconfiguration with cmu pll select. consider that you have one transceiver channel listening to one cmu pll of the transceiver block. you want to reconfigure the transceiver channel to a different data rate. you can first use cmu pll reconfiguration mode (set reconfig_mode_sel[2:0] to 3?b100 ) and reconfigure the second unused cmu pll of the transceiver block to the desired data rate. for more information, refer to ?cmu pll reconfiguration operation? on page 2?108 . you can then use channel reconfiguration with cmu pll select mode (set reconfig_mode_sel[2:0] to 3?b110 ) and reconfigure the transceiver channel to listen to the second reconfigured cmu pll. for more information, refer to ?channel reconfiguration with tx pll select: operation? on page 2?106 . 1 the main pll corresponds to the cmu pll configuration set in the general screen of the altgx megawizard plug-in manager. the alternate pll corresponds to the cmu pll configuration set in the reconfig alt pll screen. altgx_reconfig megawizard plug-in manager setup for channel reconfiguration with tx pll select mode the following sections describe the tx pll selection operation in the altgx megawizard plug-in manager. in addition to the first six settings listed in ?altgx_reconfig megawizard plug-in manager setup for channel and cmu pll reconfiguration mode? on page 2?101 , you must set up the following input ports that are available for selection in the channel and tx pll reconfiguration screen: 1. logical_tx_pll_sel and logical_tx_pll_sel_en ?for more information about these two ports, refer to ?the logical_tx_pll_sel and logical_tx_pll_sel_en ports? on page 2?109 . the following input port is available for selection in the error checks/data rate switch screen: 2. rx_tx_duplex_sel[1:0] ?this signal informs the dynamic reconfiguration controller if the targeted transceiver channel configuration is receiver only , transmitter only , or receiver and transmitter . the . mif also contains information about the transceiver channel configuration. the altgx_reconfig megawizard plug-in manager asserts the error signal if there is a mismatch between the rx_tx_duplex_sel [1:0] signal and the .mif contents. for more information, refer to ?dynamic reconfiguration controller port list? on page 2?11 .
2?106 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation channel reconfiguration with tx pll select: operation in channel reconfiguration, only a write transaction can occur; no read transactions are allowed. set the reconfig_mode_sel[2:0] control signal to 3?b001 to use the channel reconfiguration feature. when you use this feature, the dynamic reconfiguration controller requires that you provide a 16-bit word ( reconfig_data[15:0] ) on every write transaction using the write_all signal. this 16-bit word is part of a .mif that is generated by the quartus ii software when an altgx instance is compiled. set the rx_tx_duplex_sel [1:0] port to enable the transmitter, receiver, or receiver and transmitter portion for reconfiguration. set the logical_channel_address port to specify the logical channel address of the transceiver channel. ensure the busy signal is low and assert the write_all signal for one reconfig_clk clock cycle. figure 2?47 depicts a .mif write transaction when dynamically reconfiguring a transceiver channel. the .mif write transaction in channel reconfiguration with tx pll select mode remains the same, except for the value you must set at reconfig_mode_sel[2:0] and the differences in the .mif words utilized. set reconfig_mode_sel[2:0] to 3'b001 for channel reconfiguration with tx pll select mode. cmu pll reconfiguration mode you can use this mode to reconfigure only the cmu pll without affecting the remaining blocks of the transceiver channel. when you reconfigure the cmu pll of a transceiver block to run at a different data rate, all the transceiver channels listening to this cmu pll also get reconfigured to the new data rate. this reconfiguration mode is a .mif -based approach. 1 cmu pll reconfiguration mode is applicable only to regular transceiver channels configured in non-basic (pma direct) modes. 1 cmu pll reconfiguration mode is not applicable to bonded, basic (pma direct) 1, basic (pma direct) n, and cei configurations. 1 the logical_channel_address port is not applicable in cmu pll reconfiguration mode, even though it is available as an input. tx pll powerdown during cmu pll reconfiguration mode, the dynamic reconfiguration controller automatically powers down the selected cmu pll until it completes reconfiguration. the altgx_reconfig instance does not provide any external ports to control the cmu pll power down. when you reconfigure the cmu pll, the pll_locked signal goes low. therefore, after reconfiguring the transceiver, wait for the pll_locked signal from the altgx instance before continuing normal operation. the dynamic reconfiguration controller powers down only the selected cmu pll. the other cmu pll is not affected.
chapter 2: hardcopy iv gx dynamic reconfiguration 2?107 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 blocks reconfigured in cmu pll reconfiguration mode each transceiver block has two cmu plls?cmu0 pll and cmu1 pll.you can reconfigure each of these cmu plls to a different data rate in this dynamic reconfiguration mode. figure 2?50 shows a conceptual view of both cmu plls in a transceiver block. altgx megawizard plug-in manager setup for cmu pll reconfiguration mode when you want to reconfigure the cmu pll to another data rate, enable .mif generation and set up the altgx megawizard plug-in manager as described in the following steps. the dynamic reconfiguration controller reconfigures the cmu pll with the new information stored in the .mif . 1. select the channel and transmitter pll reconfiguration option in the reconfig screen. 2. provide the new data rate you want the cmu pll to run at in the general screen. 3. provide the logical reference index value in the what is the main pll logical reference index? option in the reconfig clks screen. for more information, refer to ?selecting the logical reference index of the cmu pll? on page 2?77 . figure 2?50. cmu plls in a transceiver block f u ll d u plex transcei v er channel rx pll tx cha nnel rx cha nnel cmu channels refclk0 refclk1 clock m ux clock m ux cmu0 pll cmu1 pll logical tx pll select local divider digital+analog logic digital+analog logic clock m ux blocks that can be reconfigured in cmu pll reconfigu ration mode
2?108 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation 1 the logical reference index of cmu0 pll within a transceiver block is always the complement of the logical reference index of cmu1 pll. this logical reference index value is stored as logical tx pll, along with the other transceiver channel settings in the .mif . 1 you can reuse the .mif generated for one cmu pll to reconfigure the other cmu pll in the same or in other transceiver blocks. altgx_reconfig megawizard plug-in manager setup for cmu pll reconfiguration mode the settings available for cmu pll reconfiguration mode are listed below. in addition to the first six settings listed in ?altgx_reconfig megawizard plug-in manager setup for channel and cmu pll reconfiguration mode? on page 2?101 , you must set up the following input ports that are available for selection in the channel and tx pll reconfiguration screen: the following input port is available for selection in the error checks/data rate switch screen: 1. logical_tx_pll_sel and logical_tx_pll_sel_en ?for more information about these two ports, refer to ?the logical_tx_pll_sel and logical_tx_pll_sel_en ports? on page 2?109 . 2. rx_tx_duplex_sel[1:0] ?this signal informs the dynamic reconfiguration controller if the targeted transceiver channel configuration is receiver only , transmitter only , or receiver and transmitter . the .mif also contains information about the transceiver channel configuration. the altgx_reconfig megawizard plug-in manager asserts the error signal if there is a mismatch between the rx_tx_duplex_sel[1:0] signal and the .mif contents. for more information, refer to ?dynamic reconfiguration controller port list? on page 2?11 . cmu pll reconfiguration operation 1. set the reconfig_mode_sel[2:0] signal to 3?b100 to activate this mode. 2. set the logical_channel_address port to the logical channel address of the transceiver channel connected to the cmu pll. 3. ensure that the busy signal is low. 4. initiate a write transaction by asserting the write_all signal for one reconfig_clk cycle to write the first 16-bit word of the .mif . similarly, initiate a write transaction to write all the words of the .mif . you can use the reconfig_address_out_en port to determine when to initiate the next write transaction. the dynamic reconfiguration controller asserts the busy signal for every write transaction initiated by you. the busy signal remains asserted until the complete 16-bit word has been written. the dynamic reconfiguration controller automatically increments the values on the reconfig_address_out[5:0] port. during reconfiguration, the dynamic reconfiguration controller powers down the cmu pll until new values are written. the dynamic reconfiguration controller asserts the channel_reconfig_done signal to indicate that the cmu pll reconfiguration is complete.
chapter 2: hardcopy iv gx dynamic reconfiguration 2?109 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 figure 2?51 depicts a .mif write transaction in cmu pll reconfiguration mode. the logical_tx_pll_sel and logical_tx_pll_sel_en ports this section describes when to enable the logical_tx_pll_sel and logical_tx_pll_sel_en ports and how to use them in the following dynamic reconfiguration modes: channel and cmu pll reconfiguration mode channel reconfiguration with tx pll select mode cmu pll reconfiguration mode these are optional input ports to the altgx_reconfig instance. the logical_tx_pll_sel and logical_tx_pll_sel_en ports are enabled by default when you enable the channel and tx pll select/reconfig option. when you disable the logical_tx_pll_sel and logical_tx_pll_sel_en ports, the dynamic reconfiguration controller uses the logical reference index of the cmu pll stored in the .mif generated (logical tx pll). when you enable the logical_tx_pll_sel and logical_tx_pll_sel_en ports, the dynamic reconfiguration controller uses the value at logical_tx_pll_sel to identify the cmu pll, only when you set logical_tx_pll_sel_en to 1'b1. figure 2?51. cmu pll reconfiguration?.mif write transaction note to figure 2?51 : (1) this waveform assumes that the transceiver channel is configured in receiver and transmitter configuration. therefore, the .mif size is 8. addr0 addr1 1 st 16-bits don?t care 2 nd 16-bits addr0 addr37 27 th 16-bits don?t care 3?b100 reconfig_mode_sel[2:0] reconfig_clk w rite_all bu sy reconfig_address_out[5:0] reconfig_address_en reconfig_data[15:0] (1) channel_reconfig_done
2?110 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation how to use the logical_tx_pll_sel port? enable both the logical_tx_pll_sel and logical_tx_pll_sel_en ports. specify the logical reference index of the cmu pll used in the reconfiguration at logical_tx_pll_sel. set a value of 0 or 1 at this port. these 0 and 1 values correspond to the logical reference index that you have already set in the altgx megawizard plug-in manager in the following options: what is the main transmitter pll logical reference index? what is the alternate transmitter pll logical reference index? set logical_tx_pll_sel_en to 1'b1 (the dynamic reconfiguration controller uses the logical reference index value set at logical_tx_pll_sel instead of logical tx pll stored in the .mif ). when can the logical_tx_pll_sel and logical_tx_pll_sel_en ports be used? by default, the altgx_reconfig megawizard plug-in manager enables the logical_tx_pll_sel and logical_tx_pll_sel_en ports when you select the channel and tx pll select/reconfig option as the reconfiguration mode. condition 1: if you want to use the logical_tx_pll_sel only under some conditions and use the logical tx pll (logical reference index value stored in the . mif ) otherwise: both the logical_tx_pll_sel and the logical_tx_pll_sel_en ports are enabled by default. therefore, if you want to use the logical tx pll value stored in the .mif , set logical_tx_pll_sel_en to 1'b0 . instead, if you want to use the value at logical_tx_pll_sel , set logical_tx_pll_sel_en to 1'b1 . (the dynamic reconfiguration controller uses the value set at logical_tx_pll_sel only when you set logical_tx_pll_sel_en to 1'b1 , as shown in figure 2?52 ). figure 2?52. using logical_tx_pll_sel and logical_tx_pll_sell_en ports 0 1 logical tx pll (logical reference index v alue stored in the .mif) logical_tx_pll_sel[1:0] (logical reference index specified in the altgx_reco nfig megawizard plug-in manager) logical_tx_pll_sel_en altgx_reco nfig instance selected logical reference index v alue
chapter 2: hardcopy iv gx dynamic reconfiguration 2?111 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 1 the values at logical_tx_pll_sel and logical_tx_pll_sel_en need to be held at a constant logic level until the channel_reconfig_done signal is asserted. table 2?30 shows how the dynamic reconfiguration controller selects between the logical reference index stored in the .mif (logical tx pll) and the logical reference index specified at the logical_tx_pll_sel port. when you configure a transceiver channel in the altgx megawizard plug-in manager, altera recommends that you keep track of the transmitter pll that drives the channel. 1 the logical_tx_pll_sel port does not modify transceiver settings on the rx side. table 2?30. various combinations of the logical_tx_pll_sel and logical_tx_pll_sel_en ports logical_tx_pll_sel logical_tx_pll_sel_en logical reference index value selected by the altgx_reconfig instance enabled enabled and value is 1 value on the logical_tx_pll_sel port enabled enabled and value is 0 logical reference index value stored in the .mif (logical tx pll) enabled disabled value on the logical_tx_pll_sel port enabled disabled logical reference index value stored in the .mif (logical tx pll)
2?112 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation figure 2?53 shows the required signal transitions to reconfigure the cmu pll with a logical tx pll value of 1. keep the logical_tx_pll_sel and logical_tx_pll_sel_en signals at a constant logic level until the dynamic reconfiguration controller asserts the channel_reconfig_done signal. condition 2: you need to reuse the .mif created for one cmu pll on the other cmu pll of the same transceiver block. consider the following altgx settings: the main pll in the general screen is configured to switch from 2 gbps to 3.125 gbps. you have assigned a logical reference index of 1 for this main pll (cmu0 pll). you generate a .mif for these settings. the logical tx pll value stored in the .mif is 1. you want to reuse the same .mif to reconfigure cmu1 pll instead (your intention is to switch both cmu plls in the transceiver block to 3.125 gbps). however, the logical reference index stored in the .mif is 1 (applicable only to cmu0 pll). you need to overwrite this logical tx pll value of 1 stored in the .mif with the logical reference index of cmu1 pll. you can achieve this by using logical_tx_pll_sel and logical_tx_pll_sel_en and by setting logical_tx_pll_sel = 1'b0 (logical reference index of cmu1 pll) and logical_tx_pll_sel_en = 1'b1 . by doing so, the dynamic reconfiguration controller writes the .mif contents to cmu1 pll (the logical reference index of this pll is automatically 0 when you set the logical reference index of cmu0 pll as 1). the following section describes when to re-use the .mif generated for one cmu pll on another cmu pll, during the various dynamic reconfiguration modes. figure 2?53. signal transition to reconfigure a transmitter pll with a reference index value of 1 100 logical_tx_pll_sel_en logical_tx_pll_sel[1:0] w rite_all channel_reconfig_done reconfig_mode_sel[2:0] dynamic reconfigu ration controller does not register the logical_tx_pll_sel v alu e for this w rite because the logical_tx_pll_sel_en is lo w
chapter 2: hardcopy iv gx dynamic reconfiguration 2?113 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 for channel and cmu pll reconfiguration and cmu pll reconfiguration modes consider that you create a .mif containing the desired altgx settings to reconfigure the cmu0 pll. assume that the logical reference index you assigned to cmu0 pll is 0. you can reuse this .mif created for cmu0 pll on cmu1 pll of the same transceiver block if you want to reconfigure cmu1 pll to the new data rate information stored in the .mif . you must set logical_tx_pll_sel to 1'b1 and logical_tx_pll_sel_en to 1'b1 and then write this .mif into the transceiver channel. by doing so, the dynamic reconfiguration controller overwrites the logical tx pll value stored in the .mif with the logical reference index of cmu1 pll. for channel reconfiguration with tx pll select mode consider that you create a .mif containing the logical reference index of the tx pll that the reconfigured transceiver channel needs to listen to. cmu1 pll is reconfigured with the new data rate information stored in the .mif . assume that the logical reference index you assigned to cmu1 pll is 0 . the .mif then contains the logical reference index of cmu1 pll as 0 (logic tx pll = 0). when you use channel reconfiguration with tx pll select mode, and reconfigure the transceiver channel with this .mif , the transceiver channel is reconfigured to listen to cmu1 pll. if you want to reconfigure the transceiver channel to listen to cmu0 pll instead, you can reuse this .mif . you must set logical_tx_pll_sel to 1'b1 and logical_tx_pll_sel_en to 1'b1 and then write this .mif into the transceiver channel. by doing so, the dynamic reconfiguration controller overwrites the logical tx pll value stored in the .mif with the logical reference index of cmu0 pll. the transceiver channel is reconfigured to listen to cmu0 pll. condition 3: reuse the .mif created for one cmu pll on a cmu pll of another transceiver block. the following section describes when to re-use the .mif generated for one cmu pll on a cmu pll of another transceiver block during the various dynamic reconfiguration modes.
2?114 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation for channel and cmu pll reconfiguration and cmu pll reconfiguration modes: consider that you create a .mif containing the desired altgx settings to reconfigure the cmu0 pll. assume that the logical reference index you assigned to cmu0 pll is 1. you can reuse this .mif created for cmu0 pll on cmu0 pll of another transceiver block if you want to reconfigure the cmu0 pll of the other transceiver block to exactly the same data rate information stored in the .mif . if the logical reference index of the other cmu0 pll is also the same as the logical tx pll value stored in the .mif , you can write the same .mif without using the logical_tx_pll_sel (set logical_tx_pll_sel_en to 1'b0 ). you must set logical_channel_address to the logical channel address of the transceiver channel associated to the other cmu0 pll that you want to reconfigure. if the logical reference index of the other cmu0 pll is different from the logical tx pll value stored in the .mif , you must use the logical_tx_pll_sel port. you must also set logical_channel_address to the logical channel address of the transceiver channel associated to the other cmu0 pll you want to reconfigure. by doing so, the dynamic reconfiguration controller overwrites the logical tx pll value stored in the .mif with the logical reference index of the other cmu0 pll. the cmu0 pll of the other transceiver block is reconfigured with the new data rate information stored in the .mif . for channel reconfiguration with tx pll select mode consider that you create a .mif containing the logical reference index of the tx pll that the reconfigured transceiver channel needs to listen to. assume that the logical reference index you assigned to cmu0 pll is 0 . the .mif then contains the logical reference index of cmu0 pll as 0 (logic tx pll = 0). when you use channel reconfiguration with tx pll select mode, and reconfigure the transceiver channel with this .mif , the transceiver channel is reconfigured to listen to cmu0 pll. if you want to reconfigure another transceiver channel of another transceiver block to listen to its own cmu0 pll, you can reuse this .mif . if the logical reference index of the other cmu0 pll is also the same as the logical tx pll value stored in the .mif , you can write the same .mif without using the logical_tx_pll_sel (set logical_tx_pll_sel_en to 1'b0 ). you must set logical_channel_address to the logical channel address of the transceiver channel associated to the other cmu0 pll that you intend to reconfigure. if the logical reference index of the other cmu0 pll is different from the logical tx pll value stored in the .mif , you must use the logical_tx_pll_sel port. set logical_channel_address to the logical channel address of the transceiver channel associated to the other cmu0 pll you intend to reconfigure.
chapter 2: hardcopy iv gx dynamic reconfiguration 2?115 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 by doing so, the dynamic reconfiguration controller overwrites the logical tx pll value stored in the .mif with the logical reference index of the other cmu0 pll. the transceiver channel of another transceiver block is then reconfigured to listen to the cmu0 pll of its other transceiver block. general guidelines for specifying the input reference clocks the following are general guidelines for setting up the input reference clocks in the reconfig clks screen of the altgx megawizard plug-in manager. assign the identification numbers to all input reference clocks that are used in the design in the reconfig clks screen. you can set up a maximum of 10 input reference clocks and assign identification numbers from 1 to 10 (1, 2, 3, 4, 5, 6, 7, 8, 9, and 10). keep the identification numbers consistent for all the .mifs generated in the design. maintain the input reference clock frequencies settings for all the .mifs . consider you have two altgx instances in your design. table 2?31 describes how to set up the identification numbers for the input reference clocks for all the .mifs involved in the design. table 2?31. example for the specifying the input reference clocks (part 1 of 4) altgx instances and settings altgx setting altgx instance 1 altgx instance 2 what is the number of channels? option in the general screen 1 (regular transceiver channel) 1 (regular transceiver channel)
2?116 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation enable channel and transmitter pll reconfiguration option in the reconfig screen enabled assume the following settings for altgx instance 1: consider that you have set up the transmitter pll in the general screen to run at 3.125 gbps (main pll) consider that you have set up the input reference clock frequency of the main pll as 156.25 mhz the regular transceiver channel configured in altgx instance 1 is therefore listening to this main pll consider that your intention is to reconfigure the data rate of the regular transceiver channel to 2gbps select the use alternate transmitter pll option to dynamically reconfigure the transceiver channel to listen to an alternate pll (channel reconfiguration with tx pll select mode) enabled assume the following settings for altgx instance 2: consider that you have set up the transmitter pll in the general screen to run at 1 gbps (main pll) consider that you have set up the input reference clock frequency of the main pll as 125 mhz the regular transceiver channel configured in altgx instance 2 is therefore listening to this main pll consider that your intention is to reconfigure the data rate of the regular transceiver channel to 1.250 gbps select the use alternate transmitter pll option to dynamically reconfigure the transceiver channel to listen to an alternate pll (channel reconfiguration with tx pll select mode) use alternate transmitter pll option in the reconfig screen enabled set up the alternate transmitter pll to run at 2gbps set up the logical reference index of the alternate transmitter pll (for example, 0 ) set up the protocol and starting channel number settings consider that you have set up the input reference clock of the alternate transmitter pll as 125 mhz. enabled set up the alternate transmitter pll to run at 1.250 gbps set up the logical reference index of the alternate transmitter pll (for example: 1 ) set up the protocol and starting channel number settings consider that you have set up the input reference clock of the alternate transmitter pll as 156.25 mhz table 2?31. example for the specifying the input reference clocks (part 2 of 4) altgx instances and settings altgx setting altgx instance 1 altgx instance 2
chapter 2: hardcopy iv gx dynamic reconfiguration 2?117 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 what is the main transmitter pll logical reference index? option in the reconfig clks screen the altgx megawizard plug-in manager automatically sets up the logical reference index of the main pll as the inverse of the logical reference index of the alternate transmitter pll in this case, the logical reference index of the main transmitter pll is set up as 1 . the altgx megawizard plug-in manager automatically sets up the logical reference index of the main pll as the inverse of the logical reference index of the alternate transmitter pll in this case, the logical reference index of the main transmitter pll is set up as 0 . what is the selected input clock source for the transmitter pll and receiver pll? option in the reconfig clks screen in altgx instance 1, you have set up the input reference clock as 156.25 mhz for main transmitter pll assign an identification number to 156.25 mhz. because there are a total of two input reference clock frequencies in this design (156.25 mhz and 125 mhz), you can assign a value of 1 or 2 (for example, 2 ) in altgx instance 2, you have set up the input reference clock as 125 mhz for main transmitter pll assign an identification number to 125 mhz. because there are a total of two input reference clock frequencies in this design (156.25 mhz and 125 mhz), you can assign a value of 1 or 2 (for example, 1 ) what is the selected input clock source for the alternate transmitter pll? option in the reconfig clks screen when you set up the identification number of the input clock source for the main transmitter pll (156.25 mhz) as 2, you must set up the identification of the input clock source for the alternate transmitter pll (125 mhz) as 1 . when you set up the identification number of the input clock source for the main transmitter pll (125 mhz) as 2, you must set up the identification of the input clock source for the alternate transmitter pll (156.25 mhz) as 1 . table 2?31. example for the specifying the input reference clocks (part 3 of 4) altgx instances and settings altgx setting altgx instance 1 altgx instance 2
2?118 chapter 2: hardcopy iv gx dynamic reconfiguration description of transceiver channel reconfiguration modes hardcopy iv device handbook, volume 3 ? june 2009 altera corporation .mif generation enable the quartus ii settings for generating a .mif for altgx instance 1 for more information about these settings, refer to ?quartus ii settings for .mif generation? on page 2?70 consider that the name of the .mif generated is altgx_instance1 .mif enable the quartus ii settings for generating a .mif for altgx instance 2 for more information about these settings, refer to ?quartus ii settings for .mif generation? on page 2?70 consider that the name of the .mif generated is altgx_instance2 .mif because there are two .mifs generated for this design, you must maintain the identification numbers of the input reference clocks in this design for both .mifs . figure 2?54 shows the input reference clock connections to the transceiver channels based on what you set as the input clock source for each of the two transmitter plls in the design. table 2?31. example for the specifying the input reference clocks (part 4 of 4) altgx instances and settings altgx setting altgx instance 1 altgx instance 2
chapter 2: hardcopy iv gx dynamic reconfiguration 2?119 description of transceiver channel reconfiguration modes ? june 2009 altera corporation hardcopy iv device handbook, volume 3 figure 2?54. input reference clocks connections to the transceiver channels full duplex transceiver channel 1 cmu0 pll rx pll digital +analog logic cmu1 pll digital+analog logic tx channel 1 logical tx pll select rx channel 1 156 .25 mhz 125mhz refclk0 (identification number = 2) refclk1 (identification number = 1) 3.125 gbps 3.125 gbps 3.125 gbps local divider 3.125 gbps 1 gbps cmu channels clock mux clock mux clock mux full duplex transceiver channel 2 rx pll digital +analog logic digital+analog logic tx channel 2 logical tx pll select rx channel 2 1 gbps 1 gbps 1 gbps local divider clock mux based on what you have set up as the input clock source for cmu1 pll, this clock mux selects the corresponding input clock source for cmu1 pll. based on what you have set up as the input clock source for cmu0 pll, this clock mux selects the corresponding input clock source for cmu0 pll.
2?120 chapter 2: hardcopy iv gx dynamic reconfiguration design examples: dynamic reconfiguration controller hardcopy iv device handbook, volume 3 ? june 2009 altera corporation design examples: dynamic reconfiguration controller (altgx_reconfig) the following design examples describe the possible topologies of the dynamic reconfiguration controller with altgx instances. table 2?32 lists the various dynamic reconfiguration examples described in this section. example 1: one reconfiguration controller connected to multiple altgx instances consider a design with two altgx instances: altgx instance 1 with five transceiver channels and altgx instance 2 with three transceiver channels. assume the following for example 1: altgx instance 1 and altgx instance 2 cannot be physically packed into the same transceiver block. one dynamic reconfiguration controller controls both altgx instances. you want to dynamically reconfigure the transmit v od pma control ( tx_vodctrl ) of the first channel of altgx instance 1 and receiver equalization pma control ( rx_eqctrl ) of the second channel of altgx instance 2. table 2?32. design examples using the dynamic reconfiguration controller example overview example 1 this example describes a single controller controlling multiple instances of an altgx megafunction. this example illustrates ?method 1? on page 2?54 of the pma controls reconfiguration mode. example 2 this example describes a single controller controlling a single altgx instance. this example illustrates ?method 1? on page 2?54 of the pma controls reconfiguration mode. example 3 this example describes the hdl construct requirements if you are stamping the altgx instances several times. each altgx instance in turn can have more than one transceiver channel. this example illustrates ?method 2? on page 2?56 of the pma controls reconfiguration mode. example 4 this design example explains the steps to dynamically divide the transmit data rate of a transceiver channel by 4, 2, or 1 without requiring .mif generation. example 5 this design example explains the steps to dynamically reconfigure a cmu pll using cmu pll reconfiguration mode. this example illustrates the generation and usage of a .mif file. example 6 this design example explains the steps to dynamically reconfigure a transceiver channel between a gige configuration and a sonet/sdh oc48 configuration.
chapter 2: hardcopy iv gx dynamic reconfiguration 2?121 design examples: dynamic reconfiguration controller (altgx_reconfig) ? june 2009 altera corporation hardcopy iv device handbook, volume 3 figure 2?55 shows the altgx_reconfig instance connected to both altgx instance 1 and altgx instance 2. table 2?33 lists the altgx and altgx_reconfig settings and instances for example 1. figure 2?55. pma controls reconfiguration for example 1 note to figure 2?55 : (1) reconfig_fromgxb[50:0] = { reconfig_fromgxb2[16:0] , reconfig_fromgxb1[33:0]}. altgx_reco nfig instance set the what is the number of channels controlled by the reconfig controller? option = 12 set the what is the starting channel number? option = 8 set the what is the starting channel number? option = 0 reconfig_fromgxb[50:0] (1) reconfig_fromgxb2[16:0] reconfig_fromgxb1[33:0] reconfig_fromgxb[3:0] bu sy altgx instance 2 (number of channels is 3) altgx instance 1 (number of channels is 5) reconfig_clk read w rite_all tx_v odctrl [2:0] rx_eq ctrl [3:0] rx_tx_du plex_sel[1:0] logical_channel_address[3:0] data_v alid table 2?33. altgx and altgx_reconfig settings and instances for example 1 (part 1 of 2) altgx settings and instances altgx_reconfig settings and instance altgx setting altgx instance 1 altgx instance 2 altgx_reconfig setting altgx_reconfig instance 1 what is the number of channels? option in the general screen 5 (regular transceiver channels) 3 (regular transceiver channels) what is the number of channels controlled by the reconfig controller? option in the reconfiguration settings screen. for more information, refer to ?total number of channels controlled by the altgx_reconfig instance? on page 2?35 . determine the highest logical channel address (10). round it up to the next multiple of 4. set this option to 12 .
2?122 chapter 2: hardcopy iv gx dynamic reconfiguration design examples: dynamic reconfiguration controller hardcopy iv device handbook, volume 3 ? june 2009 altera corporation altgx instances and altgx_re config inst ances connections use the following steps to connect the altgx and altgx_reconfig instances: 1. connect the reconfig_fromgxb1[33:0] output port from altgx instance 1 to the reconfig_fromgxb [33:0] input port of the altgx_reconfig instance. 2. similarly, connect the reconfig_fromgxb2[16:0] output port from altgx instance 2 to the reconfig_fromgxb[50:34] input port of the altgx_reconfig instance. 3. connect the reconfig_togxb[3:0] output port of the altgx_reconfig instance to the reconfig_togxb[3:0] input ports of both altgx instance 1 and altgx instance 2. what is the starting channel number? option in the reconfig screen. for more information, refer to ?logical channel addressing? on page 2?23 . set this option to 0 . the logical channel addresses of the 1st to 5th channels are 0 , 1 , 2 , 3 , and 4 , respectively. set this option to 8 . the logical channel addresses of the 1st to 3rd channels are 8 , 9 , and 10 , respectively. use the 'logical_channel_add ress' port for analog controls reconfiguration option in the analog controls screen. select this option. the altgx_reconfig megawizard plug-in manager enables the logical_ channel_ address[3:0] input port analog controls (vod, pre-emphasis, and manual equalization) option in the reconfig screen enable this option. enable this option. use the rx_tx_duplex_ sel port to enable the rx only, tx only, or duplex reconfiguration option in the error checks/data rate switch screen. select this option. the altgx_reconfig megawizard plug-in manager enables the rx_tx_duplex_ sel[1:0] input port. the various analog controls in the analog controls screen. select the tx_vodctrl and rx_eqctrl controls. tx_vodctrl is 3bits wide rx_eqctrl is 4bits wide. reconfig_ fromgxb1 and reconfig_ fromgxb2 outputs. reconfig_ fromgxb1 is 34 bits wide (2 * 17) reconfig_ fromgxb2 is 17 bits wide (1 * 17) reconfig_ fromgxb input reconfig_ fromgxb is 51 bits wide (3 * 17, 12 channels can logically fit into three transceiver blocks) table 2?33. altgx and altgx_reconfig settings and instances for example 1 (part 2 of 2) altgx settings and instances altgx_reconfig settings and instance altgx setting altgx instance 1 altgx instance 2 altgx_reconfig setting altgx_reconfig instance 1
chapter 2: hardcopy iv gx dynamic reconfiguration 2?123 design examples: dynamic reconfiguration controller (altgx_reconfig) ? june 2009 altera corporation hardcopy iv device handbook, volume 3 for more information, refer to ?connecting the reconfig_fromgxb and reconfig_togxb ports? on page 2?40 . dynamically reconfiguring the tx_vodctrl and rx_eqctrl pma controls using method 1 for more information about dynamically reconfiguring the pma controls using method 1, refer to ?write transaction? on page 2?58 in ?method 1? on page 2?54 . example 2: two altgx_reconfig instances connected to two altgx instances this design example has two instances of distinct configurations: altgx instance 1 with five transceiver channels and altgx instance 2 with three transceiver channels. this configuration requires separate dynamic reconfiguration controllers for the two instances. this scenario covers the case of multiple dynamic reconfiguration controllers controlling multiple instances of the altgx. figure 2?56 shows altgx_reconfig instance 1 connected to altgx instance 1 and altgx_reconfig instance 2 connected to altgx instance 2. assume that you want to reconfigure the transmit v od pma control of the second channel of the altgx instance 1 and the receive equalization pma control of the third channel of altgx instance 2. the following are the steps to set up the configuration. figure 2?56. pma controls reconfiguration for example 2 altgx_reco nfig instance 1 set the what is the number of channels controlled by the reconfig controller? option = 8 set the what is the starting channels number? option = 0 reconfig_fromgxb [33:0] reconfig_fromgxb [33:0] reconfig_togx b [3:0] bu sy altgx instance 1 (number of channels is 5) reconfig_clk read w rite_all tx_v odctrl [2:0] rx_tx_d u plex_sel[1:0] logical_channel_address [2:0] data_v alid altgx_reco nfig instance 2 set the what is the number of channels controlled by the reconfig controller? option = 4 set the what is the starting channels number? option = 0 reconfig_fromgxb [16:0] reconfig_fromgxb [16:0] reconfig_togx b [3:0] bu sy altgx instance 2 (number of channels is 3) reconfig_clk read w rite_all rx_tx_d u plex_sel[1:0] logical_channel_address 1:0] rx_eq ctrl [3:0] data_v alid
2?124 chapter 2: hardcopy iv gx dynamic reconfiguration design examples: dynamic reconfiguration controller hardcopy iv device handbook, volume 3 ? june 2009 altera corporation table 2?34 lists the altgx and altgx_reconfig settings and instances for example 2. table 2?34. altgx and altgx_reconfig settings and instances for example 2 altgx settings and instances altgx_reconfig settings and instance altgx setting altgx instance 1 altgx instance 2 altgx_reconfig setting altgx_reconfig instance 1 what is the number of channels? option in the general screen 5 (regular transceiver channels) 3 (regular transceiver channels) what is the number of channels controlled by the reconfig controller? option in the reconfiguration settings screen for more information, refer to ?total number of channels controlled by the altgx_reconfig instance? on page 2?35 . determine the highest logical channel address (4). round it up to the next multiple of 4. set this option to 8 . what is the starting channel number? option in the reconfig screen. for more information, refer to ?logical channel addressing? on page 2?23 . set this option to 0 . the logical channel addresses of the 1st to 5th channels are 0 , 1 , 2 , 3 , and 4 , respectively. set this option to 0 . the logical channel addresses of the 1st to 3rd channels are 0 , 1 , and 2 , respectively. use 'logical_channel_add ress' port for analog controls reconfiguration option in the analog controls screen select this option. the altgx_reconfig megawizard plug-in manager enables the logical_ channel_ address[3:0] input port. analog controls (vod, pre-emphasis, and manual equalization) option in the reconfig screen enable this option. enable this option. use the rx_tx_duplex_ sel port to enable the rx only, tx only, or duplex reconfiguration option in the error checks/data rate switch screen. select this option. the altgx_reconfig megawizard plug-in manager enables the rx_tx_duplex_ sel[1:0] input port. the various analog controls in the analog controls screen. select the tx_vodctrl control. tx_vodctrl is 3bits wide. reconfig_ fromgxb output reconfig_ fromgxb is 34 bits wide (2 * 17) reconfig_ fromgxb is 17 bits wide (1 * 17) reconfig_ fromgxb input reconfig_ fromgxb is 34 bits wide (2 * 17, 8 channels can logically fit into three transceiver blocks).
chapter 2: hardcopy iv gx dynamic reconfiguration 2?125 design examples: dynamic reconfiguration controller (altgx_reconfig) ? june 2009 altera corporation hardcopy iv device handbook, volume 3 altgx instances and altgx_re config inst ances connections use the following steps to connect the altgx and altgx_reconfig instances: 1. connect the reconfig_fromgxb signal from each altgx instance to the same signal of the corresponding altgx_reconfig instance. for more information, refer to figure 2?56 . 2. connect the reconfig_togxb signal from each altgx_reconfig instance to the same signal of the corresponding altgx instance. dynamically reconfiguring the tx_vodctrl pma control of altgx instance 1 from altgx_reconfig inst ance 1 using method 1 for more information about dynamically reconfiguring the pma controls using method 1, refer to ?write transaction? in ?method 1? on page 2?54 . dynamically reconfiguring the rx_eqctrl pma control of altgx instance 2 from altgx_reconfig inst ance 2 using method 1: for more information about dynamically reconfiguring the pma controls using method 1, refer to ?write transaction? in ?method 1? on page 2?54 . example 3: one altgx_reconfig instance connected to an altgx instance stamped five times this design example consists of five channels of transceivers. this configuration has one dynamic reconfiguration controller to control five channels and includes stamping five instantiations of one channel altgx instance configuration. this example assumes the instantiation name is ?instance1?. altgx instance with one transceiver channel use the following steps for altgx instances with one transceiver channel: 1. set the what is the number of channels? option in the general screen of the altgx megawizard plug-in manager to 1. 2. enable the analog controls (vod, pre-emphasis, and manual equalization) option in the reconfig screen of the altgx megawizard plug-in manager. 3. the reconfig_fromgxb output signal is transceiver block based; the number of bits for this instance is 17. this is because the number of channels is one and it can logically fit into a single transceiver block. the reconfig_togxb input signal is a fixed bus (4 bits wide). 4. set the what is the starting channel number ? option in the reconfig screen of the altgx megawizard plug-in manager to 0 . for more information, refer to ?logical channel addressing? on page 2?23 . 5. click finish . instantiating five transceiver channels using the same altgx instance when you stamp instance 1 five times, the what is the starting channel number? options of the other five stamped instances (assume instance2, instance3, instance4, instance5, and instance6) are 4, 8, 12 , and 16 , respectively. for more information, refer to ?logical channel addressing? on page 2?23 .
2?126 chapter 2: hardcopy iv gx dynamic reconfiguration design examples: dynamic reconfiguration controller hardcopy iv device handbook, volume 3 ? june 2009 altera corporation dynamic reconfiguration controller instance (altgx_reconfig instance) use the following steps for the dynamic reconfiguration controller instance (altgx_reconfig instance): 1. launch the altgx_reconfig megawizard plug-in manager. 2. set the what is the number of channels controlled by the reconfig controller? option in the reconfiguration settings screen of the altgx_reconfig megawizard plug-in manager to 20 . this enables five sets of the megawizard plug-in manager signals ( reconfig_fromgxb[84:0] ). 3. connect each of the stamped altgx instances to one set of the megawizard plug-in manager signals. 4. select the necessary write and read controls to write in and read out from the v od , pre-emphasis, equalization, and dc gain options. for example, if you select the v od setting, the tx_vodctrl signal is 60 bits wide (3 bits per channel). the tx_vodctrl [2:0] corresponds to the single channel of the first stamped instance. the bits tx_vodctrl [11:3] are not used because they correspond to the unused channels in the first stamped instance with logical channel addresses 1 to 3. similarly, tx_vodctrl [14:12] corresponds to the single channel of the second stamped instance, and so on. altgx instances and altgx_re config inst ance connections use the following steps to connect the altgx and altgx_reconfig instances: 1. connect the reconfig_fromgxb signal from each altgx instance to the same signal in the altgx_reconfig instance. you must connect it in such a way that the reconfig_fromgxb output port of the first altgx instance (altgx instance with the what is the starting channel number? option of 0) is connected to the lsb of the reconfig_fromgxb input port of the altgx_reconfig instance, and so on. 2. connect the reconfig_togxb signal from the altgx_reconfig instance to the same signal in each of the altgx instances. dynamically reconfiguring the tx_vodctrl of instance 1 using method 2 use the following steps to dynamically reconfigure tx_vodctrl on instance 1 using method 2: 1. set the tx_vodctrl port to the desired setting. for example, if you want to write a v od value of 2, set the tx_vodctrl [2:0] port to 3'b010 . 2. for more information, refer to ?method 2? on page 2?56 . 1 when you perform a write transaction using method 2, the values on the pma control ports are written on all transceiver channels connected to the dynamic reconfiguration controller. therefore, ensure that you also have the desired values on tx_vodctrl [59:3] . if you want to ensure that the v od settings of the remaining channels are not affected, you can optionally perform a read transaction and obtain the existing values and write back the same values.
chapter 2: hardcopy iv gx dynamic reconfiguration 2?127 design examples: dynamic reconfiguration controller (altgx_reconfig) ? june 2009 altera corporation hardcopy iv device handbook, volume 3 example 4: data rate division in tx mode this design example explains the steps to dynamically divide the transmit data rate of a transceiver channel by 4, 2, or 1 without requiring .mif generation. the design contains the following two instances: altgx instance 1?two regular transceiver channels configured in basic functional mode with 8b/10b enabled and running at 4.25 gbps data rate. you can reconfigure the mode dynamically between 4.25 gbps, 2.125 gbps, and 1062.5 mbps. altgx_reconfig instance 1?a single dynamic reconfiguration controller connected to altgx instance 1. use the following steps to dynamically reconfigure the transmit data rate of the transceiver channel: 1. create a basic functional mode by setting the operation mode to receiver and transmitter configuration and the what is the number of channels? option to 2. 2. set up the options shown in table 2?35 for both the altgx and altgx_reconfig megawizard plug-in managers. table 2?35. data rate division in tx dynamic reconfiguration mode for example 4 (part 1 of 3) altgx settings and instances altgx_reconfig settings and instance altgx setting altgx instance 1 (basic functional mode, receiver and transmitter operation mode) altgx_reconfig setting altgx_reconfig instance 1 what is the deserializer block width? option select double-width mode. this is required because the highest data rate in this example is 4.25 gbps (single-width mode can be selected only up to 3.750 gbps). what is the number of channels controlled by the reconfig controller? option in the reconfiguration settings screen for more information about this setting, refer to ?total number of channels controlled by the altgx_reconfig instance? on page 2?35 . determine the highest logical channel address (1). round it up to the next multiple of 4. set this option to 4 . what is the channel width? option you can set the channel width to 16 or 32 . the lowest core fabric frequency allowed in the quartus ii software is 25 mhz. therefore, the transceiver runs at 1062.5 mbps with a 32-bit core fabric-transceiver interface. the core fabric clock frequency in this case is 26.5 mhz (1062.5/40 = 26.5625). data rate division in tx option in the reconfiguration settings screen enable this option. this creates the rate_switch_ctrl [1:0] input signal. refer to ta bl e 2? 24 to set a value at the rate_switch_ctrl [1:0] port.
2?128 chapter 2: hardcopy iv gx dynamic reconfiguration design examples: dynamic reconfiguration controller hardcopy iv device handbook, volume 3 ? june 2009 altera corporation what is the input clock frequency? option set the input frequency to 106.25 mhz . use the rate_switch_out port to read out the current data rate division option in the error checks/data rate switch screen. you can optionally enable the rate_switch_out [1:0] output signal by selecting this option. for more information, refer to ?total number of channels controlled by the altgx_reconfig instance? on page 2?35 , which shows the values for each of the rate_switch_ctrl [1:0] settings. use the rate_switch_ctrl [1:0] signal only for dividing the data rate of the transmit side. to divide the data rate for both transmit and receive sides, a .mif -based approach is required. what is the starting channel number? option in the reconfig screen. (for more information, refer to ?total number of channels controlled by the altgx_reconfig instance? on page 2?35 ). set this option to 0 . the logical channel addresses of the 1st and 2nd channels are 0 and 1 , respectively. the logical_channel_ address[1:0] port this port is enabled automatically because the number of channels controlled is more than 1. specify the channel to be reconfigured at this logical_channel_ address [1:0] port. reconfig_ fromgxb1 output reconfig_fromgxb1 is 17 bits wide (1 * 17). connect reconfig_fromgxb1 [16:0] to the reconfig_fromgxb [16:0] input of the altgx_reconfig instance. reconfig_fromgxb input reconfig_fromgxb is 17 bits wide (1 * 17, 4 regular transceiver channels can logically fit into one transceiver block). connect reconfig_fromgxb [16:0] to the reconfig_fromgxb1 [16:0] output of the altgx instance. table 2?35. data rate division in tx dynamic reconfiguration mode for example 4 (part 2 of 3) altgx settings and instances altgx_reconfig settings and instance altgx setting altgx instance 1 (basic functional mode, receiver and transmitter operation mode) altgx_reconfig setting altgx_reconfig instance 1
chapter 2: hardcopy iv gx dynamic reconfiguration 2?129 design examples: dynamic reconfiguration controller (altgx_reconfig) ? june 2009 altera corporation hardcopy iv device handbook, volume 3 1 the alternate reference clock is not required because one clock source is used. also, all data rates can be derived from the 106.25 mhz clock. 1 create the altgx_reconfig instance control logic, reset control logic, and the core fabric logic to handle the data path. for more information about transceiver resets, refer to ?error indication in the altgx_reconfig megawizard plug-in manager? on page 2?139 . example 5: cmu pll reconfiguration mode with altgx instances in transmitter only configuration consider the following scenario: the design has four transmitter only altgx instances in the same transceiver block. all four instances are configured in basic functional mode and 2.5 gbps data rate. all four channels can listen to cmu0 pll. the input reference clock used by cmu0 pll is 100 mhz. you want to reconfigure all four channels identically to 2 gbps together. reconfig_togxb [3:0] input connect the reconfig_togxb[3:0] signals between the altgx instance 1 and altgx_reconfig instance 1. reconfig_togxb[3:0] output connect the reconfig_togxb[3:0] signals between the altgx instance 1 and altgx_reconfig instance 1. channel and transmitter pll reconfiguration option in the reconfig screen enable this option. this is required to allow the altgx_reconfig instance to modify the transmitter channel local divider values dynamically. use the ?rx_tx_duplex_sel? port to enable rx only, tx only, or duplex configuration option in the error checks/data rate switch screen this setting is optional and not required in the data rate division in tx mode. table 2?35. data rate division in tx dynamic reconfiguration mode for example 4 (part 3 of 3) altgx settings and instances altgx_reconfig settings and instance altgx setting altgx instance 1 (basic functional mode, receiver and transmitter operation mode) altgx_reconfig setting altgx_reconfig instance 1
2?130 chapter 2: hardcopy iv gx dynamic reconfiguration design examples: dynamic reconfiguration controller hardcopy iv device handbook, volume 3 ? june 2009 altera corporation figure 2?57 shows this scenario before and after dynamic reconfiguration. you can achieve this by reconfiguring the cmu0 pll once to run for 2 gbps. this, in turn, changes the transmit data rate of all four channels listening to this cmu0 pll. you must enable .mif generation. change the settings shown in table 2?36 and save them in the .mif . figure 2?57. before and after example of cmu pll reconfiguration tx only cha nn el 1 cmu channels tx only cha nn el 2 refclk0 refclk1 100 mhz 125 mhz clock m ux clock m ux 2 gbps cmu0 pll 2.5 gbps cmu1 pll tx only cha nn el 3 logical tx pll select logical tx pll select logical tx pll select local divider local divider local divider 6.25 gbps digital+analog logic 6.25 gbps digital+analog logic 6.25 gbps digital+analog logic 6.25 gbps digital+analog logic tx only cha nn el 4 local divider logical tx pll select blocks reconfig ured using cmu pll reconfigu ration mode table 2?36. cmu pll reconfiguration scenario (part 1 of 2) altgx instances altgx_reconfig instance altgx setting four tx only instances altgx_reconfig setting altgx_reconfig instance what is the effective data rate? option 2 gbps channel and tx pll select/reconfig option enabled
chapter 2: hardcopy iv gx dynamic reconfiguration 2?131 design examples: dynamic reconfiguration controller (altgx_reconfig) ? june 2009 altera corporation hardcopy iv device handbook, volume 3 after generating the .mif , follow the steps listed in ?cmu pll reconfiguration operation? on page 2?108 to write all the words. example 6: dynamically reconfiguring a transceiver channel between a gige configuration and a sonet/sdh oc48 configuration the altgx megawizard plug-in manager settings?for example, data path, clocking, and core fabric-transceiver interface width?are different for the gige configuration versus the sonet/sdh oc48 configuration. the differences between the two configurations are listed in table 2?36 . enable channel and transmitter pll reconfiguration option enabled use ?reconfig_address_en? option enabled enable channel and transmitter pll reconfiguration option enabled what is the main transmitter pll reference index? option 1 how many input clocks? option 2 what is the selected input clock source for the transmitter pll and receiver pll? option 1 what is clock 0 input frequency? option 125 mhz table 2?36. cmu pll reconfiguration scenario (part 2 of 2) altgx instances altgx_reconfig instance altgx setting four tx only instances altgx_reconfig setting altgx_reconfig instance table 2?37. differences between gige and sonet/sdh oc48 (part 1 of 2) number functional block gige sonet/sdh oc48 1 core fabric-transceiver interface width 81 6 2 8b/10b enabled yes no 3 rate matcher enabled yes no 4 byte ordering block enabled no yes 5 clock used for synchronizing the receive output data ( tx_dataout ) tx_clkout (because rate matcher is used) rx_clkout 6 data rate 1.25 gbps 2.488 gbps
2?132 chapter 2: hardcopy iv gx dynamic reconfiguration design examples: dynamic reconfiguration controller hardcopy iv device handbook, volume 3 ? june 2009 altera corporation these differences determine the selection of parameters in the altgx megawizard plug-in manager and the required core array to dynamically reconfigure a transceiver channel between these two configurations. figure 2?58 shows the required functional blocks to perform channel reconfiguration. 7 allowed input reference clock frequencies 62.5 mhz 125 mhz 77.76 mhz 155.52 mhz 311.04 mhz 622.08 mhz 8 pcs-pma interface width 10 (because data is 8b/10b encoded) 8 table 2?37. differences between gige and sonet/sdh oc48 (part 2 of 2) number functional block gige sonet/sdh oc48 figure 2?58. dynamically reconfiguring between gige and sonet/sdh oc48 configurations user logic for gige and so n et / sdh datapath reset control logic user control logic to control the altgx_reco n fig interface dynamic reconfig u ration controller (altgx_reco n fig) altgx interface user logic in the core fa b ric ram initializer (altmem_i n it) containing the gige .mif ram initializer (altmem_i n it) containing the sonet/sdh .mif ram transcei v er interfaces ram
chapter 2: hardcopy iv gx dynamic reconfiguration 2?133 design examples: dynamic reconfiguration controller (altgx_reconfig) ? june 2009 altera corporation hardcopy iv device handbook, volume 3 the description of the functional blocks is divided into four sections. the topics described in each section are as follows: section i?lists the steps to configure the altgx instance to generate the .mif for gige and sonet/sdh oc48 configurations. it also lists the steps to create the altgx_reconfig instance. section ii?sets up the user control logic for the altgx_reconfig controller. section iii?explains the logic to process the gige and sonet/sdh data. this logic is required due to the differences in the data interface widths and the clocking between the two configurations (shown in table 2?36 ). section iv?explains how to reset the user control logic to control the transceiver channel and system resets. section i?configure the altgx instance to generate the .mif use the following steps to generate a .mif for gige and sonet/sdh oc48 configurations: 1. set up the altgx megawizard plug-in manager with the desired settings for the gige configuration. generate the altgx instance for the gige configuration. name this instance ?gige_gxb?. table 2?38 explains the various options to set in the gige_gxb instance. 2. generate the altgx_reconfig instance to control the gige_gxb instance. 3. create a top-level design only with the gige_gxb instance. enable the quartus ii settings to generate a .mif . generate the .mif for the gige configuration. compile the top-level design. the quartus ii software generates a .mif for the gige configuration. the gige_gxb .mif contains the desired gige configuration settings. 4. modify the altgx instance with the desired settings for the sonet/sdh oc48 configuration. name this instance ?sonet_gxb?. 5. create a top-level design only with the sonet_gxb instance. enable the quartus ii settings to generate a .mif . compile the top-level design. the quartus ii software generates a .mif for the sonet/sdh oc4 configuration. the sonet_gxb .mif contains the desired sonet/sdh configuration settings. 6. initialize two memory elements with the .mif contents and write user logic to select the appropriate .mif to use with the altgx_reconfig instance. table 2?38 shows the altgx instance settings for a single regular transceiver channel in gige configuration. table 2?38. step 1: generate the altgx instance for the gige configuration (part 1 of 3) altgx megawizard plug-in manager option setting general screen which protocol will you be using? option set the protocol to gige configuration.
2?134 chapter 2: hardcopy iv gx dynamic reconfiguration design examples: dynamic reconfiguration controller hardcopy iv device handbook, volume 3 ? june 2009 altera corporation pll/ports screen in the optional ports section: select the following control and status signals: rx_digitalreset tx_digitalreset rx_analogreset rx_pll_locked rx_freqlocked add the other required status signals (for a list of altgx signals and their functionality, refer to the transceiver port list in the hardcopy iv gx transceiver architecture chapter in volume 3 of the hardcopy iv device handbook .) reconfig screen analog controls (vod, pre-emphasis, and manual equalization) option if you need control of the transceiver pma controls, select analog pma controls . for more information about pma controls, refer to ?pma controls reconfiguration? on page 2?52 . enable channel and transmitter pll reconfiguration option because you need to reconfigure the transceiver channel from a gige configuration to a sonet/sdh oc48 configuration, select this option. channel interface option selecting this option creates the data interface signals tx_datainfull[43:0] and rx_dataoutfull[63:0] that are comprised of control and data signals. this selection is required because the core fabric-transceiver interface is different for a gige configuration versus a sonet/sdh configuration (refer to row 8 in table 2?37 on page 2?131 ). the description of the individual bits of tx_datainfull[43:0] and rx_datainfull[63:0] are provided in table 2?28 on page 2?91 and table 2?29 on page 2?94 . use alternate transmitter pll option selecting this option enables the second pll for the sonet/sdh oc48 configuration. a second pll is needed because of the difference in the required input clock frequency and data rate between the gige and sonet/sdh oc48 configurations (refer to rows 6 and 7 in table 2?37 on page 2?131 ). what is the protocol to be reconfigured to? option set this option to sonet/sdh . what is the subprotocol to be reconfigured to? option set sub protocol to oc48 . what is the input clock frequency? and what is the alternate transmitter pll bandwidth mode? options select the input clock frequency and alternate transmitter pll bandwidth mode options based on the requirements. the allowed reference clock input frequencies for sonet/sdh oc48 are specified in row 7 of table 2?37 on page 2?131 . table 2?38. step 1: generate the altgx instance for the gige configuration (part 2 of 3) altgx megawizard plug-in manager option setting
chapter 2: hardcopy iv gx dynamic reconfiguration 2?135 design examples: dynamic reconfiguration controller (altgx_reconfig) ? june 2009 altera corporation hardcopy iv device handbook, volume 3 what is the alternate transmitter pll logical reference index? option for the logical reference index option, select 1 or 0 . the quartus ii software uses the logical reference index to select the pll clock outputs for transmit and receive channels when configured to sonet/sdh oc48 protocol. the mux values selected for the gige and sonet/sdh oc48 modes must be different. for example, if you select a logical reference index of 1 for the sonet/sdh oc48 configuration, you need to select 0 for the gige configuration. if you select the same values for the two configurations, the transceiver behavior after reconfiguration becomes unpredictable. reconfig 2 screen how should the receivers be clocked? option select the use the respective channel core clocks option. selecting this option creates the rx_clkout port. select this option because of the clocking differences between the two modes (row 5 of table 2?37 on page 2?131 ). the core fabric logic can clock the receiver output of the altgx instance with rx_clkout for sonet/sdh mode and tx_clkout for gige mode. how should the transmitters be clocked? option select any option. because this example assumes a one channel reconfiguration in the transceiver block, the preceding options will not make a difference. however, if the number of channels used in channel reconfiguration is more than one, altera recommends you select the share single transmitter core clock between transmitters option to conserve clock routing resources. check a control box to use the corresponding control port: option select signals in this option based on the requirements. the signals in this tab can be selected only if the channel interface option is enabled in the reconfig screen. for this example, select the rx_byteorderalignstatus and rx_a1a2sizeout signals because these signals are required for sonet/sdh oc48 configuration. some of the signals are meaningful only for the modes for which they are intended. for example, the rx_byteorderalignstatus signal is only meaningful in the sonet/sdh oc48 configuration. the core fabric logic does not use these signals for gige configuration. for more information about the protocol specific altgx interface signals, refer to the transceiver port list in the hardcopy iv gx transceiver architecture chapter in volume 3 of the hardcopy iv device handbook . in the subsequent screens, select the required signals and complete the megawizard plug-in manager instantiation. table 2?38. step 1: generate the altgx instance for the gige configuration (part 3 of 3) altgx megawizard plug-in manager option setting
2?136 chapter 2: hardcopy iv gx dynamic reconfiguration design examples: dynamic reconfiguration controller hardcopy iv device handbook, volume 3 ? june 2009 altera corporation step 2?create the altgx_reconfig instance for the gige configuration 1. set the what is number of channels controlled by the reconfig controller? option to 1. 2. select analog controls to modify the pma values, if desired. 3. select the channel reconfiguration with tx pll select/reconfig option. this selection is required to perform a channel reconfiguration. 4. select the required signals under the write control and read control options, if the analog controls option in screen 1 is selected. 1 refer to the altgx_reconfig megafunction user guide chapter in volume 3 of the hardcopy iv device handbook for information about write control and read control signals. 5. complete the altgx_reconfig megawizard plug-in manager instantiation. step 3?create a top-level design and generate the .mif for the gige configuration clock input connections for the altgx instance are listed below. the clock source needs to be feed the following clock inputs: gige configuration? pll_inclk and rx_cruclk inputs. sonet/sdh oc48 configuration? pll_inclk_alt and rx_cruclk_alt inputs. 1. because gige is the protocol mode you selected in the first page of the altgx megawizard plug-in manager, the quartus ii software requires the gige clock source to be connected to the pll_inclk and rx_cruclk inputs. 2. connect the cal_blk_clk input of the altgx instance to a clock source. 1 for the cal_blk_clk signal requirements, refer to the transceiver port list in the hardcopy iv gx transceiver architecture chapter in volume 3 of the hardcopy iv device handbook . 3. connect the tx_dataout and rx_datain ports to the top-level module. this is required for the quartus ii software to compile successfully. to generate the .mif , connecting the other input and output ports of the altgx instance is not mandatory. 4. assign pins for the clock ports ( pll_inclk, rx_cruclk, pll_inclk_alt, and rx_cruclk_alt ). if pin assignments are not made for the tx_dataout and rx_datain ports of the altgx instance, the quartus ii software automatically selects pins for these ports and names the .mif with the instance name. the .mif can still be used by any physical transceiver channel to perform reconfiguration. after compilation of the design, the quartus ii software creates the .mif in the reconfig_mif folder under the project directory. copy the .mif and save it in a separate folder. otherwise, the new .mif that is generated for the sonet/sdh configuration will overwrite the current .mif .
chapter 2: hardcopy iv gx dynamic reconfiguration 2?137 design examples: dynamic reconfiguration controller (altgx_reconfig) ? june 2009 altera corporation hardcopy iv device handbook, volume 3 step 4?modify the altgx instance for a sonet/sdh oc48 configuration 1. to create a .mif for the sonet/sdh oc48 configuration, either modify the existing altgx instance created for the gige configuration or create a new instance for the sonet configuration. however, the first method is easier because it does not require major rtl or schematic changes. 2. open the existing altgx instance. select the which protocol you will be using? option and set it to sonet/sdh . set the sub protocol option to oc48 . all the other signals selected for gige mode do not need to be changed. 3. in the reconfig screen, select the channel interface and alternate reference clock options. in the protocol section, select gige . select the same input clock frequency selected for the gige instance in the general screen. 4. for the logical reference clock index option, choose the complement of what you selected for the gige instance. 5. complete the instantiation. step 5?generate the .mif for the sonet/sdh oc48 configuration 1. before compiling the design, in the rtl or schematic, connect pll_inclk and rx_cruclk to the clock source that provides the sonet/sdh oc48 clock. similarly, connect pll_inclk_alt and rx_cruclk_alt to the clock source that provides the gige clock. the quartus ii software generates the new .mif in the /reconfig_mif directory. step 6?initialize two memory elements with the .mif contents and write logic to select the .mif and to control the altgx_reconfig instance 1. assign the two .mifs to the altmem_init megafunction in the megawizard plug-in manager to initialize each of the ram. this megafunction reads from an internal rom (inside the megafunction) or an external rom (on-chip or off-chip), and writes to the ram after power up. f hardcopy iv gx asic does not support pre-loading or initializing internal memory blocks with .mif when used as ram. for more information, refer to ram initializer (altmem_init) megafunction user guide . section ii?control the logic for the dynamic reconfiguration controller the control logic block is required to perform the following functions: select the memory to configure a channel to the gige or sonet/sdh configuration. control the reconfiguration mode (namely the pma controls reconfiguration mode or the channel and cmu pll reconfiguration mode). control the read and write signals to the altgx_reconfig instance based on the busy and data valid signals.
2?138 chapter 2: hardcopy iv gx dynamic reconfiguration design examples: dynamic reconfiguration controller hardcopy iv device handbook, volume 3 ? june 2009 altera corporation section iii?logic and clocking for the gige and sonet/sdh oc48 datapath in the altgx megawizard plug-in manager, the channel interface that created tx_datainfull[43:0] and rx_dataoutfull[63:0] was selected. in addition, the rx_byteorderalignstatus and rx_a1a2size signals were selected. the core fabric selectively uses some of these signals based on whether the transceiver channel is configured in a gige configuration or a sonet/sdh oc48 configuration. table 2?39 provides descriptions for the tx_datainfull[43:0] and rx_dataoutfull[63:0] signals for gige and sonet/sdh oc48 configurations. clocking for the transmit side, the core fabric user logic for the sonet/sdh oc48 and gige configurations sends the data synchronized to the tx_clkout signal. therefore, the clocking for the transmit side remains the same for the two modes. for the receive side, the data and status signals from the altgx instance for the gige configuration is synchronized to tx_clkout because rate matching is used. for the sonet/sdh oc48 configuration, the signals are synchronized to rx_clkout. therefore, the core fabric user logic has two functional protocol specific logic blocks to handle data for the gige and sonet/sdh oc48 configurations. based on the configured protocol mode, the receive side logic selects the appropriate data path. table 2?39. core fabric-transceiver interface signals?gige and sonet/sdh oc48 configurations signal name description gige configuration tx_datainfull[7:0] 8-bit unencoded data input to the transceiver channel tx_datainfull[8] tx_ctrlenable (control signal k/d) rx_dataoutfull[7:0] 8-bit unencoded data output from the transceiver channel rx_dataoutfull[8] rx_ctrldetect (control signal k/d) rx_dataoutfull[9] rx_errdetect rx_dataoutfull[10] rx_syncstatus rx_dataoutfull[11] rx_disperr rx_dataoutfull[12] rx_patterndetect sonet/sdh oc48 configuration tx_datainfull[7:0] lsb data input to the transceiver channel tx_datainfull[29:22] msb data input to the transceiver channel rx_dataoutfull[7:0] lsb data output from the transceiver channel rx_dataoutfull[29:22 msb data output from the transceiver channel rx_dataoutfull[10] , rx_dataoutfull[42] rx_syncstatus[1:0] rx_dataoutfull[12] , rx_dataoutfull[44] rx_patterndetect[1:0]
chapter 2: hardcopy iv gx dynamic reconfiguration 2?139 error indication in the altgx_reconfig megawizard plug-in manager ? june 2009 altera corporation hardcopy iv device handbook, volume 3 section iv?reset control logic the reset control sequence for channel reconfiguration must be followed during and after the channel configuration process. in addition, when resetting the transceiver channel, the reset control logic needs to reset the data path in the core fabric to clear the error data received during the reconfiguration process. f for more information, refer to the reset control and power down chapter in volume 2 in the stratix iv device handbook . 1 for a pma controls only configuration (for example, changing the vod, equalization, dc gain, or pre-emphasis), the transceiver channel or the datapath in the core fabric does not require a reset after reconfiguration. reset is required only for channel reconfiguration or rate switch. simulation to simulate channel reconfiguration, some simulation tools only allow .ram or hexadecimal (intel-format) file ( .hex ) files to initialize the memory. to convert the generated .mif to a .hex file, open the .mif in the quartus ii software and save it as a .hex file. initialize the memory elements with the .hex file to simulate the design. error indication in the altgx_reconfig megawizard plug-in manager the altgx_reconfig megawizard plug-in manager provides an error status signal when you select the enable illegal mode checking option or the enable self recovery option in the error checks/data rate switch screen. the conditions under which the error signal is asserted are: enable illegal mode checking option?when you select this option, the dynamic reconfiguration controller checks whether an attempted operation falls under one of the conditions listed below. the dynamic reconfiguration controller detects these conditions within two reconfig_clk cycles, de-asserts the busy signal, and asserts the error signal for two reconfig_clk cycles. pma controls, read operation?none of the output ports ( rx_eqctrl_out, rx_eqdcgain_out, tx_vodctrl_out, tx_preemp_0t_out , tx_preemp_1t_out , and tx_preemp_2t_out ) are selected in the altgx_reconfig instance. the read signal is asserted. pma controls, write operation?none of the input ports ( rx_eqctrl, rx_eqdcgain, tx_vodctrl, tx_preemp_0t, tx_preemp_1t , and tx_preemp_2t ) are selected in the altgx_reconfig instance. the write_all signal is asserted. enable self recovery option?when you select this option, the controller automatically recovers if the operation did not complete within the expected time. the error signal is driven high whenever the controller performs a self recovery. tx data rate switch using local divider-read operation option?the read transaction is valid only for the following two dynamic reconfiguration modes: pma controls reconfiguration mode tx data rate switch using local divider mode
2?140 chapter 2: hardcopy iv gx dynamic reconfiguration combining transceiver channels with dynamic reconfiguration enabled hardcopy iv device handbook, volume 3 ? june 2009 altera corporation tx data rate switch using local divider-write operation with unsupported value option: the rate_switch_ctrl[1:0] input port is set to 11 the reconfig_mode_sel[2:0] input port is set to 4 (if other reconfiguration mode options are selected in the reconfiguration settings screen) the write_all is asserted tx data rate switch using local divider-write operation without input port option: the rate_switch_ctrl[1:0] input port is not used the reconfig_mode_sel[2:0] port is set to 4 (if other reconfiguration mode options are selected in the reconfiguration settings screen) the write_all is asserted tx data rate switch using local divider- read operation without output port option: the rate_switch_out[1:0] output port is not used the reconfig_mode_sel[2:0] port is set to 4 (if other reconfiguration mode options are selected in the reconfiguration settings screen) the read is asserted channel and/or tx pll reconfiguration-read operation option: the reconfig_mode_sel[2:0] input port is set to 1, 4, 5 , or 6 the read signal is asserted combining transceiver channels with dynamic reconfiguration enabled packing the transceiver channels into the same physical transceiver block is called ?combining?. you can combine the transceiver channels in a design into the same physical transceiver block by assigning the tx_dataout and rx_datain pins of the channels to the same transceiver block. the quartus ii software also allows you to combine multiple channels into the same physical transceiver block based on the same requirements described in the following sections.
chapter 2: hardcopy iv gx dynamic reconfiguration 2?141 combining transceiver channels with dynamic reconfiguration enabled ? june 2009 altera corporation hardcopy iv device handbook, volume 3 requirements when you enable dynamic reconfiguration, the quartus ii software has certain requirements for combining multiple transceiver channels in the same physical transceiver block: all the channels that you want to combine into the same transceiver block must have the same options enabled in the reconfig screen of the altgx megawizard plug-in manager. for example, when you enable the analog controls (vod, pre-emphasis, and manual equalization) option in the reconfig screen of the altgx megawizard plug-in manager for a channel, you need to enable the same option for all the other channels to be combined. all the channels must be controlled by the same altgx_reconfig (dynamic reconfiguration controller) instance. the transceiver channels connected to multiple altgx_reconfig instances cannot be combined into the same physical transceiver block, even if they are configured to the same functional mode and data rate. 1 the preceding two constraints are mandatory to combine transceiver channels into the same transceiver block. f for additional requirements to combine the altgx instances within the same transceiver block or in transceiver blocks on the same side of the device, refer to the configuring multiple protocols and data rates chapter in volume 2 of the stratix iv device handbook . combining a transmitter only instance and receiver only instance consider that you want to combine one receiver only instance and another transmitter only instance in the same transceiver block: the receiver only instance must be controlled by an altgx_reconfig instance for offset cancellation control. because you want to combine the receiver only instance with another transmitter only instance into the same transceiver block, you must control the transmitter only instance using the same altgx_reconfig instance. you must enable the same options in the reconfig screen of the altgx megawizard plug-in manager for both the transmitter only and receiver only instances. 1 there are constraints with the independent transmitter only and independent receiver only configurations. both transmitter and receiver have to go through a reset sequence, even if the transmitter or receiver is reconfigured. merging transceiver channels with channel and cmu pll reconfiguration mode enabled into the same transceiver block the quartus ii software requires the following assignment editor setting for all channels assigned to the same transceiver bank when you enable the channel and cmu pll reconfiguration option. assignment setting: assignment name - gxb tx pll reconfiguration group setting (as shown in figure 2?59 ).
2?142 chapter 2: hardcopy iv gx dynamic reconfiguration combining transceiver channels with dynamic reconfiguration enabled hardcopy iv device handbook, volume 3 ? june 2009 altera corporation if you have more than one channel with the channel and cmu pll reconfiguration option enabled, and if you assign them to different reconfiguration groups without pin assignments for the tx_dataout pins, the quartus ii software automatically assigns these channels to different transceiver blocks. if you use a hardcopy iv gx device with one transceiver block, you cannot compile the design if you assign different tx pll reconfig group values for the channels in your design. to understand this assignment setting, assume that you have two transmit channels in the same transceiver bank with the channel and cmu pll reconfiguration option enabled. if the transmit output pins are tx_dataout_ch0 and tx_dataout_ch1 , set the assignments shown in table 2?40 and table 2?41 to compile the design. merging transceiver channels listening to two transmitter plls consider that you create an altgx instance for a receiver and transmitter or transmitter only configuration that has a main and alternate transmitter pll. if you want to place other channels in the same transceiver bank, the other channels need to also have a main and alternate transmitter pll option to merge successfully. for example, consider that you create the following instances: altgx instance 1: one channel with a receiver and transmitter configuration, with the main transmitter pll (assume a logical tx pll value of 0 ), configured to 6.25 gbps data rate and the alternate transmitter pll configured to 2.500 gbps. figure 2?59. reconfiguration group setting required for channel and cmu pll reconfiguration table 2?40. tx_dataout_ch0 reconfiguration assignment settings assignment setting to: tx_dataout_ch0 assignment name: gxb tx pll reconfiguration group setting value: 0 table 2?41. tx_dataout_ch1 reconfiguration assignment settings assignment setting to: tx_dataout_ch1 assignment name: gxb tx pll reconfiguration group setting value: 0
chapter 2: hardcopy iv gx dynamic reconfiguration 2?143 dynamic reconfiguration duration and core fabric resource utilization ? june 2009 altera corporation hardcopy iv device handbook, volume 3 assume that you create another instance with the following configuration: altgx instance 2: one channel with a receiver and transmitter configuration, with only one transmitter pll (assume a logical tx pll value of 0 ), configured to 6.25 gbps. in this case, you cannot merge altgx instance 1 and altgx instance 2 in the same transceiver bank because altgx instance 2 listens to only one transmitter pll. to successfully merge the two instances, create altgx instance 2 with an alternate transmitter pll configured to 2.500 gbps. merging transceiver channels listening to one transmitter pll consider that you create an altgx instance ( receiver and transmitter or transmitter only configuration) that has only one transmitter pll. if you want to create another altgx instance configured at a different data rate in the same transceiver bank, provide different logical tx pll values for the two instantiations. for example, to merge the following instantiations in the same transceiver bank: altgx instance 1: one channel with a receiver and transmitter configuration, configured at 3.125 gbps data rate. altgx instance 2: one channel with a receiver and transmitter configuration, configured at 2.500 gbps. if you set the what is the main transmitter pll logical reference index? option (in the reconfig clks screen) for altgx instance 1 to 0, set this option to 1 for altgx instance 2. the two altgx instances need to have different logical tx pll values because the quartus ii software requires separate transmitter plls for these two channels. dynamic reconfiguration duration and core fabric resource utilization this section describes the time taken for dynamic reconfiguration transactions and core fabric resources used by the dynamic reconfiguration controller when used in different modes of reconfiguration. dynamic reconfiguration duration dynamic reconfiguration duration is the number of cycles for which the busy signal is asserted when the dynamic reconfiguration controller performs write transactions, read transactions, or offset cancellation of the receiver channels. pma controls reconfiguration duration the following section contains an estimate of the number of reconfig_clk clock cycles for which the busy signal is asserted during pma controls reconfiguration using method 1 and method 2. for more information, refer to ?dynamically reconfiguring pma controls? on page 2?53 .
2?144 chapter 2: hardcopy iv gx dynamic reconfiguration dynamic reconfiguration duration and core fabric resource utilization hardcopy iv device handbook, volume 3 ? june 2009 altera corporation pma controls reconfiguration duration when using method 1 use the logical_channel_address port in method 1. the write transaction and read transaction duration is as follows: write transaction duration for writing values to the following pma controls, the busy signal is asserted for 260 reconfig_clk clock cycles for each of these controls: tx_preemp_1t (pre-emphasis control first post-tap) tx_vodctrl (voltage output differential) rx_eqctrl (equalizer control) rx_eqdcgain (equalizer dc gain) for writing values to the following pma controls, the busy signal is asserted for 520 reconfig_clk clock cycles for each of these controls: tx_preemp_0t (pre-emphasis control pre-tap) tx_preemp_2t (pre-emphasis control second post-tap) read transaction duration for reading the existing values of the following pma controls, the busy signal is asserted for 130 reconfig_clk clock cycles for each of these controls. the data_valid signal is then asserted once the busy signal goes low. tx_preemp_1t_out (pre-emphasis control first post-tap) tx_vodctrl_out (voltage output differential) rx_eqctrl_out (equalizer control) rx_eqdcgain_out (equalizer dc gain) for reading the existing values of the following pma controls, the busy signal is asserted for 260 reconfig_clk clock cycles for each of these controls. the data_valid signal is then asserted once the busy signal goes low. tx_preemp_0t_out (pre-emphasis control pre-tap) tx_preemp_2t_out (pre-emphasis control second post-tap) pma controls reconfiguration duration when using method 2 the logical_channel_address port is not used in method 2. the write transaction duration and read transaction duration are as follows: write transaction duration for writing values to the following pma controls, the busy signal is asserted for 260 reconfig_clk clock cycles per channel for each of these controls: tx_preemp_1t (pre-emphasis control first post-tap) tx_vodctrl (voltage output differential) rx_eqctrl (equalizer control) rx_eqdcgain (equalizer dc gain)
chapter 2: hardcopy iv gx dynamic reconfiguration 2?145 dynamic reconfiguration duration and core fabric resource utilization ? june 2009 altera corporation hardcopy iv device handbook, volume 3 for writing values to the following pma controls, the busy signal is asserted for 520 reconfig_clk clock cycles per channel for each of these controls: tx_preemp_0t (pre-emphasis control pre-tap) tx_preemp_2t (pre-emphasis control second post-tap) read transaction duration for reading the existing values of the following pma controls, the busy signal is asserted for 130 reconfig_clk clock cycles per channel for each of these controls. the data_valid signal is then asserted once the busy signal goes low. tx_preemp_1t_out (pre-emphasis control first post-tap) tx_vodctrl_out (voltage output differential) rx_eqctrl_out (equalizer control) rx_eqdcgain_out (equalizer dc gain) for reading the existing values of the following pma controls, the busy signal is asserted for 260 reconfig_clk clock cycles per channel for each of these controls. the data_valid signal is then asserted once the busy signal goes low. tx_preemp_0t_out (pre-emphasis control pre-tap) tx_preemp_2t_out (pre-emphasis control second post-tap) offset cancellation duration when the device powers up, the busy signal remains low for the first reconfig_clk clock cycle. after the device powers up, it takes 70 reconfig_clk clock cycles for the dynamic reconfiguration controller to identify the receiver channels. when the dynamic reconfiguration controller identifies the receiver channels and verifies the logical channel address to physical channel mapping, it takes another 7872 reconfig_clk clock cycles per receiver channel to perform the offset cancellation process. in other words, the busy signal goes low after 7924 reconfig_clk clock cycles per receiver channel (50 + 2 + 7872). 1 if the design does not require pma controls reconfiguration, each altgx instance in the design can have its own dynamic reconfiguration controller (altgx_reconfig instance). this minimizes offset cancellation duration. dynamic reconfiguration duration for channel and tx pll select/reconfig modes table 2?42 shows the number of reconfig_clk clock cycles it takes for the dynamic reconfiguration controller to reconfigure various parts of the transceiver channel and cmu pll. table 2?42. dynamic reconfiguration duration for transceiver channel and cmu pll reconfiguration (part 1 of 2) transceiver portion under reconfiguration number of reconfig_clk clock cycles transmitter channel reconfiguration 1690 clock cycles receiver channel reconfiguration 5181 clock cycles
2?146 chapter 2: hardcopy iv gx dynamic reconfiguration dynamic reconfiguration duration and core fabric resource utilization hardcopy iv device handbook, volume 3 ? june 2009 altera corporation dynamic reconfiguration (altgx_reconfig instance) resource utilization you can observe the resources utilized during dynamic reconfiguration in the altgx_reconfig megawizard plug-in manager. this section contains an estimate of the logic elements (le) resources utilized during dynamic reconfiguration. you can obtain resource utilization for all other pma controls from the altgx_reconfig megawizard plug-in manager. for example, the number of les used by one dynamic reconfiguration controller is 43 with only tx_vodctrl selected. similarly, the number of registers is 130. figure 2?60 shows the resource utilization in the altgx_reconfig megawizard plug-in manager. transmitter and receiver channel reconfiguration 6861 clock cycles cmu pll only reconfiguration 970 clock cycles transmitter channel and cmu pll reconfiguration 2650 clock cycles transceiver channel and cmu pll reconfiguration 7850 clock cycles table 2?42. dynamic reconfiguration duration for transceiver channel and cmu pll reconfiguration (part 2 of 2) transceiver portion under reconfiguration number of reconfig_clk clock cycles figure 2?60. resource utilization in the altgx_reconfig megawizard plug-in manager
chapter 2: hardcopy iv gx dynamic reconfiguration 2?147 functional simulation of the offset cancellation process ? june 2009 altera corporation hardcopy iv device handbook, volume 3 functional simulation of the offset cancellation process this section contains the points to be considered during the functional simulation of the dynamic reconfiguration process. you must connect the altgx_reconfig instance to the altgx_instance/altgx instances in your design for functional simulation. the functional simulation uses a reduced timing model of the dynamic reconfiguration controller. therefore, the duration of the dynamic reconfiguration process is 16 reconfig_clk clock cycles for functional simulation only. the gxb_powerdown signal must not be asserted during the offset cancellation sequence (for functional simulation and silicon). document revision history table 2?43 shows the revision history for this chapter. table 2?43. document revision history date and document version changes made summary of changes june 2009, v1.0 initial release. ?
2?148 chapter 2: hardcopy iv gx dynamic reconfiguration document revision history hardcopy iv device handbook, volume 3 ? june 2009 altera corporation
? june 2009 altera corporation hardcopy iv device handbook volume 3 3. hardcopy iv gx altgx_reconfig megafunction user guide introduction the megawizard tm plug-in manager in the quartus ? ii software creates or modifies design files that contain custom megafunction variations. these auto-generated megawizard plug-in manager files can then be instantiated in a design file. the megawizard plug-in manager allows you to specify options for the altgx_reconfig megafunction. start the megawizard plug-in manager using one of the following methods: megawizard plug-in manager command. block editor (schematic symbol), open the edit menu and choose insert symbol . the symbol dialog box appears. in the symbol dialog box, click megawizard plug-in manager . qmegawiz. dynamic reconfiguration this section describes the options available on the individual pages of the altgx_reconfig megawizard plug-in manager. 1 r r rv wr f f c r r 1 w fr f r r r c fc vr c create a new custom megafunction variation . click next . figure 3?1. megawizard plug-in manager (page 1) hiv53003-1.0
3?2 chapter 3: hardcopy iv gx altgx_reconfig megafunction user guide dynamic reconfiguration hardcopy iv device handbook volume 3 ? june 2009 altera corporation figure 3?2 shows the second page of the megawizard plug-in manager. select the following options (click next when you are done): 1. in the list of megafunctions on the left, click the ? + ? icon beside the i/o item. from the options presented, choose altgx_reconfig megafunction . 2. from the drop-down menu beside which device family will you be using? , select stratix iv . note that the project target device is stratix iv gx and a hardcopy iv gx companion device must be selected. 3. from the radio buttons under which type of output file do you want to create? , choose your output file format ( ahdl , vhdl , or verilog hdl ). 4. in the box beneath what name do you want for the output file? , enter the file name or click the browse button to search for it. 1 r c ccf w c rcfr crr fr c figure 3?2. megawizard plug-in manager?altgx_reconfig (page 2)
chapter 3: hardcopy iv gx altgx_reconfig megafunction user guide 3?3 dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 3?3 shows page 3 of the altgx_reconfig megawizard plug-in manager. from the drop-down menu, select the number of channels controlled by the dynamic reconfiguration controller. figure 3?3. megawizard plug-in manager?altgx_reconfig (reconfiguration settings) (page 3)
3?4 chapter 3: hardcopy iv gx altgx_reconfig megafunction user guide dynamic reconfiguration hardcopy iv device handbook volume 3 ? june 2009 altera corporation table 3?1 describes the available options on page 3 of the megawizard plug-in manager for your altgx_reconfig custom megafunction variation. select the match project/default option if you want to change the device currently selected device family options. make your selections on page 3, then click next . tab le 3 ?1 . megawizard plug-in manager options (page 3) (part 1 of 2) altgx_reconfig setting description reference what is the number of channels controlled by the reconfig controller? determine the highest logical channel address amongst all the altgx instances connected to the altgx_reconfig instance. round it up to the next multiple of four and set that number in this option. depending on this setting, the altgx_reconfig megawizard plug-in manager generates the appropriate signal width for the interface signal ( reconfig_fromgxb ) between the altgx_reconfig and altgx instances. it also gives the necessary bus width for all the selected physical media attachment (pma) signals. depending on the number of channels set, the resource estimate changes because this is a soft implementation that uses fabric logic resources. the resource estimate is shown in the bottom left of page 3 of the megawizard plug-in manager. ?total number of channels controlled by the altgx_reconfig instance? section of the hardcopy iv gx dynamic reconfiguration chapter in volume 3 of the hardcopy iv device handbook
chapter 3: hardcopy iv gx altgx_reconfig megafunction user guide 3?5 dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 3?4 shows page 4 of the altgx_reconfig megawizard plug-in manager. what are the features to be reconfigured by the reconfig controller? this feature is always enabled by default: offset cancellation for receiver channels ?after the device powers up, the dynamic reconfiguration controller performs offset cancellation on the receiver portion of all the transceiver channels controlled by it. ?offset cancellation? section of the hardcopy iv gx dynamic reconfiguration chapter in volume 3 of the hardcopy iv device handbook this feature are available for selection: analog controls ?allows dynamic reconfiguration of pma controls such as equalization, pre-emphasis, dc gain, and vod. data rate division in tx ?allows dynamic reconfiguration of the transmitter local divider settings to 1,2, or 4. the transmitter channel data rate is reconfigured based on the local divider settings. channel and tx pll select/reconfig ?the following features are available under this option: ? cmu pll reconfiguration ?allows the dynamic reconfiguration of the cmu pll to a different data rate. ? channel and cmu pll reconfiguration ?allows the dynamic reconfiguration of the transceiver channel from one functional mode to another and also the reconfiguration of the cmu pll. ? channel reconfiguration with tx pll select ? allows you to select another transmitter pll for the transceiver channel and reconfigure the channel to another data rate. ?pma controls reconfiguration? section of the hardcopy iv gx dynamic reconfiguration chapter in volume 3 of the hardcopy iv device handbook ?cmu pll reconfiguration mode? section of the hardcopy iv gx dynamic reconfiguration chapter in volume 3 of the hardcopy iv device handbook ?channel and cmu pll reconfiguration mode? section of the hardcopy iv gx dynamic reconfiguration chapter in volume 3 of the hardcopy iv device handbook ?cmu pll reconfiguration mode? section of the hardcopy iv gx dynamic reconfiguration chapter in volume 3 of the hardcopy iv device handbook tab le 3 ?1 . megawizard plug-in manager options (page 3) (part 2 of 2) altgx_reconfig setting description reference
3?6 chapter 3: hardcopy iv gx altgx_reconfig megafunction user guide dynamic reconfiguration hardcopy iv device handbook volume 3 ? june 2009 altera corporation figure 3?4. megawizard plug-in manager?altgx_reconfig (analog controls) (page 4)
chapter 3: hardcopy iv gx altgx_reconfig megafunction user guide 3?7 dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook volume 3 table 3?2 describes the available options on page 4 of the megawizard plug-in manager for your altgx_reconfig custom megafunction variation. make your selections on page 4, then click next . tab le 3 ?2 . megawizard plug-in manager options (page 4) (part 1 of 2) altgx_reconfig setting description reference use ? logical_channel_ address ? port for analog controls reconfiguration this option is applicable only for analog controls reconfiguration and is available for selection when the number of channels controlled by the altgx_reconfig instance is more than one. the dynamic reconfiguration controller reconfigures only the channel whose logical channel address is specified at the logical_channel_address port. the width of this port is selected by the altgx_reconfig megawizard plug-in manager depending on the number of channels controlled by the dynamic reconfiguration controller. the maximum width of the logical_channel_address port is 9 bits. ?dynamically reconfiguring pma controls? section of the hardcopy iv gx dynamic reconfiguration chapter in volume 3 of the hardcopy iv device handbook use the same control signal for all channels this option is available for selection when the number of channels controlled by the altgx_reconfig instance is more than one. the dynamic reconfiguration controller writes the same control signals to all the channels connected to it when you enable this option. this option is not available for selection when you enable the use 'logical_channel_address' port for analog controls reconfiguration option.
3?8 chapter 3: hardcopy iv gx altgx_reconfig megafunction user guide dynamic reconfiguration hardcopy iv device handbook volume 3 ? june 2009 altera corporation write control the pma control ports available to write various analog settings to the transceiver channels controlled by the dynamic reconfiguration controller are as follows:  tx_vodctrl ?voltage output differential (v od ) ? 3 bits per channel  tx_preemp_0t ?pre-emphasis control pre-tap ? 5 bits per channel  tx_preemp_1t ?pre-emphasis control 1st post-tap?5 bits per channel  tx_preemp_2t ?pre-emphasis control 2nd post-tap?5 bits per channel  rx_eqdcgain ?equalizer dc gain?3 bits per channel  rx_eqctrl ?equalizer control?4 bits per channel these are optional signals. the signal widths are based on the setting you entered for the what is the number of channels controlled by the reconfig controller? option and whether you enable the use 'logical_channel_address' port for analog controls reconfiguration option. at least one of these pma control ports must be enabled to configure and use the dynamic reconfiguration controller. ?dynamically reconfiguring pma controls? section of the hardcopy iv gx dynamic reconfiguration chapter in volume 3 of the hardcopy iv device handbook read control the pma control ports available to read the existing values from the transceiver channels controlled by the dynamic reconfiguration controller are as follows:  tx_vodctrl_out ?v od )?3 bits per channel  tx_preemp_0t_out ?pre-emphasis control pre-tap?5 bits per channel  tx_preemp1t_out ?pre-emphasis control 1st post-tap?5 bits per channel  tx_preemp_2t_out ?pre-emphasis control 2nd post-tap?5 bits per channel  rx_eqdcgain_out ?equalizer dc gain?3 bits per channel  rx_eqctrl_out ?equalizer control?4 bits per channel these are optional signals. the signal widths are based on the setting you entered for the what is the number of channels controlled by the reconfig controller? option and whether you enable the use 'logical_channel_address' port for analog controls reconfiguration option. the pma controls are available for selection only if the corresponding write control is selected. read and write transactions cannot be performed simultaneously. tab le 3 ?2 . megawizard plug-in manager options (page 4) (part 2 of 2) altgx_reconfig setting description reference
chapter 3: hardcopy iv gx altgx_reconfig megafunction user guide 3?9 dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 3?5 shows page 5 of the altgx_reconfig megawizard plug-in manager. table 3?3 describes the available options on page 5 of the megawizard plug-in manager for your altgx_reconfig custom megafunction variation. figure 3?5. megawizard plug-in manager?altgx_reconfig (analog controls) tab le 3 ?3 . megawizard plug-in manager options (page 5) (part 1 of 2) altgx_reconfig setting description reference use ?reconfig_address_out? this option is enabled by default when you select the channel and tx pll select/reconfig option. the value on reconfig_address_out[5:0] indicates the address associated with the words in the .mif , which contains the dynamic reconfiguration instructions. the dynamic reconfiguration controller automatically increments the address at the end of each .mif write transaction. ?dynamic reconfiguration controller port list? section in the hardcopy iv gx dynamic reconfiguration chapter in volume 3 of the hardcopy iv device handbook use ?reconfig_address_en? when high, this optional output status signal indicates that the address to be used in the .mif write transaction cycle has changed. this signal gets asserted when the .mif write transaction is completed (the busy signal de-asserted). ?dynamic reconfiguration controller port list? section in the hardcopy iv gx dynamic reconfiguration chapter in volume 3 of the hardcopy iv device handbook use ?reset_reconfig_address? when asserted, this optional control signal resets the reconfig_address_out (current reconfiguration address) to 0. ?dynamic reconfiguration controller port list? section in the hardcopy iv gx dynamic reconfiguration chapter in volume 3 of the hardcopy iv device handbook
3?10 chapter 3: hardcopy iv gx altgx_reconfig megafunction user guide dynamic reconfiguration hardcopy iv device handbook volume 3 ? june 2009 altera corporation figure 3?6 shows page 6 of the altgx_reconfig megawizard plug-in manager. use ?logical_tx_pll_sel? this is an optional control signal. the logical_tx_pll_sel[1:0] signal refers to the logical reference index of the cmu pll. the functionality of the signal depends on the feature activated, as shown below: cmu pll reconfiguration ?the corresponding cmu pll is reconfigured based on the value at logical_tx_pll_sel[1:0] . channel and cmu pll reconfiguration ?the corresponding cmu pll is reconfigured based on the value at this signal. the transceiver channel listens to the cmu pll selected by logical_tx_pll_sel[1:0] . channel reconfiguration with tx pll select ?the transceiver channel listens to the tx pll selected by logical_tx_pll_sel[1:0] . ?the logical_tx_pll_sel and logical_tx_pll_sel_en ports? section in the hardcopy iv gx dynamic reconfiguration chapter in volume 3 of the hardcopy iv device handbook use ?logical_tx_pll_sel_en? this is an optional control signal. when you enable this signal, the value set on the logical_tx_pll_sel[1:0] signal is valid only if logical_tx_pll_sel_en is set to 1 . ?the logical_tx_pll_sel and logical_tx_pll_sel_en ports? section in the hardcopy iv gx dynamic reconfiguration chapter in volume 3 of the hardcopy iv device handbook tab le 3 ?3 . megawizard plug-in manager options (page 5) (part 2 of 2) altgx_reconfig setting description reference figure 3?6. megawizard plug-in manager?altgx_reconfig (error checks/data rate switch)
chapter 3: hardcopy iv gx altgx_reconfig megafunction user guide 3?11 dynamic reconfiguration ? june 2009 altera corporation hardcopy iv device handbook volume 3 table 3?4 describes the available options on page 6 of the megawizard plug-in manager for your altgx_reconfig custom megafunction variation. make your selections on page 6, then click next . tab le 3 ?4 . megawizard plug-in manager options (page 6) altgx_reconfig setting description reference enable illegal mode checking when you select this option, the altgx_reconfig megawizard plug-in manager provides the error output port. the dynamic reconfiguration controller checks for specific unsupported options within two reconfig_clk cycles, de-asserts the busy signal and asserts the error output port for two reconfig_clk cycles. the dynamic reconfiguration controller does not execute the unsupported operation. ?error indication in the altgx_reconfig megawizard plug-in manager? section of the hardcopy iv gx dynamic reconfiguration chapter in volume 3 of the hardcopy iv device handbook enable self recovery when you select this option, the altgx_reconfig megawizard plug-in manager provides the error output port. the dynamic reconfiguration controller quits an operation if it did not complete within the expected number of clock cycles. after recovering from the illegal operation, the dynamic reconfiguration controller de-asserts the busy signal and asserts the error output port for two reconfig_clk cycles. ?error indication in the altgx_reconfig megawizard plug-in manager? section of the hardcopy iv gx dynamic reconfiguration chapter in volume 3 of the hardcopy iv device handbook use rate_switch_out port to read out the current data rate division the rate_switch_out[1:0] signal is available when you select data rate division in tx mode. you can read the existing local divider settings of a transmitter channel at this port. the decoding for this signal is listed below: 2?b00?division of 1 2?b01?division of 2 2?b10?division of 4 2?b11?not supported ?data rate division in tx mode? section in the hardcopy iv gx dynamic reconfiguration chapter in volume 3 of the hardcopy iv device handbook use the rx_tx_duplex_sel port to enable rx only, tx only or duplex configuration. you can read or write the receiver and transmitter settings, or only the receiver settings, or only the transmitter settings, based on the value you set at the rx_tx_duplex_sel[1:0] port. 2?b00?duplex mode 2?b01?rx only mode 2?b10?tx only mode 2?b11?unsupported value (do not use this value) if you disable the rx_tx_duplex_sel[1:0] port, the dynamic reconfiguration controller will read or write both the receiver and transmitter settings. ?dynamically reconfiguring pma controls? section of the hardcopy iv gx dynamic reconfiguration chapter in volume 3 of the hardcopy iv device handbook
3?12 chapter 3: hardcopy iv gx altgx_reconfig megafunction user guide dynamic reconfiguration hardcopy iv device handbook volume 3 ? june 2009 altera corporation figure 3?7 shows page 7 (the simulation libraries page) of the megawizard plug-in manager, which is used for dynamic reconfiguration selection. make your selections, then click next . table 3?5 describes the available option on page 7 of the megawizard plug-in manager for your altgx_reconfig custom megafunction variation. make your selections on page 6, then click next . figure 3?7. megawizard plug-in manager?altgx_reconfig (simulation libraries) tab le 3 ?5 . megawizard plug-in manager options (page 7) altgx_reconfig setting description generate a netlist for synthesis area and timing estimation selecting this option generates a netlist file that third-party synthesis tools use to estimate timing and resource usage
chapter 3: hardcopy iv gx altgx_reconfig megafunction user guide 3?13 document revision history ? june 2009 altera corporation hardcopy iv device handbook volume 3 figure 3?8 shows page 7 (the last page) of the megawizard plug-in manager for the dynamic reconfiguration protocol set up. you can select optional files on this page. after you make your selections, click finish to generate the files. document revision history table 3?6 shows the revision history for this chapter. figure 3?8. megawizard plug-in manager?altgx_reconfig (summary) tab le 3 ?6 . document revision history date and document version changes made summary of changes june 2009, v1.0 initial release. ?
3?14 chapter 3: hardcopy iv gx altgx_reconfig megafunction user guide document revision history hardcopy iv device handbook volume 3 ? june 2009 altera corporation
? june 2009 altera corporation hardcopy iv device handbook, volume 3 additional information about this handbook this handbook provides comprehensive information about the altera ? hardcopy ? iv family of devices. how to contact altera for the most up-to-date information about altera products, see the following table. typographic conventions the following table shows the typographic conventions that this document uses. contact (note 1) contact method address technical support website www.altera.com/support technical training website www.altera.com/training email custrain@altera.com product literature website www.altera.com/literature non-technical support (general) email nacomp@altera.com (software licensing) email authorization@altera.com note: (1) you can also contact your local altera sales office or sales representative. visual cue meaning bold type with initial capital letters indicates command names, dialog box titles, dialog box options, and other gui labels. for example, save as dialog box. for gui elements, capitalization matches the gui. bold type indicates directory names, project names, disk drive names, file names, file name extensions, dialog box options, software utility names, and other gui labels. for example, \qdesigns directory, d: drive, and chiptrip.gdf file. italic type with initial capital letters indicates document titles. for example, an 519: stratix iv design guidelines. italic type indicates variables. for example, n + 1. variable names are enclosed in angle brackets (< >). for example, and .pof file. initial capital letters indicates keyboard keys and menu names. for example, delete key and the options menu. ?subheading title? quotation marks indicate references to sections within a document and titles of quartus ii help topics. for example, ?typographic conventions.?
info?2 additional information hardcopy iv device handbook, volume 3 ? june 2009 altera corporation courier type indicates signal, port, register, bit, block, and primitive names. for example, data1 , tdi , and input . active-low signals are denoted by suffix n . for example, resetn . indicates command line commands and anything that must be typed exactly as it appears. for example, c:\qdesigns\tutorial\chiptrip.gdf . also indicates sections of an actual file, such as a report file, references to parts of files (for example, the ahdl keyword subdesign ), and logic function names (for example, tri ). 1., 2., 3., and a., b., c., and so on. numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. bullets indicate a list of items when the sequence of the items is not important. 1 the hand points to information that requires special attention. c a caution calls attention to a condition or possible situation that can damage or destroy the product or your work. w a warning calls attention to a condition or possible situation that can cause you injury. r the angled arrow instructs you to press enter . f the feet direct you to more information about a particular topic. visual cue meaning
101 innovation drive san jose, ca 95134 www.altera.com hardcopy iv device handbook, volume 4 hc4_h5v4-1.0
copyright ? 2009 altera corporation. all rights reserved. altera, the programmable solutions company, the stylized altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of altera corporation in the u.s. and other countries. all other product or service names are the property of their respective holders. altera products are protected under numerous u.s. and foreign patents and pending ap- plications, maskwork rights, and copyrights. altera warrants performance of its semiconductor products to current specification s in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibilit y or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera corporation. altera cu stomers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services .
? june 2009 altera corporation hardcopy iv device handbook, volume 4 contents chapter revision dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v section i. hardcopy iv device datasheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i-1 chapter 1. dc and switching characteristics of hardcopy iv devices electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 i/o standard specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 transceiver performance specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 core performance specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 clock tree specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 pll specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 dsp block specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 trimatrix memory block specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 jtag specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 periphery performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 high-speed i/o specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 external memory interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 oct calibration block specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 duty cycle distortion (dcd) specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 i/o timing model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36 additional information about this handbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info-1 how to contact altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info-1 typographic conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info-1
iv contents hardcopy iv device handbook, volume 4 ? june 2009 altera corporation
? june 2009 altera corporation hardcopy iv device handbook, volume 4 chapter revision dates the chapter in this book, hardcopy iv device handbook, volume 4 , was revised on the following date. where chapters or groups of chapters are available separately, part numbers are listed. chapter 1 dc and switching characteristics of hardcopy iv devices revised: june 2009 part number: hiv54001-1.0
vi chapter revision dates hardcopy iv device handbook, volume 4 ? june 2009 altera corporation
? june 2009 altera corporation hardcopy iv device handbook, volume 4 section i. hardcopy iv device datasheet this section provides the datasheet for the hardcopy ? iv device family. this section includes the following chapter: chapter 1, dc and switching characteristics of hardcopy iv devices revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook.
i?2 section i: hardcopy iv device datasheet hardcopy iv device handbook, volume 4 ? june 2009 altera corporation
? june 2009 altera corporation hardcopy iv device handbook volume 4 1. dc and switching characteristics of hardcopy iv devices electrical characteristics this chapter covers the electrical characteristics for hardcopy ? iv devices. operating conditions when hardcopy iv devices are implemented in a system, they are rated according to a set of defined parameters. to maintain the highest possible performance and reliability, consider the operating requirements described in this chapter. hardcopy iv devices are not speed binned like stratix ? iv devices because hardcopy iv devices are designed and built to function at a target frequency based on timing constraints. hardcopy iv devices are offered in both commercial and industrial grades. absolute maximum ratings absolute maximum ratings define the maximum operating conditions for hardcopy iv devices. the values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. the functional operation of the device is not implied for these conditions. 1 conditions other than those listed in table 1?1 and table 1?3 may cause permanent damage to the device. additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device. tab le 1 ?1 . hardcopy iv device absolute maximum ratings?preliminary (part 1 of 2) (note 1) symbol description minimum maximum unit v cc core voltage and periphery circuitry power supply -0.5 1.35 v v ccpt (2) power supply for programmable power technology ??v v ccpgm configuration pins power supply -0.5 3.75 v v ccaux power supply for temperature sensing diode and por -0.5 3.75 v v ccbat (3) battery back-up power supply for design security volatile key register ??v v ccpd i/o pre-driver power supply -0.5 3.75 v v ccio i/o power supply -0.5 3.9 v v cc_clkin differential clock input power supply -0.5 3.75 v v ccd_pll pll digital power supply -0.5 1.35 v v cca_pll pll analog power supply -0.5 3.75 v v i dc input voltage -0.5 4.0 v i out dc output current per pin -25 40 ma t j operating junction temperature -55 125 c hiv54001-1.0
1?2 chapter 1: dc and switching characteristics of hardcopy iv devices electrical characteristics hardcopy iv device handbook volume 4 ? june 2009 altera corporation table 1?2 hardcopy iv gx transceiver power supply absolute maximum ratings. maximum allowed overshoot/undershoot voltage during transitions, input signals may overshoot to the voltage shown in table 1?3 and undershoot to -2.0 v for input currents less than 100 ma and periods shorter than 20 ns. table 1?3 lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime. the maximum allowed overshoot duration is specified as a percentage of high-time over the lifetime of the device. a dc signal is equivalent to 100% duty cycle. t stg storage temperature (no bias) -65 150 c notes for ta bl e 1? 1 : (1) supply voltage specifications apply to voltage readi ngs taken at the device pins and not the power supply. (2) hardcopy iv devices do not require programmable power technology. (3) this power supply is not used in hardcopy iv devices. tab le 1 ?1 . hardcopy iv device absolute maximum ratings?preliminary (part 2 of 2) (note 1) symbol description minimum maximum unit tab le 1 ?2 . hardcopy iv gx transceiver power supply absolute maximum ratings symbol description minimum maximum unit v cca_l transceiver high voltage power (left side) -0.5 3.75 v v cca_r transceiver high voltage power (right side) -0.5 3.75 v v cchip_l transceiver hard ip digital power (right side) -0.5 1.35 v v cchip_r transceiver hard ip digital power (left side) -0.5 1.35 v v ccr_l receiver power (left side) -0.5 1.35 v v ccr_r receiver power (right side) -0.5 1.35 v v cct_l transmitter power (left side) -0.5 1.35 v v cct_r transmitter power (right side) -0.5 1.35 v v ccl_gxbln (1) transceiver clock power (left side) -0.5 1.35 v v ccl_gxbrn (1) transceiver clock power (right side) -0.5 1.35 v v cch_gxbln (1) transmitter output buffer power (left side) -0.5 1.65 v v cch_gxbrn (1) transmitter output buffer power (right side) -0.5 1.65 v notes to ta bl e 1? 2 : (1) the v cch and v ccl powers are per transceiver block.
chapter 1: dc and switching characteristics of hardcopy iv devices 1?3 electrical characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 figure 1?1 shows the methodology to determine overshoot duration. the overshoot voltage is displayed in red and is present at the hardcopy iv pin, up to 4.1 v. in table 1?3 , for an overshoot of up to 4.1 v, the percentage of high time for overshoot is greater than 3.15 v can be as high as 46% over an 11.4 year period. the percentage of high time is calculated as ( t/t) 100. this 11.4 year period assumes the device is always turned on with 100% i/o toggle rate and 50% duty cycle signal. for lower i/o toggle rates and situations where the device is in an idle state, lifetimes are increased. tab le 1 ?3 . maximum allowed overshoot during transitions?preliminary symbol description condition overshoot duration as percentage of high time unit vi (ac) ac input voltage 4.0 v 100.000 % 4.05 v 79.330 % 4.1 v 46.270 % 4.15 v 27.030 % 4.2 v 15.800 % 4.25 v 9.240 % 4.3 v 5.410 % 4.35 v 3.160 % 4.4 v 1.850 % 4.45 v 1.080 % 4.5 v 0.630 % 4.55 v 0.370 % 4.6 v 0.220 % 4.65 v 0.130 % 4.7 v 0.074 % 4.75 v 0.043 % 4.8 v 0.025 % 4.85 v 0.015 % figure 1?1. overshoot duration 3.0 v 3.15 v 4.1 v t t
chapter 1: dc and switching characteristics of hardcopy iv devices 1?4 electrical characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 recommended operating conditions this section lists the functional operation limits for ac and dc parameters for hardcopy iv devices. table 1?4 shows the steady-state voltage and current values expected from hardcopy iv devices. all supplies are required to monotonically reach their full-rail values within t ramp maximum. allowed ripple on power supplies is bounded by the minimum and maximum specifications listed in table 1?4 . tab le 1 ?4 . hardcopy iv device recommended operating conditions?preliminary (part 1 of 2) symbol description condition minimum typical maximum unit v cc core voltage and periphery circuitry power supply ? 0.870.900.93v v ccpt (1) power supply for programmable power technology ????v v ccaux power supply for the temperature sensing diode and por ? 2.375 2.5 2.625 v v ccpd i/o pre-driver (3.0 v) power supply ? 2.85 3 3.15 v i/o pre-driver (2.5 v) power supply ? 2.375 2.5 2.625 v v ccio i/o buffers (3.0-v) power supply ? 2.85 3 3.15 v i/o buffers (2.5-v) power supply ? 2.375 2.5 2.625 v i/o buffers (1.8-v) power supply ? 1.71 1.8 1.89 v i/o buffers (1.5-v) power supply ? 1.425 1.5 1.575 v i/o buffers (1.2-v) power supply ? 1.14 1.2 1.26 v v ccpgm configuration pins (3.0-v) power supply ? 2.85 3 3.15 v configuration pins (2.5-v) power supply ? 2.375 2.5 2.625 v configuration pins (1.8-v) power supply ? 1.71 1.8 1.89 v v cca_pll pll analog voltage regulator power supply ? 2.375 2.5 2.625 v v ccd_pll pll digital voltage regulator power supply ? 0.87 0.90 0.93 v v cc_clkin differential clock input power supply ? 1.075 1.2 1.325 v differential clock input power supply ? 1.375 1.5 1.625 v differential clock input power supply ? 1.675 1.8 1.925 v differential clock input power supply ? 2.375 2.5 2.625 v differential clock input power supply ? 2.875 3.0 3.125 v v ccbat (2) battery back-up power supply (for design security volatile key register) ????v v i dc input voltage ? ?0.5 ? 3.6 v v o output voltage ? 0 ? v ccio v t j operating junction temperature commercial 0 ? 85 c industrial ?40 ? 100 c
chapter 1: dc and switching characteristics of hardcopy iv devices 1?5 electrical characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 table 1?5 shows the transceiver power supply recommended operating conditions. dc characteristics this section lists the supply current, i/o pin leakage current, input pin capacitance, on-chip termination (oct) tolerance, and hot socketing specifications. supply current standby current is the current the device draws after the device is configured, with no inputs or outputs toggling and no activity in the device. because these currents vary largely with the resources you use, use the excel-based powerplay early power estimator (epe) to get supply current estimates for your design. t ramp power supply ramp time normal por (porsel = 1) 0.05 ? 100 ms fast por (porsel = 1) (3) 0.05 ? 4 ms notes to ta bl e 1? 4 : (1) hardcopy iv devices do not require programmable power technology. (2) in hardcopy iv devices, this power supply is not used. (3) if the porsel pin is connected to v cc , all supplies must ramp up within 4 ms. tab le 1 ?4 . hardcopy iv device recommended operating conditions?preliminary (part 2 of 2) symbol description condition minimum typical maximum unit tab le 1 ?5 . hardcopy iv gx transceiver power supply recommended operating conditions symbol description minimum typical maximum unit v cca_l transceiver high voltage power (left side) 2.85/2.375 3.0/2.5 (3) 3.15/2.625 v v cca_r transceiver high voltage power (right side) v v cchip_l (1) transceiver hard ip digital power (right side) 0.87 0.90 0.93 v v cchip_r (1) transceiver hard ip digital power (left side) v v ccr_l receiver power (left side) 1.05 1.1 1.15 v v ccr_r receiver power (right side) v v cct_l transmitter power (left side) 1.05 1.1 1.15 v v cct_r transmitter power (right side) v v ccl_gxbln (2) transceiver clock power (left side) 1.05 1.1 2.35 v v ccl_gxbrn (2) transceiver clock power (right side) v v cch_gxbln (2) transmitter output buffer power (left side) 1.33/1.425 1.4/1.5 (4) 1.47/1.575 v v cch_gxbrn (2) transmitter output buffer power (right side) v notes to ta bl e 1? 5 : (1) if v cchip_l/r is connected to the same power supply source as vcc, the recommended minimum and maximum operating supply levels are 0.87 v and 0.93 v respectively. (2) the v cch and v ccl powers are per transceiver block (3) v cca_l/r must be connected to a 3.0 v supply if the cmu pll, receiver cdr, or both are configured at a base data rate > 4.25gbps. for d ata rates up to 4.25 gbps, you can connect v cca_l/r to either 3.0 v or 2.5 v. (4) for data rates up to 6.5 gbps, you can connect v cch_gxbl/r to either 1.4 v or 1.5 v.
chapter 1: dc and switching characteristics of hardcopy iv devices 1?6 electrical characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 table 1?6 lists supply current specifications for v cc_clkin and v ccpgm . use the powerplay epe to get supply current estimates for the remaining power supplies. i/o pin leakage current table 1?7 defines the hardcopy iv i/o pin leakage current specifications. oct specifications if oct calibration is enabled, calibration is automatically performed at power up for i/os connected to the calibration block. table 1?8 lists the hardcopy iv oct calibration block accuracy specifications. tab le 1 ?6 . supply current specifications for v cc_clkin and v ccpgm ?preliminary (note 1) symbol parameter min max unit i clkin v cc_clkin current specifications 0 tbd ma i pgm v ccpgm current specifications 0 tbd ma note to tab l e 1 ?6 : (1) pending silicon characterization. tab le 1 ?7 . hardcopy iv i/o pin leakage current?preliminary (note 1) , (2) symbol description conditions min typ max unit i i input pin v i = 0v to v cc iom ax -10 ? 10 a i oz tri-stated i/o pin v o = 0v to v cc ioma x -10 ? 10 a notes to ta bl e 1? 7 : (1) this value is specified for normal device operation. the value may vary during power up. this applies for all v ccio settings (3.0, 2.5, 1.8, 1.5, and 1.2 v). (2) the 10 ma i/o leakage current limit is applicable when the internal clamping diode is off. a higher current is observed when the diode is on. tab le 1 ?8 . hardcopy iv oct with calibration specification for i/os?preliminary (note 1) symbol description conditions calibration accuracy unit commercial (2) industry 25- r s 3.0/2.5 internal series termination with calibration (25- setting) v cc io = 3.0/2.5 v tbd ? % 50- r s 3.0/2.5 internal series termination with calibration (50- setting) v cc io = 3.0/2.5 v tbd ? % 50- r t 2.5 internal series termination with calibration (50- setting) v ccio = 2.5 v tbd ? % 25- r s 1.8 internal series termination with calibration (25- setting) v ccio = 1.8 v tbd ? % 50- r s 1.8 internal series termination with calibration (50- setting) v ccio = 1.8 v tbd ? % 50- r t 1.8 internal series termination with calibration (50- setting) v ccio = 1.8 v tbd ? % 50- r s 1.5 internal series termination with calibration (50- setting) v ccio = 1.5 v tbd ? % 50- r t 1.5 internal series termination with calibration (50- setting) v ccio = 1.5 v tbd ? % 50- r s 1.2 internal series termination with calibration (50- setting) v ccio = 1.2 v tbd ? % 50- r t 1.2 internal series termination with calibration (50- setting) v ccio = 1.2 v tbd ? % notes to ta bl e 1? 8 : (1) oct calibration accuracy is valid at the time of calibration only. (2) pending silicon characterization.
chapter 1: dc and switching characteristics of hardcopy iv devices 1?7 electrical characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 the calibration accuracy for calibrated series and parallel octs are applicable at the moment of calibration. if the voltage or temperature changes, the termination resistance value varies. table 1?9 lists the resistance tolerance for hardcopy iv oct. table 1?10 lists oct variation with temperature and voltage after power-up calibration. use table 1?10 and equation 1?1 to determine the oct variation when voltage and temperature vary after power-up calibration. tab le 1 ?9 . i/o oct resistance tolerance?preliminary (note 1) symbol description resistance tolerance commercial max industrial max unit r oc t_cal internal series/parallel oct with calibration (2) ?% r oct_uncal internal series/parallel oct without calibration tbd ? % notes to ta bl e 1? 9 : (1) pending silicon characterization. (2) for resistance tolerance after power-up calibration, refer to table 1?10 . equation 1?1. oct variation without re-calibration (note 1) note to equation 1?1 : (1) r cal is calibrated oct at power up. t and v are variations in temperature and voltage with respect to temperature and v ccio values, respectively, at power up. table 1?10. oct variation after power-up calibration?preliminary (note 1) , (2) symbol description v ccio (v) commercial typical unit dr/dv oct variation with voltage without re-calibration 3.0 tbd %/mv 2.5 tbd 1.8 tbd 1.5 tbd 1.2 tbd dr/dt oct variation with temperature without re-calibration 3.0 tbd %/c 2.5 tbd 1.8 tbd 1.5 tbd 1.2 tbd notes to ta bl e 1? 10 : (1) valid for v ccio range of 5% and a temperature range of 0 to 85c. (2) pending silicon characterization. r oct r cal 1 dr dt ------ - t dr dv ------ - v + + ?? ?? =
chapter 1: dc and switching characteristics of hardcopy iv devices 1?8 electrical characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 pin capacitance table 1?11 shows the hardcopy iv device family pin capacitance. hot socketing table 1?12 defines the hot socketing specification for hardcopy iv devices. internal weak pull-up resistor table 1?13 lists the weak pull-up resistor values for hardcopy iv devices. table 1?11. hardcopy iv device capacitance?preliminary (note 1) symbol description typical unit c iotb input capacitance on top/bottom i/o pins tbd pf c iolr input capacitance on left/right i/o pins tbd pf c clktb input capacitance on top/bottom dedicated clock input pins tbd pf c clklr input capacitance on left/right dedicated clock input pins tbd pf c outfb input capacitance on dual-purpose clock output/feedback pins tbd pf c clk1 c clk3 c clk8 c clk10 input capacitance for dedicated clock input pins tbd pf note to tab l e 1 ?1 1 : (1) pending silicon characterization. table 1?12. hardcopy iv hot socketing specifications?preliminary (note 1) symbol description maximum i iiopin(dc) dc current per i/o pin 300 a i iopin(ac) ac current per i/o pin 8 ma for t rise > 10 ns note to tab l e 1 ?1 2 : (1) pending silicon characterization. table 1?13. hardcopy iv internal weak pull-up resistor?preliminary (note 1) , (2) symbol parameter conditions min typ max unit r pu the value of i/o pin pull-up resistor before and during user mode, if the pull-up resistor option is enabled. v ccio = 3.0 v 5% (3) ?25 ? k v ccio = 2.5 v 5% (3) ?25 ? k v ccio = 1.8 v 5% (3) ?25 ? k v ccio = 1.5 v 5% (3) ?25 ? k v ccio = 1.2 v 5% (3) ?25 ? k notes to ta bl e 1? 13 : (1) pending silicon characterization. (2) all i/o pins have an option to enable weak pull-up except test and jtag pins. (3) pin pull-up resistance values may be lower if an external source drives the pin higher than v ccio .
chapter 1: dc and switching characteristics of hardcopy iv devices 1?9 electrical characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 i/o standard specifications table 1?14 through table 1?19 list input voltage (v ih and v il ), output voltage (v oh and v ol ), and current drive characteristics (i oh and i ol ) for various i/o standards supported by hardcopy iv devices. these tables also show the hardcopy iv device family i/o standard specifications. refer to the ?glossary? on page 1?32 for an explanation of terms used in table 1?14 through table 1?19 . v ol and v oh values are valid at the corresponding i oh and i ol , respectively. refer to ?single-ended voltage referenced i/o standard? in table 1?39 on page 1?32 for an example of a voltage referenced receiver input waveform and explanation of terms used in table 1?15 . table 1?14. single-ended i/o standards?preliminary i/o standard v ccio (v) v il (v) v ih (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min typ max min max min max max min 3.0-v lvttl 2.85 3 3.15 -0.3 0.8 1.7 3.6 0.4 2.4 2 -2 3.0-v lvcmos 2.85 3 3.15 -0.3 0.8 1.7 3.6 0.2 v ccio - 0.2 0.1 -0.1 2.5-v lvttl/lvcmos 2.375 2.5 2.625 -0.3 0.7 1.7 3.6 0.2 2.1 0.1 -0.1 0.4 2 1 -1 0.7 1.7 2 -2 1.8-v lvttl/lvcmos 1.71 1.8 1.89 -0.3 0.35 * v ccio 0.65 * v ccio v ccio + 0.3 0.45 v ccio -0.45 2-2 1.5-v lvttl/lvcmos 1.425 1.5 1.575 -0.3 0.35 * v ccio 0.65 * v ccio v ccio + 0.3 0.25 * v ccio 0.75 * v ccio 2-2 1.2-v lvttl/lvcmos 1.14 1.2 1.26 -0.3 0.35 * v ccio 0.65 * v ccio v ccio + 0.3 0.25 * v ccio 0.75 * v ccio 2-2 3.0-v pci 2.85 3 3.15 ? 0.3 * v ccio 0.5 * v ccio 3.6 0.1 * v ccio 0.9 * v ccio 1.5 -0.5 3.0-v pci-x 2.85 3 3.15 ? 0.35 * v ccio 0.5 * v ccio ? 0.1 * v ccio 0.9 * v ccio 1.5 -0.5 table 1?15. single-ended sstl and hstl i/o reference voltage specifications?preliminary i/o standard v ccio (v) v ref (v) v tt (v) min typ max min typ max min typ max sstl-2 class i, ii 2.375 2.5 2.625 0.49 * v ccio 0.5 * v ccio 0.51 * v ccio v ref - 0.04 v ref v ref + 0.04 sstl-18 class i, ii 1.71 1.8 1.89 0.49 * v ccio 0.5 * v ccio 0.51 * v ccio v ref - 0.04 v ref v ref + 0.04 sstl-15 class i, ii 1.425 1.5 1.575 0.49 * v ccio 0.5 * v ccio 0.51 * v ccio v ref - 0.04 v ref v ref + 0.04 hstl-18 class i, ii 1.71 1.8 1.89 0.85 0.9 0.95 ? v ccio /2 ? hstl-15 class i, ii 1.425 1.5 1.575 0.68 0.75 0.9 ? v ccio /2 ? hstl-12 class i, ii 1.14 1.2 1.26 0.48 * v ccio 0.5 * v ccio 0.52 * v ccio ? v ccio /2 ? table 1?16. single-ended sstl and hstl i/o standards signal specifications?preliminary (part 1 of 2) i/o standard v il(dc) (v) v ih(dc) (v) v il(ac) (v) v ih(ac) (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min max min max max min max min sstl-2 class i -0.3 v ref - 0.15 v ref + 0.15 v ccio + 0.3 v re f - 0.31 v ref + 0.31 v tt - 0.57 v tt + 0.57 8.1 -8.1 sstl-2 class ii -0.3 v ref - 0.15 v ref + 0.15 v ccio + 0.3 v re f - 0.31 v ref + 0.31 v tt - 0.76 v tt + 0.76 16.2 -16.2 sstl-18 class i -0.3 v ref - 0.125 v re f + 0.125 v ccio + 0.3 v re f - 0.25 v ref + 0.25 v tt - 0.475 v tt + 0.475 6.7 -6.7 sstl-18 class ii -0.3 v ref - 0.125 v re f + 0.125 v ccio + 0.3 v re f - 0.25 v ref + 0.25 0.28 v ccio - 0.28 13.4 -13.4
chapter 1: dc and switching characteristics of hardcopy iv devices 1?10 electrical characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 refer to ?differential i/o standards? in table 1?39 on page 1?32 for receiver input and transmitter output waveforms and for all differential i/o standards (lvds, mini-lvds, and rsds). v cc_clkin is the power supply for differential column clock input pins. v ccpd is the power supply for row i/os and all other column i/os. sstl-15 class i -0.3 v ref - 0.1 v re f + 0.1 v ccio + 0.3 v ref - 0.175 v re f + 0.175 0.2 * v ccio 0.8 * v ccio 8-8 sstl-15 class ii -0.3 v ref - 0.1 v re f + 0.1 v ccio + 0.3 v ref - 0.175 v re f + 0.175 0.2 * v ccio 0.8 * v ccio 16 -16 hstl-18 class i -0.3 v ref - 0.1 v re f + 0.1 v ccio + 0.3 v re f - 0.2 v ref + 0.2 0.4 v ccio - 0.4 8-8 hstl-18 class ii -0.3 v ref - 0.1 v re f + 0.1 v ccio + 0.3 v re f - 0.2 v ref + 0.2 0.4 v ccio - 0.4 16 -16 hstl-15 class i -0.3 v ref - 0.1 v re f + 0.1 v ccio + 0.3 v re f - 0.2 v ref + 0.2 0.4 v ccio - 0.4 8-8 hstl-15 class ii -0.3 v ref - 0.1 v re f + 0.1 v ccio + 0.3 v re f - 0.2 v ref + 0.2 0.4 v ccio - 0.4 16 -16 hstl-12 class i -0.15 v re f - 0.08 v ref + 0.08 v ccio + 0.15 v re f - 0.15 v ref + 0.15 0.25* v ccio 0.75* v ccio 8-8 hstl-12 class ii -0.15 v re f - 0.08 v ref + 0.08 v ccio + 0.15 v re f - 0.15 v ref + 0.15 0.25* v ccio 0.75* v ccio 16 -16 table 1?16. single-ended sstl and hstl i/o standards signal specifications?preliminary (part 2 of 2) i/o standard v il(dc) (v) v ih(dc) (v) v il(ac) (v) v ih(ac) (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min max min max max min max min table 1?17. differential sstl i/o standard specifications?preliminary i/o standard v ccio (v) v swing(dc) (v) v x(ac) (v) v swing(ac) (v) v ox(ac) (v) min typ max min max min typ max min max min typ max sstl-2 class i, ii 2.375 2.5 2.625 0.3 v ccio + 0.6 v ccio /2 - 0.2 ? v ccio /2 + 0.2 0.6 v ccio + 0.6 v ccio /2 - 0.15 ? v ccio /2 + 0.15 sstl-18 class i, ii 1.71 1.8 1.89 0.3 v ccio + 0.6 v ccio /2 - 0.175 ? v ccio /2 + 0.175 0.5 v ccio + 0.6 v ccio /2 - 0.125 ? v ccio /2 + 0.125 sstl-15 class i, ii 1.425 1.5 1.575 0.2 ? ? v ccio /2 ? 0.4 ? ? v ccio /2 ? table 1?18. differential hstl i/o standard specifications?preliminary i/o standard v ccio (v) v dif(dc) (v) v x(ac) (v) v cm(dc) (v) v dif(ac) (v) min typ max min max min typ max min typ max min max hstl-18 class i, ii 1.71 1.8 1.89 0.2 ? 0.78 ? 1.12 0.8 ? 1.12 0.4 ? hstl-15 class i, ii 1.425 1.5 1.575 0.2 ? 0.68 ? 0.9 0.7 ? 0.9 0.4 ? hstl-12 class i, ii 1.14 1.2 1.26 0.2 ? ? 0.5* v ccio ? 0.4* v ccio 0.5* v ccio 0.6* v ccio 0.3 ? table 1?19. differential i/o standard specifications?preliminary (note 1) (part 1 of 2) i/o standard v ccio (v) v id (mv) v icm(dc) (v) v od (v) (2) v ocm (v) (2) min typ max min condition max min condition max min typ max min typ max 2.5v lvds (hio) 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.05 (4) d ma x 700 mbps 1.8 (4) 0.247 ? 0.6 1.125 1.25 1.375 ? 1.05 (4) d max > 700 mbps 1.55 (4) ???? ? ?
chapter 1: dc and switching characteristics of hardcopy iv devices 1?11 electrical characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 power consumption altera offers two ways to estimate power consumption for a design: the excel-based powerplay epe and the quartus ? ii powerplay power analyzer feature. use the interactive excel-based powerplay epe prior to designing to get a magnitude estimate of the device power. the quartus ii powerplay power analyzer provides better quality estimates based on the specifics of the design after place-and-route is complete. the powerplay power analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, combined with detailed circuit models, can yield very accurate power estimates. refer to table 1?6 on page 1?6 for supply current estimates for v ccpgm and v cc_clkin . use the powerplay epe and power analyzer for current estimates of the remaining power supplies. f for more information about power estimation tools, refer to the powerplay early power estimator page on the altera website and the powerplay power analysis chapter in volume 3 of the quartus ii handbook . 2.5v lvds (vio) 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.05 (4) d ma x 700 mbps 1.8 (4) 0.247 ? 0.6 1 1.25 1.5 ? 1.05 (4) d max > 700 mbps 1.55 (4) ???? ? ? rsds (hio) 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.3 ? 1.4 0.1 0.2 0.6 0.5 1.2 1.4 rsds (vio) 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.3 ? 1.4 0.1 0.2 0.6 0.5 1.2 1.5 mini-lvds (hio) 2.375 2.5 2.625 200 ? 600 0.4 ? 1.325 0.25 ? 0.6 0.5 1.2 1.4 mini-lvds (vio) 2.375 2.5 2.625 200 ? 600 0.4 ? 1.325 0.25 ? 0.6 0.5 1.2 1.5 lvpecl (vio) (5) 2.375 (6) 2.5 (6) 2.625 (6) 300 ? ? 0.6 d ma x 700 mbps 1.8 (3) ???? ? ? ??? ? ? ?0.6 d max > 700 mbps 1.6 (3) ???? ? ? notes to ta bl e 1? 19 : (1) vio (vertical i/o) is top and bottom i/os; hio (horizontal i/o) is left and right i/os. (2) rl range: 90 rl 110 . (3) for d max > 700 mbps, the minimum input voltage is 0.85 v; the maximum input voltage is 1.75 v. for f max 700 mbps, the minimum input voltage is 0.45 v; the maximum input voltage is 1.95 v. (4) for data rate: d max > 700 mbps, the minimum input voltage is 1.0 v, the maximum input voltage is 1.6 v. for d max 700 mbps, the minimum input voltage is 0 v, the maximum input voltage is 1.85 v. (5) column and row i/o banks support lvpecl i/o standards for input operation only on dedicated clock input pins. differential c lock inputs in column i/o use v cc_clkin , which must be powered by 2.5 v. differential clock inputs in row i/os are powered by v ccpd . (6) the power supply for column i/o lvpecl differential clock input buffer is v cc_clkin . table 1?19. differential i/o standard specifications?preliminary (note 1) (part 2 of 2) i/o standard v ccio (v) v id (mv) v icm(dc) (v) v od (v) (2) v ocm (v) (2) min typ max min condition max min condition max min typ max min typ max
chapter 1: dc and switching characteristics of hardcopy iv devices 1?12 switching characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 switching characteristics this section provides performance characteristics of hardcopy iv core and periphery blocks for commercial grade devices. hardcopy iv devices are designed to meet, at minimum, the ?3 speed grade of the hardcopy iv devices. silicon characterization determines the actual performance of the hardcopy iv devices. these characteristics are designated as preliminary or final , as defined in the following: preliminary ?preliminary characteristics are created using simulation results, process data, and other known parameters. final ?final numbers are based on actual silicon characterization and testing. these numbers reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions. transceiver performance specifications this section describes transceiver performance specifications. table 1?20 lists hardcopy iv gx transceiver specifications. table 1?20. hardcopy iv gx transceiver specifications (part 1 of 5) symbol parameter minimum typical maximum unit reference clock input frequency from refclk input pins ?50?672mhz phase frequency detector (cmu pll and receiver cdr) ?50?325mhz absolute vmax for a refclk pin ???1.6v operational vmax for a refclk pin ???1.5v absolute vmin for a refclk pin ?-0.4??v rise/fall time ? ? ? 0.2 ui duty cycle ? 45 ? 55 % peak-to-peak differential input voltage ? 200 ? 1600 mv spread-spectrum modulating clock frequency pci express 30 ? 33 khz spread-spectrum downspread pci express ? 0 to -0.5% ? ? on-chip termination resistors ? ? 100 ? ohm vicm (ac coupled) ? ? 1100 ? mv vicm (dc coupled) hcsl i/o standard for pci express reference clock 250 ? 550 mv rref ? ? 2000 +/-1% ? ohm transceiver clocks calibration block clock frequency ?10?125mhz
chapter 1: dc and switching characteristics of hardcopy iv devices 1?13 switching characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 fixedclk clock frequency pci express receiver detect ? 125 ? mhz reconfig_clk clock frequency dynamic reconfiguration clock frequency 2.5/37.5 (2) ?50? transceiver block minimum power-down pulse width ??1?s receiver data rate (single width, non-pma direct) ? 600 ? 3750 mbps data rate (double width, non-pma direct) ? 1000 ? 6500 mbps data rate (single width, pma direct) ? 600 ? 3250 mbps data rate (double width, pma direct) ? 1000 ? 6500 mbps absolute vmax for a receiver pin (3) ???1.6v operational vmax for a receiver pin ???1.5v absolute vmin for receiver pin ? -0.4 ? - v maximum peak-to-peak differential input voltage vid (diff p-p) vicm = 0.82v setting ? ? 2.7 v vicm = 1.1v setting (4) ??1.6v minimum peak-to-peak differential input voltage vid (diff p-p) data rate = 600 mbps to 5 gbps 100 ? ? mv data rate > 5 gbps 165 ? ? mv vicm vicm = 0.82v setting ? 820 ? mv vicm = 1.1v setting (4) ?1100?mv differential on-chip termination resistors 85-ohm setting ? 85 ? ohm 100-ohm setting ? 100 ? ohm 120-ohm setting ? 120 ? ohm 150-ohm setting ? 150 ? ohm return loss differential mode pci express 50 mhz to 1.25ghx: -10db ??? xaui 100 mhz to 2.5 ghz: -10db ??? (oif) cei 100 mhz to 4.875 ghz: -8db 4.875ghz to 10ghz: 16.6 db/decade slope ??? table 1?20. hardcopy iv gx transceiver specifications (part 2 of 5) symbol parameter minimum typical maximum unit
chapter 1: dc and switching characteristics of hardcopy iv devices 1?14 switching characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 return loss common mode pci express 50 mhz to 1.25ghx: -6db ??? xaui 100 mhz to 2.5 ghz: -6db ??? (oif) cei 100 mhz to 4.875 ghz: -6db 4.875ghz to 10ghz: 16.6 db/decade slope ??? programmable ppm detector (5) ? +/- 62.5, 100, 125, 200, 250, 300, 500, 1000 ??ppm run length ? ? 80 ? ui programmable equalization ? ? ? 16 db signal detect/loss threshold pci express (pipe) mode 65 ? 175 mv cdr ltr time (6) ???75s cdr minimum t1b (7) ?15??s ltd l oc k ti me (8) ?01004000ns data lock time from rx_freqlocked (9) ???4000ns receiver buffer and cdr offset cancellation time (per channel) ???7872 reconfig_clk cycles programmable dc gain dc gain setting = 0 ? 0 ? db dc gain setting = 1 ? 3 ? db dc gain setting = 2 ? 6 ? db dc gain setting = 3 ? 9 ? db dc gain setting = 4 ? 12 ? db transmitter data rate (single width, non-pma direct) ? 600 ? 3750 mbps data rate (double width, non-pma direct) ? 1000 ? 6500 mbps data rate (single width, pma direct) (10) ? 600 ? 3250 mbps data rate (double width, pma direct) (10) ? 1000 ? 6500 mbps vocm 0.65v setting ? 650 ? mv differential on-chip termination resistors 85-ohm setting ? 85 ? ohm 100-ohm setting ? 100 ? ohm 120-ohm setting ? 120 ? ohm 150-ohm setting ? 150 ? ohm table 1?20. hardcopy iv gx transceiver specifications (part 3 of 5) symbol parameter minimum typical maximum unit
chapter 1: dc and switching characteristics of hardcopy iv devices 1?15 switching characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 return loss differential mode pci express 50 mhz to 1.25ghx: -10db ??? xaui 312 mhz to 625 mhz: -10db 625mhz to 3.125ghz: - 10db/decade slope ??? (oif) cei 100 mhz to 4.875 ghz: -8db 4.875ghz to 10ghz: 16.6 db/decade slope ??? return loss common mode pci express 50 mhz to 1.25ghx: -6db ??? (oif) cei 100 mhz to 4.875 ghz: -6db 4.875ghz to 10ghz: 16.6 db/decade slope ??? rise time ? 50 ? 200 ps fall time (11) ?50?200ps intra differential pair skew ? ? ? 15 ps intra-transceiver block skew x4 pma and pcs bonded xaui, pci express (pipe) x4, basic x4 ??120ps inter-transceiver block skew x8 pma and pcs bonded pci express (pipe) x8, basic x8 ? ? 500 ps inter-transceiver block skew xn pma-only bonded (12) basic (pma direct) xn (for n < 18 channels located across 3 transceiver blocks) ? (13) ?ps inter-transceiver block skew xn pma-only bonded (12) basic (pma direct) xn (for n > or = 18 channels located across 4 transceiver blocks) ? (13) ?ps cmu pll0 and cmu pll1 supported data range ? 600 ? 6500 mbps cmu pll lock time from pll_powerdown deassertion ???100s atx pll supported data range (14) /l = 1 4800-5400 and 6000-6375 ??mbps /l = 2 2400-2700 and 3000-3187.5 ??mbps /l = 4 1200-1350 and 1500-1593.75 ??mbps transceiver-fpga fabric interface ????? interface speed (non-pma direct) ?25?250mhz interface speed (pma direct) ? 50 ? 325 mhz table 1?20. hardcopy iv gx transceiver specifications (part 4 of 5) symbol parameter minimum typical maximum unit
chapter 1: dc and switching characteristics of hardcopy iv devices 1?16 switching characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 figure 1?2 shows the lock time parameters in manual mode. figure 1?3 shows the lock time parameters in automatic mode. 1 ltd = lock-to-data ltr = lock-to-reference digital reset pulse width ? minimum is 2 parallel clock cycles ??? notes to ta bl e 1? 20 : (1) the -2x speed grade is the fastest speed grade offered in the following hardcopy iv gx devices: HC4GX15lf780n, hc4gx25lf780n , hc4gx25lf1152n, hc4gx25ff1152n, hc4gx35ff1152n, hc4gx35lf1517n and hc4gx35ff1517n. (2) the minimum reconfig_clk frequency is 2.5mhz if the transceiver channel is configured in transmitter only mode. the minimum reconfig_clk frequency is 37.5mhz if the transceiver channel is configured in receiver only or receiver and transmitter mode. for more detai ls, refer to hardcopy iv dynamic reconfiguration chapter in volume 3 of the hardcopy iv device handbook. (3) the device cannot tolerate prolonged operation at this absolute maximum. (4) the 1.1-v rx vicm setting must be used if the input serial data standard is lvds and the link is dc coupled. (5) the rate matcher supports only up to +/- 300ppm. (6) time taken to rx_pll_locked goes high from rx_analogreset deassertion. refer to figure 1?2 . (7) time for which the cdr must be kept in lock-to-reference mode after rx_pll_locked goes high and before rx_locktodata is asse rted in manual mode. refer to figure 1?2 . (8) time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. refer to figure 1?2 . (9) time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. refer to figure 1?3 . (10) a gpll may be required to meet pma-hardcopy fabric interface timing above certain data rates and this requirement is same a s pma-fpga fabric interface. refer to section ?left/right pll requirements in basic (pma direct) mode? in the stratix iv transceiver clocking chapter in volume 2 of the stratix iv device handbook . (11) the quartus ii software automatically selects the appropriate slew rate depending on the configured data rate or functional mode. (12) for applications that require low transmit lane-to-lane skew, use basic (pma direct) xn to achieve pma-only bonding across all channels in the link. you can bond all channels on one side of the device by configuring them in basic (pma-direct) xn mode. refer to the basic (pma direct) mode clocking section in the stratix iv transceiver clocking chapter for details on clocking requirements in this mode. (13) pending characterization. (14) the quartus ii software automatically selects the appropriate /l divider depending upon the configured data rate. table 1?20. hardcopy iv gx transceiver specifications (part 5 of 5) symbol parameter minimum typical maximum unit
chapter 1: dc and switching characteristics of hardcopy iv devices 1?17 switching characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 table 1?21 through table 1?23 show the typical vod for various differential termination settings for hardcopy iv gx devices. figure 1?2. lock time parameters for manual mode figure 1?3. lock time parameters for automatic mode ltr ltd invalid data v alid data r x_locktodata ltd lock time cdr status r x_dataout r x_ p l l_ l o c k e d r x_analogreset cdr ltr time cdr minimum t1b ltr ltd invalid data v alid data r x_freqlocked data lock time from rx_freqlocked r x_dataout cdr status
chapter 1: dc and switching characteristics of hardcopy iv devices 1?18 switching characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 table 1?24 shows hardcopy iv gx transceiver jitter specifications for all supported protocols. table 1?21. typical vod setting, tx term = 85 ohm symbol vod setting (mv) 0123456 7 vod differential peak-peak typical 170 340 510 595 680 765 850 1020 table 1?22. typical vod setting, tx term = 100 ohm symbol vod setting (mv) 012345 6 7 vod differential peak-peak typical 200 400 600 700 800 900 1000 1200 table 1?23. typical vod setting, tx term = 120 ohm symbol vod setting (mv) 012 3 4 5 vod differential peak-peak typical 300 600 900 1050 1200 1350 table 1?24. hardcopy iv gx transceiver block jitter specification (note 1) and (2) (part 1 of 6) symbol/description conditions min typ max unit sonet/sdh transmit jitter generation (3) peak-to-peak jitter at 622.08 mbps pattern = prbs23 ? ? 0.1 ui rms jitter at 622.08 mbps pattern = prbs23 ? ? 0.01 ui peak-to-peak jitter at 2488.32 mbps pattern = prbs23 ? ? 0.1 ui rms jitter at 2488.32 mbps pattern = prbs23 ? ? 0.01 ui sonet/sdh receiver jitter tolerance (3) jitter tolerance at 622.08mbps jitter frequency = 0.03khz pattern = prbs23 > 15 > 15 > 15 ui jitter frequency = 25khz pattern = prbs24 > 1.5 > 1.5 > 1.5 ui jitter frequency = 250khz pattern = prbs25 > 0.15 > 0.15 > 0.15 ui
chapter 1: dc and switching characteristics of hardcopy iv devices 1?19 switching characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 jitter tolerance at 2488.32mbps jitter frequency = 0.06khz pattern = prbs23 > 15 > 15 > 15 ui jitter frequency = 100khz pattern = prbs24 > 1.5 > 1.5 > 1.5 ui jitter frequency = 1mhz pattern = prbs25 > 0.15 > 0.15 > 0.15 ui jitter frequency = 10mhz pattern = prbs26 > 0.15 > 0.15 > 0.15 ui fibre channel transmit jitter generation (4) , (12) total jitter fc-1 pattern = crpat ? ? 0.23 ui deterministic jitter fc-1 pattern = crpat ? ? 0.11 ui total jitter fc-2 pattern = crpat ? ? 0.33 ui deterministic jitter fc-2 pattern = crpat ? ? 0.2 ui total jitter fc-4 pattern = crpat ? ? 0.52 ui deterministic jitter fc-4 pattern = crpat ? ? 0.33 ui fibre channel receiver jitter tolerance (4) , (13) deterministic jitter fc-1 pattern = cjtpat > 0.37 ui random jitter fc-1 pattern = cjtpat > 0.31 ui sinusoidal jitter fc-1 fc/25000 > 1.5 ui fc/1667 > 0.1 ui deterministic jitter fc-2 pattern = cjtpat > 0.33 ui random jitter fc-2 pattern = cjtpat > 0.29 ui sinusoidal jitter fc-2 fc/25000 > 1.5 ui fc/1667 > 0.1 ui deterministic jitter fc-4 pattern = cjtpat > 0.33 ui random jitter fc-4 pattern = cjtpat > 0.29 ui sinusoidal jitter fc-4 fc/25000 > 1.5 ui fc/1667 > 0.1 ui xaui transmit jitter generation (5) total jitter at 3.125gbps pattern = cjpat ? ? 0.3 ui deterministic jitter at 3.125gbps pattern = cjpat ? ? 0.17 ui xaui receiver jitter tolerance (5) total jitter ? > 0.65 ui deterministic jitter ? > 0.37 ui peak-to-peak jitter jitter frequency = 22.1khz > 8.5 ui table 1?24. hardcopy iv gx transceiver block jitter specification (note 1) and (2) (part 2 of 6) symbol/description conditions min typ max unit
chapter 1: dc and switching characteristics of hardcopy iv devices 1?20 switching characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 peak-to-peak jitter jitter frequency = 1.875mhz > 0.1 ui peak-to-peak jitter jitter frequency = 20mhz > 0.1 ui pci express transmit jitter generation (6) total jitter at 2.5gbps (gen1) compliance pattern ?? 0.25 ui total jitter at 5gbps (gen2) compliance pattern ?? ? ui pci express receiver jitter tolerance (6) total jitter at 2.5gbps (gen1) compliance pattern > 0.6 ui total jitter at 2.5gbps (gen2) compliance pattern ?? ? ui serial rapidio transmit jitter generation (7) deterministic jitter (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat ?? 0.17 ui total jitter (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat ?? 0.35 ui serial rapidio receiver jitter tolerance (7) deterministic jitter (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.37 ui combined deterministic and random jitter tolerance (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.55 ui sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 22.1khz data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 8.5 ui jitter frequency = 1.875mhz data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.1 ui jitter frequency = 20mhz data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.1 ui gige transmit jitter generation (8) deterministic jitter (peak-to-peak) pattern = crpat ?? 0.14 ui total jitter (peak-to-peak) pattern = crpat ?? 0.279 ui gige receiver jitter tolerance (8) deterministic jitter (peak-to-peak) pattern = cjpat > 0.4 ui combined deterministic and random jitter tolerance (peak-to-peak) pattern = cjpat > 0.66 ui table 1?24. hardcopy iv gx transceiver block jitter specification (note 1) and (2) (part 3 of 6) symbol/description conditions min typ max unit
chapter 1: dc and switching characteristics of hardcopy iv devices 1?21 switching characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 higig transmit jitter generation (9) deterministic jitter (peak-to-peak) data rate = 3.75gbps pattern = cjpat ?? ? ui total jitter (peak-to-peak) data rate = 3.75gbps pattern = cjpat ?? ? ui higig receiver jitter tolerance (9) deterministic jitter tolerance (peak-to-peak) data rate = 3.75gbps pattern = cjpat ?? ? ui combined deterministic and random jitter tolerance (peak-to-peak) data rate = 3.75gbps pattern = cjpat ?? ? ui sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 22.1khz data rate = 3.75 gbps pattern = cjpat ?? ? ui jitter frequency = 1.875mhz data rate = 3.75 gbps pattern = cjpat ?? ? ui jitter frequency = 20mhz data rate = 3.75 gbps pattern = cjpat ?? ? ui (oif) cei transmitter jitter generation (10) total jitter (peak-to-peak) data rate = 6.375 gbps pattern = prbs15 ber = 10exp-12 ?? ? ui (oif) cei receiver jitter tolerance (10) deterministic jitter tolerance (peak-to-peak) data rate = 6.375 gbps pattern = prbs31 ber = 10exp-12 ?? ? ui combined deterministic and random jitter tolerance (peak-to-peak) data rate = 6.375 gbps pattern = prbs31 ber = 10exp-13 ?? ? ui table 1?24. hardcopy iv gx transceiver block jitter specification (note 1) and (2) (part 4 of 6) symbol/description conditions min typ max unit
chapter 1: dc and switching characteristics of hardcopy iv devices 1?22 switching characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 38.2khz data rate = 6.375 gbps pattern = prbs31 ber = 10exp-12 ?? ? ui jitter frequency = 3.82mhz data rate = 6.375 gbps pattern = prbs31 ber = 10exp-12 ?? ? ui jitter frequency = 20mhz data rate = 6.375 gbps pattern = prbs31 ber = 10exp-12 ?? ? ui sdi transmitter jitter generation (11) alignment jitter (peak-to-peak) data rate = 1.485gbps (hd) pattern = color bar low-frequency roll- off = 100khz 0.2 ?? ui data rate = 2.97gbps (3g) pattern = color bar low-frequency roll- off = 100khz 0.3 ?? ui sdi receiver jitter tolerance (11) sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 15khz data rate = 2.97gbps (3g) pattern = single line scramble color bar > 2 ui jitter frequency = 100khz data rate = 2.97gbps (3g) pattern = single line scramble color bar > 0.3 ui jitter frequency = 148.5mhz data rate = 2.97gbps (3g) pattern = single line scramble color bar > 0.3 ui table 1?24. hardcopy iv gx transceiver block jitter specification (note 1) and (2) (part 5 of 6) symbol/description conditions min typ max unit
chapter 1: dc and switching characteristics of hardcopy iv devices 1?23 switching characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 core performance specifications this section describes the clock tree, pll, dsp, trimatrix, and configuration and jtag specifications. clock tree specifications table 1?25 lists clock tree performance specifications for the logic array, dsp blocks, and trimatrix memory blocks for hardcopy iv devices. pll specifications table 1?26 describes the hardcopy iv pll specifications when operating in both the commercial junction temperature range (0 to 85c) and the industrial junction temperature range (?40 to 100c). for a pll block diagram, refer to the ?pll specifications? row in table 1?39 on page 1?32 . sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 20khz data rate = 1.485gbps (hd) pattern = 75% color bar > 1 ui jitter frequency = 100khz data rate = 1.485gbps (hd) pattern = 75% color bar > 0.2 ui jitter frequency = 148.5mhz data rate = 1.485gbps (hd) pattern = 75% color bar > 0.2 ui notes to ta bl e 1? 24 : (1) dedicated refclk pins were used to drive the input reference clocks. (2) jitter numbers specified are valid for the stated conditions only. (3) the jitter numbers for sonet/sdh are compliant to the gr-253-core issue 3 specification. (4) the jitter numbers for fibre channel are compliant to the fc-pi-4 specification revision 6.1.0. (5) the jitter number for xaui are compliant to the ieee802.3ae-2002 specification. (6) the jitter numbers for pci express are compliant to the pcie base specification 2.0. (7) the jitter numbers for serial rapidio are compliant to the rapidio specification 1.3. (8) the jitter numbers for gige are compliant to the ieee802.3-2002 specification. (9) the jitter numbers for higig are compliant to the ieee802.3ae-2002 specification. (10) the jitter numbers for (oif) cei are compliant to the oif-cei-02.0 specification. (11) the hd-sdi and 3g-sdi jitter numbers are compliant to the smpte292m and smpte424m specifications. (12) the fibre channel transmitter jitter generation numbers are compliant to the specification at t interoperability point. (13) the fibre channel receiver jitter tolerance numbers are compliant to the specification at r interoperability point. table 1?24. hardcopy iv gx transceiver block jitter specification (note 1) and (2) (part 6 of 6) symbol/description conditions min typ max unit table 1?25. hardcopy iv clock tree performance?preliminary (note 1) device commercial grade (mhz) unit hc4e25 600 mhz hc4e35 600 mhz note to tab l e 1 ?2 5 : (1) pending silicon characterization.
1?24 chapter 1: dc and switching characteristics of hardcopy iv devices switching characteristics hardcopy iv device handbook volume 4 ? june 2009 altera corporation table 1?26. hardcopy iv pll specifications?preliminary (part 1 of 2) (note 1) symbol parameter min typ max unit f in input clock frequency 5 ? 717 (2) mhz f inpfd input frequency to the pfd 5? 325 mhz f vco pll vco operating range 600 ? 1300 mhz t einduty input clock or external feedback clock input duty cycle 40 ? 60 % f out output frequency for internal global or regional clock ? ? 600 (3) mhz f out_ext output frequency for external clock input (?3 speed grade) ? ? 717 (3) mhz t outduty duty cycle for external clock output (when set to 50%) 45 50 55 % t fcomp external feedback clock compensation time ?? 10 ns t configpll time required to reconfigure pll scan chain ?? ? scanclk cycles t configphase time required or reconfigure phase shift ?? ? scanclk cycles f scanclk scanclk frequency ?? 100 mhz t lock time required to lock from end of device power ?? ? ms t dlock time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) ?? ? ms f clbw pll closed-loop low bandwidth ?? ? mhz pll closed-loop medium bandwidth ?? ? mhz pll closed-loop high bandwidth (6) ?? ? mhz t pll_pserr accuracy of pll phase shift ?? ? ps t ar eset minimum pulse width on a reset signal 10 ? ? ns t inccj (4) input clock cycle to cycle jitter (f ref 100 mhz) ? ? ? ui (p-p) input clock cycle to cycle jitter (f ref < 100 mhz) ? ? ? ps (p-p) t outpj_dc (5) period jitter for dedicated clock output (f out 100 mhz) ? ? ? ps (p-p) period jitter for dedicated clock output (f out < 100 mhz) ? ? ? mui (p-p) t outccj_dc (5) cycle-to-cycle jitter for dedicated clock output (f out 100 mhz) ? ? ? ps (p-p) cycle-to-cycle jitter for dedicated clock output (f out < 100 mhz) ? ? ? mui (p-p) t outpj_io (5) period jitter for clock output on regular io (f out 100 mhz) ? ? ? ps (p-p) period jitter for clock output on regular io (f out < 100 mhz) ? ? ? mui (p-p) t outccj_io (5) cycle-to-cycle jitter for clock output on regular io (f out 100 mhz) ? ? ? ps (p-p) cycle-to-cycle jitter for clock output on regular io (f out <100mhz) ? ? ? mui (p-p)
chapter 1: dc and switching characteristics of hardcopy iv devices 1?25 switching characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 dsp block specifications table 1?27 describes the hardcopy iv dsp block performance specifications. trimatrix memory block specifications table 1?28 describes the hardcopy iv trimatrix memory block specifications. f drift frequency drift after pfdena is disabled for duration of 100 us ?? 10 % notes to ta bl e 1? 26 : (1) pending silicon characterization. (2) this specification is limited in quartus ii software by the i/o maximum frequency. the maximum i/o frequency is different fo r each i/o standard. (3) this specification is limited by the lower of the two: i/o f ma x or f out of the pll. (4) a high input jitter directly affects the pll output jitter. to have low pll output clock jitter, you must provide a clean cl ock source, which is less than 200 ps. (5) peak-to-peak jitter with a probability level of 10 ?12 (14 sigma, 99.99999999974404% confidence level). the output jitter specification applies to the intrinsic jitter of the pll, when an input jitter of 30 ps is applied. the external memory interface clock output jitter specifications use a different measurement method and are available in table 1?38 . (6) high bandwidth pll settings are not supported in external feedback mode. table 1?26. hardcopy iv pll specifications?preliminary (part 2 of 2) (note 1) symbol parameter min typ max unit table 1?27. hardcopy iv dsp block performance specifications?preliminary (note 1) , (2) mode number of multipliers max unit 99-bit multiplier 1 410 mhz 1212-bit multiplier 1 410 mhz 1818-bit multiplier 1495mhz 3636-bit multiplier 1365mhz 1818-bit multiply accumulator 4390mhz 1818-bit multiply adder 4405mhz 1818-bit multiply adder-signed full precision 2405mhz 1818-bit multiply adder with loopback (3) 2405mhz 36-bit shift (32 bit data) 1390mhz double mode 1365mhz notes to ta bl e 1? 27 : (1) maximum is for fully pipelined block with round and saturation disabled. (2) pending silicon characterization. (3) maximum is for non-pipelined block with loopback input registers disabled and round and saturation disabled. table 1?28. hardcopy iv trimatrix memory block performance specifications?preliminary (part 1 of 2) (note 1) memory mode trimatrix memory max unit mlab single port 6410 1500mhz simple dual-port 3220 single clock 1500mhz simple dual-port 6410 single clock 1500mhz
1?26 chapter 1: dc and switching characteristics of hardcopy iv devices switching characteristics hardcopy iv device handbook volume 4 ? june 2009 altera corporation jtag specification table 1?29 shows the jtag timing parameters and values for hardcopy iv devices. refer to the ?high-speed i/o block? row in table 1?39 on page 1?32 for jtag timing requirements. periphery performance this section describes periphery performance, including high-speed i/o and external memory interface, and oct calibration block specifications. high-speed i/o specification table 1?30 shows the high-speed i/o timing for hardcopy iv devices. m9k block single-port 25636 1575mhz simple dual-port 25636 single clk 1575mhz true dual port 51218 single clk 1575mhz m144k single-port 2k72 1460mhz simple dual-port 2k72 dual clk 1460mhz simple dual-port 2k64 dual clk (with ecc) 1250mhz true dual-port 4k36 dual clk 1460mhz note to tab l e 1 ?2 8 : (1) pending silicon characterization. table 1?29. hardcopy iv jtag timing parameters and values?preliminary symbol description min max unit t jc p tck clock period 30 ? ns t jc h tck clock high time 14 ? ns t jc l tck clock low time 14 ? ns t jp su (tdi) tdi jtag port setup time 1?ns t jp su (tms ) tms jtag port setup time 3?ns t jp h jtag port hold time 5?ns t jp co jtag port clock to output ?11 (1) ns t jp zx jtag port high impedance to valid output ?14 (1) ns t jp xz jtag port valid output to high impedance ?14 (1) ns note to tab l e 1 ?2 9 : (1) a 1 ns adder is required for each v cc io voltage step down from 3.0 v. for example, t jpco = 12 ns if v ccio of the tdo i/o bank = 2.5 v, or 13 ns if it equals 1.8 v. table 1?28. hardcopy iv trimatrix memory block performance specifications?preliminary (part 2 of 2) (note 1) memory mode trimatrix memory max unit table 1?30. high-speed i/o specifications?preliminary (part 1 of 2) (note 1), (2), (3) symbol conditions min typ max unit f hsclk (input clock frequency) clock boost factor w = 1 to 40 (4) 5?717mhz f hsclk_out (output clock frequency) 5?717mhz
chapter 1: dc and switching characteristics of hardcopy iv devices 1?27 switching characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 table 1?31 shows the dpa lock time specifications for hardcopy iv devices. transmitter dedicated lvds?f hsdr (data rate) serdes factor j = 3 to 10 150 ? 1250 mbps serdes factor j = 2, uses ddr registers (5) ? 1250 mbps serdes factor j = 1, uses sdr register (5) ?717mbps lvds_e_3r?f hsdrdpa (data rate) serdes factor j =4 to 10 (5) ? 1000 mbps lvds_e_1r?f hsdrdpa (data rate) (5) ?200mbps t x jitter total jitter for data rate, 600mbps - 1.6gbps ? ? 160 ps total jitter for data rate, < 600mbps ? ? 0.1 ui t duty tx output clock duty cycle 45 50 55 % t rise & t fall dedicated lvds ? ? 200 ps lvds_e_3r ? ? 350 ps lvds_e_1r ? ? 500 ps tccs dedicated lvds ? ? 100 ps lvds_e_3r/ lvds_e_1r ? ? 250 ps receiver f hsdrdpa (data rate) serdes factor j = 3 to 10 150 ? 1250 mbps dpa mode dpa run length ??? (6) ui soft cdr mode soft-cdr ppm tolerance ??? (6) ppm non dpa mode sampling window all differential i/o standards ? ? (6) ps notes to ta bl e 1? 30 : (1) numbers are preliminary pending characterization. (2) when j = 3 to 10, the serdes block is used. (3) when j = 1 or 2, the serdes block is bypassed. (4) clock boost factor ( ) is the ratio between the input data rate to the input clock rate. (5) the minimum specification is dependent on the clock source (for example, pll and clock pin) and the clock routing resource ( global, regional, or local) is used. (6) pending silicon characterization. table 1?30. high-speed i/o specifications?preliminary (part 2 of 2) (note 1), (2), (3) symbol conditions min typ max unit table 1?31. dpa lock time specifications?preliminary (note 1) , (2) , (3) (part 1 of 2) standard training pattern number of data transitions in one repetition of training pattern number of repetition per 256 data transition (4) condition min typ max spi-4 00000000001111111111 2 128 without dpa pll calibration 256 data transitions ? ? with dpa pll calibration 3256 data transitions + 296 slow clock cycles (5) , (6) ??
1?28 chapter 1: dc and switching characteristics of hardcopy iv devices switching characteristics hardcopy iv device handbook volume 4 ? june 2009 altera corporation figure 1?4 shows the dpa lock time specifications with dpa pll calibration enabled. external memory interface specifications table 1?32 and table 1?33 list the external memory interface specifications for the hardcopy iv device family. use these tables for memory interface timing analysis. parallel rapid i/o 00001111 2 128 without dpa pll calibration 256 data transitions ? ? with dpa pll calibration 3256 data transitions + 296 slow clock cycles (5) , (6) ?? 10010000 4 64 without dpa pll calibration 256 data transitions ? ? with dpa pll calibration 3256 data transitions + 296 slow clock cycles (5) , (6) ?? misc. 10101010 8 32 without dpa pll calibration 256 data transitions ? ? with dpa pll calibration 3 256 data transitions + 2 96 slow clock cycles (5) , (6) ?? 01010101 8 32 without dpa pll calibration 256 data transitions ? ? with dpa pll calibration 3 256 data transitions + 2 96 slow clock cycles (5) , (6) ?? notes to ta bl e 1? 31 : (1) the dpa lock time is for one channel. (2) one data transition is defined as a 0-to-1 or 1-to-0 transition. (3) the dpa lock time stated in the table applies to both commercial and industrial grade. (4) this is the number of repetition for the stated training pattern to achieve 256 data transitions. (5) slow clock = data rate (mhz)/deserialization factor. (6) the dpa lock time with dpa pll calibration enabled is preliminary. table 1?31. dpa lock time specifications?preliminary (note 1) , (2) , (3) (part 2 of 2) standard training pattern number of data transitions in one repetition of training pattern number of repetition per 256 data transition (4) condition min typ max figure 1?4. dpa lock time specification with dpa pll calibration enabled table 1?32. hardcopy iv maximum clock rate support for external memory interfaces with half-rate controller?preliminary (note 1) (part 1 of 2) memory standards mhz top and bottom i/o banks left and right i/o banks ddr3 sdram 533 (2) 533 (2) ddr2 sdram 333 333 ddr sdram 200 200 qdrii+ sram 350 350 rx_dpa_locked rx_reset dpa lock time 256 data transitions 96 slow clock cycles 256 data transitions 256 data transitions 96 slow clock cycles
chapter 1: dc and switching characteristics of hardcopy iv devices 1?29 switching characteristics ? june 2009 altera corporation hardcopy iv device handbook volume 4 external memory i/o timing specifications table 1?34 and table 1?35 list hardcopy iv device timing uncertainties on the read and write data paths. use these specifications to determine timing margins for source synchronous paths between a hardcopy iv device and an external memory device. refer to ?sw (sampling window)? in table 1?39 on page 1?32 . qdrii sram 300 300 rldram ii 400 (3) 400 (3) notes to ta bl e 1? 32 : (1) pending silicon characterization. (2) pending ip support. actual achievable performance is based on design and system-specific factors. for 533mhz ddr3 support, please contact altera. (3) pending ip support. actual achievable performance is based on design and system-specific factors. for 400mhz rldram ii support, please contact altera. table 1?33. hardcopy iv maximum clock rate support for external memory interfaces with full-rate controller?preliminary (note 1) memory standards mhz top and bottom i/o banks left and right i/o banks ddr2 sdram 267 267 ddr sdram 200 200 notes to ta bl e 1? 33 : (1) pending silicon characterization. table 1?34. sampling window (sw) - read side?preliminary (note 1) (part 1 of 2) location (2) memory type sampling window (ps) setup hold vio ddr3 (>400mhz) (3) 282 56 ddr3 344 85 ddr2 213 162 ddr1 236 178 qdrii/ii+ 218 203 rldram ii (>333mhz) (4) 198 183 table 1?32. hardcopy iv maximum clock rate support for external memory interfaces with half-rate controller?preliminary (note 1) (part 2 of 2) memory standards mhz top and bottom i/o banks left and right i/o banks
1?30 chapter 1: dc and switching characteristics of hardcopy iv devices switching characteristics hardcopy iv device handbook volume 4 ? june 2009 altera corporation dll and dqs logic block specifications table 1?36 describes the delay-locked loop (dll) frequency range specifications for hardcopy iv devices. hio ddr3 (>400mhz) (3) 282 56 ddr3 344 85 ddr2 213 162 ddr1 236 178 qdrii/ii+ 218 203 rldram ii (>333mhz) (4) 198 183 note to tab le 1 ?3 4 : (1) pending silicon characterization. (2) vio (vertical i/o) refers to i/os in the top and bottom banks; hio (horizontal i/o) refers to i/os in the left and right banks. (3) pending ip support. actual achievable performance is based on design and system-specific factors. for ddr3 > 400mhz support, contact altera. (4) pending ip support. actual achievable performance is based on design and system-specific factors. for rldram ii > 333mhz support, contact altera. table 1?35. transmitter channel-to-channel skew (tccs)?write side (note 1) location (2) memory type tccs (ps) lead lag vio ddr3 (>400mhz) (3) 234 286 ddr3 344 347 ddr2 270 380 ddr1 275 396 qdrii/ii+ 294 408 rldram ii (>333mhz) (4) 346 356 hio ddr3 (>400mhz) (3) 282 56 ddr3 344 347 ddr2 270 380 ddr1 275 396 qdrii/ii+ 294 408 rldram ii (>333mhz) (4) 346 356 notes to ta bl e 1? 35 : (1) pending silicon characterization. (2) vio (vertical i/o) refers to i/os in the top and bottom banks; hio (horizontal i/o) refers to i/os in the left and right banks. (3) pending ip support. actual achievable performance is based on design and system-specific factors. for ddr3 > 400 mhz support, contact altera. (4) pending ip support. actual achievable performance is based on design and system-specific factors. for rldram ii > 333 mhz support, contact altera. table 1?34. sampling window (sw) - read side?preliminary (note 1) (part 2 of 2) location (2) memory type sampling window (ps) setup hold
chapter 1: dc and switching characteristics of hardcopy iv devices 1?31 i/o timing model ? june 2009 altera corporation hardcopy iv device handbook volume 4 oct calibration block specifications table 1?37 describes the oct calibration block specifications for hardcopy iv devices. duty cycle distortion (dcd) specifications table 1?38 lists the worst case dcd for hardcopy iv devices. i/o timing model the i/o timing specifications for hardcopy iv devices will be available in a future revision of this chapter. table 1?36. hardcopy iv dll frequency range specifications?preliminary (note 1) frequency mode frequency range (mhz) available phase shift dqs delay buffer mode (2) number of delay chains 0 90-140 45, 90, 135, 180 low 16 1 120-190 30, 60, 90, 120 low 12 2 150-230 36, 72, 108, 144 low 10 3 180-290 45, 90, 135, 180 low 8 4 240-350 30, 60, 90, 120 high 12 5 290-420 36, 72, 108, 144 high 10 6 360-540 (3) 45, 90, 135, 180 high 8 note to tab l e 1 ?3 6 : (1) pending silicon characterization (2) low indicates 6-bit dqs delay setting, high indicates 5-bit dqs delay setting. (3) frequency > 530 mhz on mode 6 is to for 533 mhz ddr3 support. pending ip support. actual achievable performance is based on de sign and system-specific factors. for ddr3 > 400 mhz, ple ase contact altera. table 1?37. oct calibration block specifications?preliminary symbol description min typ max unit octusrclk clock required by oct calibration blocks ? ? 20 mhz t oc tcal number of octusrclk clock cycles required for oct r s /r t calibration ? 1000 ? cycles t octshift number of octusrclk clock cycles required for oct code to shift out ? 28 ? cycles t rs_rt time required to dynamically switch from r s to r t ?2.5? ns table 1?38. dcd on hardcopy iv i/o pins?preliminary symbol min max unit output duty cycle 45 55 %
1?32 chapter 1: dc and switching characteristics of hardcopy iv devices glossary hardcopy iv device handbook volume 4 ? june 2009 altera corporation glossary table 1?39 shows the glossary for this chapter. table 1?39. glossary table (part 1 of 4) letter subject definitions a ?? b ?? c ?? d differential i/o standards receiver input waveforms transmitter output waveforms e ?? f f hsclk left/right pll input clock frequency. f hsdr high-speed i/o block: maximum/minimum lvds data transfer rate (f hsdr = 1/tui), non-dpa. f hsdrdpa high-speed i/o block: maximum/minimum lvds data transfer rate (f hsdrdpa = 1/tui), dpa. g ?? h ?? i ?? single-ended waveform differential waveform positive channel (p) = v ih negative channel (n) = v il ground v id v id v id p ? n = 0 v v cm single-ended waveform differential waveform positive channel (p) = v oh negative channel (n) = v ol ground v od v od v od p ? n = 0 v v cm
chapter 1: dc and switching characteristics of hardcopy iv devices 1?33 glossary ? june 2009 altera corporation hardcopy iv device handbook volume 4 j j high-speed i/o block: deserialization factor (width of parallel data bus). jtag timing specifications jtag timing specifications are in the following figure: k ?? l ?? m ?? n ?? o ?? p pll specifications the following block diagram highlights the pll specification parameters: diagram of pll specifications (1) note: (1) core clock can only be fed by dedicated clock input pins or pll outputs. q ?? r r l receiver differential input discrete resistor (external to hardcopy iv device). table 1?39. glossary table (part 2 of 4) letter subject definitions tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms core clock external feedback reconfigurable in user mode key clk n m pfd switchover vco cp lf clkout pins gclk rclk f inpfd f in f vco f out f out_ext counters c0..c9
1?34 chapter 1: dc and switching characteristics of hardcopy iv devices glossary hardcopy iv device handbook volume 4 ? june 2009 altera corporation s sw (sampling window) the period of time during which the data must be valid in order to capture it correctly. the setup and hold times determine the ideal strobe position within the sampling window, as shown in the following figure: timing diagram single-ended voltage referenced i/o standard the jedec standard for sstl and hstl i/o defines both the ac and dc input signal values. the ac values indicate the voltage levels at which the receiver must meet its timing specifications. the dc values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. once the receiver input has crossed the ac value, the receiver changes to the new logic state. the new logic state is then maintained as long as the input stays beyond the ac threshold. this approach is intended to provide predictable receiver timing in the presence of input waveform ringing as, shown in the following figure: single-ended voltage referenced i/o standard t t c high-speed receiver/transmitter input and output clock period. tccs (channel- to-channel-skew) the timing difference between the fastest and slowest output edges, including t co variation and clock skew, across channels driven by the same pll. the clock is included in the tccs measurement (refer to the timing diagram figure under s in this table). t duty high-speed i/o block: duty cycle on high-speed transmitter output clock. timing unit interval (tui) the timing budget allowed for skew, propagation delays, and data sampling window. (tui = 1/(receiver input clock frequency multiplication factor) = t c / w ) t fa ll signal high-to-low transition time (80-20%) t inccj cycle-to-cycle jitter tolerance on pll clock input t outpj_io period jitter on general purpose i/o driven by a pll t outpj_dc period jitter on dedicated clock output driven by a pll t rise signal low-to-high transition time (20-80%) u ?? table 1?39. glossary table (part 3 of 4) letter subject definitions bit time 0.5 x tccs rskm sampling window (sw) rskm 0.5 x tccs v ih ( ac ) v ih(dc) v ref v il(dc) v il(ac ) v oh v ol v ccio v ss
chapter 1: dc and switching characteristics of hardcopy iv devices 1?35 glossary ? june 2009 altera corporation hardcopy iv device handbook volume 4 v v cm (dc) dc common mode input voltage. v ic m input common mode voltage: the common mode of the differential signal at the receiver. v id input differential voltage swing: the difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. v dif(ac) ac differential input voltage: minimum ac input differential voltage required for switching. v dif(dc) dc differential input voltage: minimum dc input differential voltage required for switching. v ih voltage input high: the minimum positive voltage applied to the input that is accepted by the device as a logic high. v ih ( ac ) high-level ac input voltage v ih ( d c) high-level dc input voltage v il voltage input low: the maximum positive voltage applied to the input that is accepted by the device as a logic low. v il( ac) low-level ac input voltage v il ( d c) low-level dc input voltage v ocm output common mode voltage: the common mode of the differential signal at the transmitter. v od output differential voltage swing: the difference in voltage between the positive and complementary conductors of a differential transmission at the transmitter. v swing differential input voltage v x input differential cross point voltage v ox output differential cross point voltage w w high-speed i/o block: clock boost factor x ?? y ?? z ?? table 1?39. glossary table (part 4 of 4) letter subject definitions
1?36 chapter 1: dc and switching characteristics of hardcopy iv devices document revision history hardcopy iv device handbook volume 4 ? june 2009 altera corporation document revision history table 1?40 shows the revision history for this chapter. table 1?40. document revision history date and document version changes made summary of changes june 2009, v1.0 initial release. ?
? june 2009 altera corporation hardcopy iv device handbook, volume 4 additional information about this handbook this handbook provides comprehensive information about the altera ? hardcopy ? iv family of devices. how to contact altera for the most up-to-date information about altera products, see the following table. typographic conventions the following table shows the typographic conventions that this document uses. contact (note 1) contact method address technical support website www.altera.com/support technical training website www.altera.com/training email custrain@altera.com product literature website www.altera.com/literature non-technical support (general) email nacomp@altera.com (software licensing) email authorization@altera.com note: (1) you can also contact your local altera sales office or sales representative. visual cue meaning bold type with initial capital letters indicates command names, dialog box titles, dialog box options, and other gui labels. for example, save as dialog box. for gui elements, capitalization matches the gui. bold type indicates directory names, project names, disk drive names, file names, file name extensions, dialog box options, software utility names, and other gui labels. for example, \qdesigns directory, d: drive, and chiptrip.gdf file. italic type with initial capital letters indicates document titles. for example, an 519: stratix iv design guidelines. italic type indicates variables. for example, n + 1. variable names are enclosed in angle brackets (< >). for example, and .pof file. initial capital letters indicates keyboard keys and menu names. for example, delete key and the options menu. ?subheading title? quotation marks indicate references to sections within a document and titles of quartus ii help topics. for example, ?typographic conventions.?
info?2 additional information hardcopy iv device handbook, volume 4 ? june 2009 altera corporation courier type indicates signal, port, register, bit, block, and primitive names. for example, data1 , tdi , and input . active-low signals are denoted by suffix n . for example, resetn . indicates command line commands and anything that must be typed exactly as it appears. for example, c:\qdesigns\tutorial\chiptrip.gdf . also indicates sections of an actual file, such as a report file, references to parts of files (for example, the ahdl keyword subdesign ), and logic function names (for example, tri ). 1., 2., 3., and a., b., c., and so on. numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. bullets indicate a list of items when the sequence of the items is not important. 1 the hand points to information that requires special attention. c a caution calls attention to a condition or possible situation that can damage or destroy the product or your work. w a warning calls attention to a condition or possible situation that can cause you injury. r the angled arrow instructs you to press enter . f the feet direct you to more information about a particular topic. visual cue meaning